Digitala Vetenskapliga Arkivet

Operational message
There are currently operational disruptions. Troubleshooting is in progress.
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Protecting Remote FPGAs and Embedded Devices from Non-Invasive Physical Attacks
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
2025 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The remote computing market has been growing rapidly for more than ten years, and this growth is expected to continue in the future. A considerable portion of this market is held by data centers, which today offer a diverse range of acceleration technologies for cloud computing, from massive multiprocessing to field-programmable gate arrays (FPGAs). Another significant portion is held by embedded devices in specialized mechanical and electronic systems from motor vehicles to home security systems. Valuable intellectual properties and sensitive information are being deployed in the cloud and embedded devices, which require strong protection. Besides the benefits, the industry’s shift toward remote computing comes with increased vulnerability to physical attacks. FPGAs and embedded devices are among the electronic devices that are most vulnerable to physical attacks, because they may be deployed in a location physically accessible by potential adversaries. This thesis aims to protect FPGAs and embedded devices from physical attacks by exploring the boundaries of possible attack vectors and introducing new countermeasures.

This thesis contains six research papers. The first paper presents an FPGA implementation of a novel arbiter physically unclonable function (PUF) with 4×4 switch blocks. The PUF provides a more resource-efficient solution to secure key generation and storage on FPGAs. The second paper presents near-field electromagnetic deep learning-based side-channel analysis performed on Raspberry Pi 3, a widely-used single-board computer. The paper investigates the generalizability of side-channel analysis by focusing on the extraction of data in memory operations.  The third and fourth papers present covert transmitting antennas and covert near-field EM sensors, respectively, both implemented entirely within the FPGA configurable fabric. The results highlight wireless covert channels as a plausible attack vector for cloud FPGAs and point to the need for further research on the topic. The fifth paper aims to improve IP security in FPGA clouds by introducing circuit disguise, a new method that enables FPGA design checks to be performed in the cloud without requiring the disclosure of the clients’ unprotected designs. Last but not least, the sixth paper presents a hybrid method for fingerprinting neural networks by combining power side-channel measurements with information domain metrics.

Abstract [sv]

Marknaden för fjärrberäkning har vuxit snabbt i över tio år, och denna tillväxt förväntas fortsätta i framtiden. En betydande del av marknaden innehas av datacenter, som idag erbjuder ett brett utbud av accelerationstekniker för molnberäkning, från massiv multiprocessering till på-plats-programmerbar grindmatriser (FPGAs). En annan viktig del utgörs av inbyggda enheter i specialiserade mekaniska och elektroniska system, från motorfordon till hemlarmsystem. Värdefulla immateriella tillgångar (IP) och känslig information distribueras i molnet och i inbyggda enheter, vilket kräver starkt skydd.  Förutom fördelarna medför industrins övergång till fjärrberäkning också en ökad sårbarhet för fysiska attacker.  FPGAs och inbyggda enheter är bland de elektroniska enheter som är mest sårbara för fysiska attacker, eftersom de kan placeras på platser som är fysiskt tillgängliga för potentiella angripare.  Denna avhandling syftar till att skydda FPGAs och inbyggda enheter mot fysiska attacker genom att undersöka gränserna för möjliga attackvektorer och introducera nya motåtgärder.

Avhandlingen innehåller sex forskningsartiklar.  Den första artikeln presenterar en FPGA-implementering av en ny typ av arbiter-baserad fysiskt icke-klonbar funktion (PUF) med 4×4 switchblock. Denna PUF erbjuder en mer resurseffektiv lösning för säker nyckelgenerering och lagring på FPGA.  Den andra artikeln presenterar närfälts elektromagnetisk djupinlärningsbaserad sidokanalsanalys utförd på Raspberry Pi 3, en allmänt använd enkortsdator. Artikeln undersöker generaliserbarheten av sidokanalsanalyser med fokus på extrahering av data i minnesoperationer.  Den tredje och fjärde artikeln presenterar dolda sändarantennor respektive dolda närfälts EM-sensorer, båda helt implementerade inom FPGAs konfigurerbara struktur. Resultaten belyser trådlösa dolda kanaler som en trovärdig attackvektor för moln-FPGAs och pekar på behovet av vidare forskning inom området.  Den femte artikeln syftar till att förbättra IP-säkerheten i moln-FPGAs genom att introducera "circuit disguise", en ny metod som möjliggör verifiering av FPGA-designer i molnet utan att klienternas oskyddade designer behöver avslöjas.  Slutligen presenterar den sjätte artikeln en hybridmetod för fingeravtrycksbestämning av neurala nätverk genom att kombinera effektsidokanalsmätningar med informationsdomänmetrik.

Abstract [tr]

Uzaktan hesaplama pazarı, on yılı aşkın süredir hızla büyümekte ve bu büyümenin önümüzdeki yıllarda da devam etmesi beklenmektedir. Günümüzde, pazarın önemli bir kısmını, çok çekirdekli işlemcilerden alanda programlanabilir kapı dizilerine (FPGA'lar) kadar çeşitli hızlandırma teknolojileri sunan veri merkezleri oluşturmaktadır. Diğer bir önemli kısmını ise, motorlu taşıtlardan ev güvenlik sistemlerine kadar özel amaçlı mekanik ve elektronik sistemlerde kullanılan gömülü cihazlar oluşturmaktadır. Bulut ortamında ve gömülü sistemlerde kullanılan değerli fikrî mülkiyetler ve hassas veriler, güçlü güvenlik önlemleri gerektirmektedir.  Uzaktan hesaplamaya geçiş, sağladığı avantajların yanı sıra, fiziksel saldırılara karşı artan bir savunmasızlığı da beraberinde getirmiştir. FPGA'lar ve gömülü cihazlar, potansiyel saldırganların fiziksel erişimine açık ortamlara yerleştirilebildikleri için, fiziksel saldırılara karşı en savunmasız elektronik donanımlar arasında yer almaktadır.  Bu tez, FPGA’lar ve gömülü cihazları fiziksel saldırılara karşı korumayı amaçlamakta; bu doğrultuda, olası saldırı vektörlerinin sınırlarını inceleyip yeni karşı önlemler geliştirmeyi hedeflemektedir.

Tez altı adet araştırma makalesini içermektedir.  İlk makale, 4×4 anahtar bloklarıyla tasarlanmış, yeni bir tür arbiter tabanlı fiziksel klonlanamayan fonksiyonun (PUF) FPGA üzerindeki uygulamasını sunmaktadır. Bu PUF, FPGA üzerinde güvenli anahtar üretimi ve depolanması için daha verimli bir çözüm sunmaktadır.  İkinci makale, yaygın olarak kullanılan tek kartlı bilgisayarlardan Raspberry Pi 3 üzerinde gerçekleştirilen, yakın alan elektromanyetik ölçümlere dayalı derin öğrenme tabanlı yan kanal incelemelerini ele almaktadır. Bu çalışma, özellikle bellek işlemlerinden veri çıkarımı konusuna odaklanarak, bu tür incelemelerin genellenebilirliğini araştırmaktadır.  Üçüncü ve dördüncü makalelerde, tamamen FPGA'nın ayarlanabilir donanımı içerisinde gerçekleştirilen gizli iletim antenleri ve gizli yakın alan elektromanyetik sensörler tanıtılmaktadır. Elde edilen sonuçlar, kablosuz gizli kanalların bulut tabanlı FPGA’lar için gerçek bir saldırı vektörü oluşturabileceğini göstermekte ve bu alanda daha fazla araştırmaya ihtiyaç olduğunu ortaya koymaktadır.  Beşinci makale, bulut FPGA’larında fikrî mülkiyet güvenliğini artırmak amacıyla, "devre kamuflajı" adını taşıyan yeni bir yöntem önermektedir. Bu yöntem, müşterilerin korumasız tasarımlarını ifşa etmeden FPGA tasarımlarının bulutta doğrulanabilmesini mümkün kılmaktadır.  Son olarak, altıncı makale, sinir ağlarının parmak izi tespitine yönelik olarak güç yan kanal ölçümleriyle bilgi alanı metriklerini birleştiren hibrit bir yöntem sunmaktadır.

Place, publisher, year, edition, pages
KTH Royal Institute of Technology, 2025. , p. 64
Series
TRITA-EECS-AVL ; 2025:59
Keywords [en]
FPGA security, embedded systems security, cloud security, physically unclonable functions, side-channel attacks, covert-channel attacks, neural network fingerprinting
Keywords [sv]
FPGA-säkerhet, säkerhet i inbyggda system, molnsäkerhet, fysiskt icke-klonbara funktioner (PUF), sidokanalattacker, dolda kanalattacker, fingeravtrycksbestämning av neurala nätverk
Keywords [tr]
FPGA güvenliği, gömülü sistemler güvenliği, bulut güvenliği, fiziksel klonlanamayan fonksiyonlar (PUF), yan kanal saldırıları, gizli kanal saldırıları, sinir ağı parmak izi tespiti
National Category
Embedded Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
URN: urn:nbn:se:kth:diva-363344ISBN: 978-91-8106-294-6 (print)OAI: oai:DiVA.org:kth-363344DiVA, id: diva2:1958212
Public defence
2025-06-11, https://kth-se.zoom.us/j/65431729410?ampDeviceId=f2e64df5-2699-4de4-a189-7ed11bea93d9&ampSessionId=1747228554863, Ka-Sal C, Kistagången 16, 164 40 Kista, Sweden, Stockholm, 09:00 (English)
Opponent
Supervisors
Funder
VinnovaSwedish Research Council
Note

QC 20250514

Available from: 2025-05-14 Created: 2025-05-14 Last updated: 2025-06-30Bibliographically approved
List of papers
1. An FPGA Implementation of 4x4 Arbiter PUF
Open this publication in new window or tab >>An FPGA Implementation of 4x4 Arbiter PUF
2021 (English)In: 2021 IEEE 51st international symposium on multiple-valued logic (ISMVL 2021), Institute of Electrical and Electronics Engineers (IEEE) , 2021, p. 160-165Conference paper, Published paper (Refereed)
Abstract [en]

The need of protecting data and bitstreams increases in computation environments such as FPGA as a Service (FaaS). Physically Unclonable Functions (PUFs) have been proposed as a solution to this problem. In this paper, we present an implementation of Arbiter PUF with 4 x 4 switch blocks in Xilinx Series 7 FPGA, perform its statistical analysis, and compare it to other Arbiter PUF variants. We show that the presented implementation utilizes five times less area than 2 x 2 Arbiter PUF-based implementations. It is suitable for many real-world applications, including identification, authentication, key provisioning, and random number generation.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2021
Series
International Symposium on Multiple-Valued Logic, ISSN 0195-623X
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-302615 (URN)10.1109/ISMVL51352.2021.00035 (DOI)000693398200026 ()2-s2.0-85113221218 (Scopus ID)
Conference
51st IEEE International Symposium on Multiple-Valued Logic (ISMVL), MAY 25-27, 2021, ELECTR NETWORK
Note

Part of proceedings: ISBN 978-1-7281-9224-6, QC 20230117

Available from: 2021-10-05 Created: 2021-10-05 Last updated: 2025-05-14Bibliographically approved
2. Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers
Open this publication in new window or tab >>Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers
2022 (English)In: Proceedings of the 2022 IFIP/IEEE 30th international conference on very large scale integration (VLSI-SOC), Institute of Electrical and Electronics Engineers (IEEE) , 2022Conference paper, Published paper (Refereed)
Abstract [en]

Today's power/EM side-channel analysis is limited by the complexity of the target hardware. We investigate the feasibility of power/EM side-channel analysis of general-purpose computers. This paper makes a step towards this goal by analyzing memory operations of Raspberry Pi 3 Model B, a widely used general-purpose IoT device that is capable of running an operating system, and shows that it is possible to extract information about the data field of memory operations from near-field EM measurements.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2022
Keywords
Side-channel attack, electromagnetic trace, memory leakage, deep learning, Raspberry Pi
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-322786 (URN)10.1109/VLSI-SoC54400.2022.9939649 (DOI)000889978800080 ()2-s2.0-85142441523 (Scopus ID)
Conference
30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), OCT 03-05, 2022, Univ Patras, Patras, GREECE
Note

Part of proceedings ISBN 978-1-6654-9005-4

QC 20230207

Available from: 2023-02-07 Created: 2023-02-07 Last updated: 2025-05-14Bibliographically approved
3. Is your FPGA transmitting secrets: covert antennas from interconnect
Open this publication in new window or tab >>Is your FPGA transmitting secrets: covert antennas from interconnect
2023 (English)In: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023, Institute of Electrical and Electronics Engineers (IEEE) , 2023, p. 79-84Conference paper, Published paper (Refereed)
Abstract [en]

A hidden transmitter embedded into a chip to extract secret information is a well-known type of hardware Trojan. Various ways of implementing covert channels have been proposed in the past. The focus of this paper is covert antennas created from the FPGA interconnect. We present several on-chip antenna implementations that leverage the routing resources of FPGAs. The proposed antennas can transmit data processed by the FPGA with bit-level precision. A near-field probe is used to capture the radiated signal and the transmitted data is restored with 100% accuracy. Our results suggest that introducing a routine screening process for covert antennas in FPGA designs, similar to the one performed for ring oscillators, would be of benefit for FPGA security.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Keywords
cloud security, covert antenna, FPGA, hardware Trojan, radio access networks., side-channel attacks
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-336743 (URN)10.1109/IPDPSW59300.2023.00025 (DOI)001055030700010 ()2-s2.0-85169292470 (Scopus ID)
Conference
2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023, May 15 2023 - May 19, 2023, St. Petersburg, United States of America
Note

Part of ISBN 9798350311990

QC 20230919

Available from: 2023-09-19 Created: 2023-09-19 Last updated: 2025-05-14Bibliographically approved
4. A Near-Field EM Sensor Implemented in FPGA Configurable Fabric
Open this publication in new window or tab >>A Near-Field EM Sensor Implemented in FPGA Configurable Fabric
2023 (English)In: Proceedings - 2023 IEEE 22nd International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom/BigDataSE/CSE/EUC/iSCI 2023, Institute of Electrical and Electronics Engineers (IEEE) , 2023, p. 1908-1913Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present the first near-field electro-magnetic (EM) sensor that is entirely implemented in the FPGA configurable fabric, without the use of any peripherals such as analog-to-digital converters, external antennas, or resistor-capacitor circuits. The sensor detects changes in path delays caused by external EM radiation using an antenna (composed of the interconnect) and a time-to-digital converter. A cloud-based FPGA remotely configured with such a sensor may act as a receiving end of a wireless covert channel, e.g., to another FPGA in the neighborhood that does not share any common resources with the receiving FPGA. Thus, our results show the plausibility of an exploitable attack vector for cloud-based FPGA that is not limited to the multi-tenancy scenario.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Keywords
cloud security, covert channel, EM sensor, FPGA, time-to-digital converter
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-348282 (URN)10.1109/TrustCom60117.2023.00259 (DOI)001239879400235 ()2-s2.0-85195460693 (Scopus ID)
Conference
22nd IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2023, November 1-3, 2023, Exeter, United Kingdom of Great Britain and Northern Ireland
Note

Part of ISBN 979-8-3503-8200-6

QC 20241023

Available from: 2024-06-20 Created: 2024-06-20 Last updated: 2025-05-14Bibliographically approved
5. Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure
Open this publication in new window or tab >>Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure
2024 (English)In: Proceedings - 2024 27th Euromicro Conference on Digital System Design, DSD 2024, Institute of Electrical and Electronics Engineers (IEEE) , 2024, p. 361-368Conference paper, Published paper (Refereed)
Abstract [en]

At present, the state-of-the-art cloud FPGA deployment process does not allow the cloud provider to perform design checks for malicious circuits unless the clients' designs are available in an unprotected form. In this paper, we introduce the circuit disguise method that allows the design checks to be performed without disclosing the clients' Intellectual Property (IP). The method is based on a lossy circuit transformation that generates a compressed version of the netlist specifying the client's design. While the design checks can still be performed on the compressed version of the netlist, reversing the transformation to recover the original design is not possible. The circuit disguise method can be used in combination with bitstream encryption. This enables the clients to protect not only the designs but also the bitstreams. Furthermore, with circuit disguise, new design checks can be performed on designs that are already compiled into a protected bitstream. We present an implementation of the circuit disguise method and demonstrate its effectiveness with various benign and malicious benchmark designs. The implementation is publicly available.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2024
Keywords
cloud security, DoS attack, FPGA, side-channel attacks, Trojans, trusted computing
National Category
Computer Sciences
Identifiers
urn:nbn:se:kth:diva-358135 (URN)10.1109/DSD64264.2024.00055 (DOI)001414927800046 ()2-s2.0-85211894946 (Scopus ID)
Conference
27th Euromicro Conference on Digital System Design, DSD 2024, Paris, France, Aug 28 2024 - Aug 30 2024
Note

Part of ISBN 979-8-3503-8038-5

QC 20250107

Available from: 2025-01-07 Created: 2025-01-07 Last updated: 2025-05-14Bibliographically approved
6. Hybrid Fingerprinting for Effective Detection of Cloned Neural Networks
Open this publication in new window or tab >>Hybrid Fingerprinting for Effective Detection of Cloned Neural Networks
Show others...
(English)Manuscript (preprint) (Other academic)
Abstract [en]

As artificial intelligence plays an increasingly important role in decision-making within critical infrastructure, ensuring the authenticity and integrity of neural networks is crucial. This paper addresses the problem of detecting cloned neural networks. We present a method for identifying clones that employs a combination of metrics from both the information and physical domains: output predictions, probability score vectors, and power traces measured from the device running the neural network during inference. We compare the effectiveness of each metric individually, as well as in combination. Our results show that the effectiveness of both the information and the physical domain metrics is excellent for a clone that is a near replica of the target neural network. Furthermore, both the physical domain metric individually and the hybrid approach outperformed the information domain metrics at detecting clones whose weights were extracted with low accuracy. The presented method offers a practical solution for verifying neural network authenticity and integrity. It is particularly useful in scenarios where neural networks are at risk of model extraction attacks, such as in cloud-based machine learning services.

Keywords
fingerprinting, neural networks, intellectual property, model extraction, power side channels
National Category
Communication Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-363339 (URN)
Funder
Vinnova, 2023-00221Swedish Civil Contingencies Agency, 2020-11632
Note

QC 20250513

Available from: 2025-05-13 Created: 2025-05-13 Last updated: 2025-05-14Bibliographically approved

Open Access in DiVA

Kappa(4670 kB)366 downloads
File information
File name FULLTEXT01.pdfFile size 4670 kBChecksum SHA-512
0b98e1754aad25bd9ce28f51e6ac49ef0e9d80bf3558ed4175e32f443d7cf2174bc268c5ef463756d80a3970899fd3ef7026d1d0442ce39267a2fa30af211b00
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
Aknesil, Can
By organisation
Electronics and Embedded systems
Embedded SystemsOther Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 368 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

isbn
urn-nbn

Altmetric score

isbn
urn-nbn
Total: 3044 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf