Endre søk
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
A Cyclic Analog to Digital Converter for CMOS image sensors
Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
2014 (engelsk)Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
Abstract [en]

The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power.

In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel readout implementation in CMOS image sensors is presented. The aim of the conducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the performance of the carried-out design have been analyzed. As an architectural improvement possibility two MDAC capacitor mismatch error reduction techniques have been presented.

 

 

sted, utgiver, år, opplag, sider
2014. , s. 112
Emneord [en]
CMOS, Image Sensor, ADC, Cyclic ADC, Algorithmic ADC, MDAC, Switched Capacitor, Comparator, OTA, Logic, IC, VLSI, Circuit, System
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-103193ISRN: LiTH-ISY-EX--13/4674--SEOAI: oai:DiVA.org:liu-103193DiVA, id: diva2:687644
Fag / kurs
Electronics Systems
Presentation
2013-06-12, Nollstället, Linköping University, B:25, Campus Valla, Linköping, 12:00 (engelsk)
Veileder
Examiner
Tilgjengelig fra: 2014-03-04 Laget: 2014-01-14 Sist oppdatert: 2014-03-04bibliografisk kontrollert

Open Access i DiVA

MScThesis-LiTH-ISY-EX--13-4674--SE-D_Levski(5815 kB)6175 nedlastinger
Filinformasjon
Fil FULLTEXT01.pdfFilstørrelse 5815 kBChecksum SHA-512
0d3cedc26f8dd261d85a4a111fdfc9050b4d6bc287f5bdaebabd0a3c23880717901d998d5fa14c45ac6ba33f5fb09e0a8d25c304f537ae064f6f6a6f0b3cd084
Type fulltextMimetype application/pdf

Søk i DiVA

Av forfatter/redaktør
Levski Dimitrov, Deyan
Av organisasjonen

Søk utenfor DiVA

GoogleGoogle Scholar
Totalt: 6175 nedlastinger
Antall nedlastinger er summen av alle nedlastinger av alle fulltekster. Det kan for eksempel være tidligere versjoner som er ikke lenger tilgjengelige

urn-nbn

Altmetric

urn-nbn
Totalt: 1091 treff
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf