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  • 1.
    A Elhassan, Amro
    KTH, School of Electrical Engineering (EES).
    Building automation and control2012Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
  • 2.
    A, Fredrik
    et al.
    KTH, School of Electrical Engineering (EES).
    Forsberg, A
    KTH, School of Electrical Engineering (EES).
    Forsén, Tobias
    KTH, School of Electrical Engineering (EES).
    Tracking Using Wireless Camera Networks2015Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
  • 3.
    A. M. Naiini, Maziar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Horizontal Slot Waveguides for Silicon Photonics Back-End Integration2014Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    This thesis presents the development of integrated silicon photonic devices. These devices are compatible with the present and near future CMOS technology. High-khorizontal grating couplers and waveguides are proposed. This work consists of simulations and device design, as well as the layout for the fabrication process, device fabrication, process development, characterization instrument development and electro-optical characterizations.

    The work demonstrates an alternative solution to costly silicon-on-insulator photonics. The proposed solution uses bulk silicon wafers and thin film deposited waveguides. Back-end deposited horizontal slot grating couplers and waveguides are realized by multi-layers of amorphous silicon and high-k materials.

    The achievements of this work include: A theoretical study of fully etched slot grating couplers with Al2O3, HfO2 and AIN, an optical study of the high-k films with spectroscopic ellipsometry, an experimental demonstration of fully etched SiO2 single slot grating couplers and double slot Al2O3 grating couplers, a practical demonstration of horizontal double slot high-k waveguides, partially etched Al2O3 single slot grating couplers, a study of a scheme for integration of the double slot Al2O3  waveguides with selectively grown germanium PIN photodetectors, realization of test chips for the integrated germanium photodetectors, and study of integration with graphene photodetectors through embedding the graphene into a high-k slot layer.

    From an application point of view, these high-k slot waveguides add more functionality to the current silicon photonics. The presented devices can be used for low cost photonics applications. Also alternative optical materials can be used in the context of this photonics platform.

    With the robust design, the grating couplers result in improved yield and a more cost effective solution is realized for integration of the waveguides with the germanium and graphene photodetectors.

     

     

     

     

  • 4.
    A. Sani, Negar
    Linköping University, Department of Science and Technology, Physics and Electronics.
    M-PSK and M-QAM Modulation/Demodulation of UWB Signal Using Six-Port Correlator2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Nowadays high speed and high data rate communication are highly demanded. Consequently, wideband and high frequency transmitter and receivers should be designed. New transmitters and receivers should also have low power consumption, simple design and low manufacturing price in order to fulfill manufacturers’ requests for mass production. Having all above specifications, six-port correlator is a proper choice to be used as modulator and demodulator in transmitters and receivers.

    In this thesis the six-port correlator is introduced, modeled and simulated using Advanced Design System (ADS) software. A simple six-port transmitter/receiver system with a line of sight link is modeled and analyzed in BER, path length and noise terms. The modulation in this system is QAM, frequency is 7.5 GHz and symbol rate is 500 Msymbol/s.

    Furthermore two methods are proposed for high frequency and high symbol rate M-PSK and M-QAM modulation using six-port correlator. The 7.5 GHz modulators are modeled and simulated in ADS. Data streams generated by pseudo random bit generator with 1 GHz bandwidth are applied to modulators. Common source field effect transistors (FETs) with zero bias are used as controllable impedance termination to apply baseband data to modulator. Both modulators show good performance in M-PSK and M-QAM modulation.

  • 5.
    Aagaard Fransson, Erik Johannes
    et al.
    KTH, School of Electrical Engineering (EES), Electromagnetic Engineering.
    Wall-Horgen, Tobias
    KTH, School of Electrical Engineering (EES), Electromagnetic Engineering.
    Building and Evaluating a 3D Scanning System for Measurementsand Estimation of Antennas and Propagation Channels2012Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Wireless communications rely, among other things, on theunderstanding of the properties of the radio propagationchannel, the antennas and their interplay. Adequate measurementsare required to verify theoretical models and togain knowledge of the channel behavior and antenna performance.As a result of this master thesis we built a 3D fieldscanner measurement system to predict multipath propagationand to measure antenna characteristics. The 3Dscanner allows measuring a signal at the point of interestalong a line, on a surface or within a volume in space. In orderto evaluate the system, we have performed narrowbandchannel sounding measurements of the spatial distributionof waves impinging at an imaginary spherical sector. Datawas used to estimate the Angle-of-Arrivals (AoA) and amplitudeof the waves. An estimation method is presented tosolve the resulting inverse problem by means of regularizationwith truncated singular value decomposition. The regularizedsolution was then further improved with the helpof a successive interference cancellation algorithm. Beforeapplying the method to measurement data, it was testedon synthetic data to evaluate its performance as a functionof the noise level and the number of impinging waves. Inorder to minimize estimation errors it was also required tofind the phase center of the horn antenna used in the channelmeasurements. The task was accomplished by directmeasurements and by the regularization method, both resultsbeing in good agreement.

  • 6.
    Aamir, Syed Ahmed
    Linköping University. Linköping University, Department of Electrical Engineering.
    A 65nm, Low Voltage, Fully Differential, SC Programmable Gain Amplifier for Video AFE2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Due to rapid growth of home entertainment consumer market, video technology has been continuously pushed to deliver sharper pictures with higher resolution. This has brought about stringent requirements on the video analog front end, which often coupled with the low power and low voltage regulations had to deal with short channel effects of the deep submicron CMOS processes.

    This thesis presents the design of a fully differential programmable gain amplifier, as a subcircuit of a larger video digitizing IC designed at division of Electronic Systems. The switched capacitor architecture of the PGA does not only buffer the signal, but performs compensation for the sync-tip of analog video signal.

    The pseudo differential OTA eliminates tail current source and maintains high signal swing and has efficient common mode feedforward mechanism. When coupled with a similar stage provides inherent common moode feedback without using an additional SC-CMFB block.

    The PGA has been implemented using a 65 nm digital CMOS process. Expected difficulties in a 1.2 V OTA design make themselves evident in 65 nm, which is why cascaded OTA structures were inevitable for attaining gain specification of 60 dB. Nested Miller compensation with a pole shifting source follower, stabilizes the multipole system. The final circuit attains up to 200 MHz bandwidth and maintains high output swing of 0.85 V. High slew rate and good common mode and power supply rejection are observed. Noise requirements require careful design of input differential stage. Although output source follower stabilized the system, it reduces significant bandwidth and adds to second order non-linearity.

  • 7.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS2010In: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10, Tampere: www.ieee.org , 2010, 1-4 p.Conference paper (Refereed)
    Abstract [en]

    This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.

  • 8.
    Aamir, Syed Ahmed
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, J Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS2010In: 17th IEEE International Conference on Electronics, Circuits, and Systems., www.ieee.org , 2010, 29-32 p.Conference paper (Refereed)
    Abstract [en]

    In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inher­ent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inher­ent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit de­vices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.

  • 9.
    Aarno, Daniel
    et al.
    KTH, School of Computer Science and Communication (CSC), Computer Vision and Active Perception, CVAP. KTH, School of Computer Science and Communication (CSC), Centres, Centre for Autonomous Systems, CAS.
    Ekvall, Staffan
    KTH, School of Computer Science and Communication (CSC), Computer Vision and Active Perception, CVAP. KTH, School of Computer Science and Communication (CSC), Centres, Centre for Autonomous Systems, CAS.
    Kragic, Danica
    KTH, School of Computer Science and Communication (CSC), Computer Vision and Active Perception, CVAP. KTH, School of Computer Science and Communication (CSC), Centres, Centre for Autonomous Systems, CAS.
    Adaptive virtual fixtures for machine-assisted teleoperation tasks2005In: 2005 IEEE International Conference on Robotics and Automation (ICRA), Vols 1-4, 2005, 1139-1144 p.Conference paper (Refereed)
    Abstract [en]

    It has been demonstrated in a number of robotic areas how the use of virtual fixtures improves task performance both in terms of execution time and overall precision, [1]. However, the fixtures are typically inflexible, resulting in a degraded performance in cases of unexpected obstacles or incorrect fixture models. In this paper, we propose the use of adaptive virtual fixtures that enable us to cope with the above problems. A teleoperative or human machine collaborative setting is assumed with the core idea of dividing the task, that the operator is executing, into several subtasks. The operator may remain in each of these subtasks as long as necessary and switch freely between them. Hence, rather than executing a predefined plan, the operator has the ability to avoid unforeseen obstacles and deviate from the model. In our system, the probability that the user is following a certain trajectory (subtask) is estimated and used to automatically adjusts the compliance. Thus, an on-line decision of how to fixture the movement is provided.

  • 10.
    Aarno, Daniel
    et al.
    KTH, School of Computer Science and Communication (CSC), Centres, Centre for Autonomous Systems, CAS. KTH, School of Computer Science and Communication (CSC), Computer Vision and Active Perception, CVAP.
    Kragic, Danica
    KTH, School of Computer Science and Communication (CSC), Centres, Centre for Autonomous Systems, CAS. KTH, School of Computer Science and Communication (CSC), Computer Vision and Active Perception, CVAP.
    Layered HMM for motion intention recognition2006In: 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, Vols 1-12, NEW YORK: IEEE , 2006, 5130-5135 p.Conference paper (Refereed)
    Abstract [en]

    Acquiring, representing and modeling human skins is one of the key research areas in teleoperation, programming. by-demonstration and human-machine collaborative settings. One of the common approaches is to divide the task that the operator is executing into several subtasks in order to provide manageable modeling. In this paper we consider the use of a Layered Hidden Markov Model (LHMM) to model human skills. We evaluate a gestem classifier that classifies motions into basic action-primitives, or gestems. The gestem classifiers are then used in a LHMM to model a simulated teleoperated task. We investigate the online and offline classilication performance with respect to noise, number of gestems, type of HAIM and the available number of training sequences. We also apply the LHMM to data recorded during the execution of a trajectory-tracking task in 2D and 3D with a robotic manipulator in order to give qualitative as well as quantitative results for the proposed approach. The results indicate that the LHMM is suitable for modeling teleoperative trajectory-tracking tasks and that the difference in classification performance between one and multi dimensional HMMs for gestem classification is small. It can also be seen that the LHMM is robust w.r.t misclassifications in the underlying gestem classifiers.

  • 11. Aarts, Fides
    et al.
    Jonsson, Bengt
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Uijen, Johan
    Vaandrager, Frits
    Generating models of infinite-state communication protocols using regular inference with abstraction2015In: Formal methods in system design, ISSN 0925-9856, E-ISSN 1572-8102, Vol. 46, no 1, 1-41 p.Article in journal (Refereed)
    Abstract [en]

    In order to facilitate model-based verification and validation, effort is underway to develop techniques for generating models of communication system components from observations of their external behavior. Most previous such work has employed regular inference techniques which generate modest-size finite-state models. They typically suppress parameters of messages, although these have a significant impact on control flow in many communication protocols. We present a framework, which adapts regular inference to include data parameters in messages and states for generating components with large or infinite message alphabets. A main idea is to adapt the framework of predicate abstraction, successfully used in formal verification. Since we are in a black-box setting, the abstraction must be supplied externally, using information about how the component manages data parameters. We have implemented our techniques by connecting the LearnLib tool for regular inference with an implementation of session initiation protocol (SIP) in ns-2 and an implementation of transmission control protocol (TCP) in Windows 8, and generated models of SIP and TCP components.

  • 12.
    Abad Caballero, Israel Manuel
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Secure Mobile Voice over IP2003Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Voice over IP (VoIP) can be defined as the ability to make phone calls and to send faxes (i.e., to do everything we can do today with the Public Switched Telephone Network, PSTN) over IP−based data networks with a suitable quality of service and potentially a superior cost/benefit ratio. There is a desire to provide (VoIP) with the suitable security without effecting the performance of this technology. This becomes even more important when VoIP utilizes wireless technologies as the data networks (such as Wireless Local Area Networks, WLAN), given the bandwidth and other constraints of wireless environments, and the data processing costs of the security mechanisms. As for many other (secure) applications, we should consider the security in Mobile VoIP as a chain, where every link, from the secure establishment to the secure termination of a call, must be secure in order to maintain the security of the entire process.

    This document presents a solution to these issues, providing a secure model for Mobile VoIP that minimizes the processing costs and the bandwidth consumption. This is mainly achieved by making use of high− throughput, low packet expansion security protocols (such as the Secure Real−Time Protocol, SRTP); and high−speed encryption algorithms (such as the Advanced Encryption Standard, AES).

    In the thesis I describe in detail the problem and its alternative solutions. I also describe in detail the selected solution and the protocols and mechanisms this solution utilizes, such as the Transport Layer Security (TLS) for securing the Session Initiation Protocol (SIP), the Real−Time Protocol (RTP) profile Secure Real−Time Protocol (SRTP) for securing the media data transport , and the Multimedia Internet KEYing (MIKEY) as the key−management protocol. Moreover, an implementation of SRTP, called MINIsrtp, is also provided. The oral presentation will provide an overview of these topics, with an in depth examination of those parts which were the most significant or unexpectedly difficult.

    Regarding my implementation, evaluation, and testing of the model, this project in mainly focused on the security for the media stream (SRTP). However, thorough theoretical work has also been performed and will be presented, which includes other aspects, such as the establishment and termination of the call (using SIP) and the key−management protocol (MIKEY).

  • 13.
    Abad Camarero, Daniel
    KTH, School of Electrical Engineering (EES), Communication Networks.
    Performance analysis of IPv4 / IPv6 protocols over the third generation mobile network2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Currently, the IPv4 protocol is heavily used by institutions, companies and individuals, but every day there is a higher number of devices connected to the network such as home appliances, mobile phones or tablets. Each machine or device needs to have its own IP address to communicate with other machines connected to Internet. This implies the need for multiple IP addresses for a single user and the current protocol begins to show some deficiencies due to IPv4 address space exhaustion. Therefore, for several years experts have been working on an IP protocol update: the IPv6 128-bit version can address up to about 340 quadrillion system devices concurrently. With IPv6, today, every person on the planet could have millions of devices simultaneously connected to the Internet.

    The choice of the IP protocol version affects the performance of the UMTS mobile network and the browsers as well. The aim of the project is to measure how the IPv6 protocol performs compared to the previous IPv4 protocol. It is expected that the IPv6 protocol generates a smaller amount of signalling and less time is required to fully load a web page. We have analysed some KPIs (IP data, signalling, web load time and battery) in lab environment using Smartphones, to observe the behaviour of both, the network and the device.  The main conclusion of the thesis is that IPv6 really behaves as expected and generates savings in signalling, although the IP data generated is larger due to the size of the headers. However, there is still much work as only the most important webpages and the applications with a high level of market penetration operate well over the IPv6 protocol.

  • 14. Abadal, Sergi
    et al.
    Alarcon, Eduard
    Cabellos-Aparicio, Albert
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Nemirovsky, Mario
    Graphene-Enabled Wireless Communication for Massive Multicore Architectures2013In: IEEE Communications Magazine, ISSN 0163-6804, E-ISSN 1558-1896, Vol. 51, no 11, 137-143 p.Article in journal (Refereed)
    Abstract [en]

    Current trends in microprocessor architecture design are leading towards a dramatic increase of core-level parallelization, wherein a given number of independent processors or cores are interconnected. Since the main bottleneck is foreseen to migrate from computation to communication, efficient and scalable means of inter-core communication are crucial for guaranteeing steady performance improvements in many-core processors. As the number of cores grows, it remains unclear whether initial proposals, such as the Network-on-Chip (NoC) paradigm, will meet the stringent requirements of this scenario. This position paper presents a new research area where massive multicore architectures have wireless communication capabilities at the core level. This goal is feasible by using graphene-based planar antennas, which can radiate signals at the Terahertz band while utilizing lower chip area than its metallic counterparts. To the best of our knowledge, this is the first work that discusses the utilization of graphene-enabled wireless communication for massive multicore processors. Such wireless systems enable broadcasting, multicasting, all-to-all communication, as well as significantly reduce many of the issues present in massively multicore environments, such as data coherency, consistency, synchronization and communication problems. Several open research challenges are pointed out related to implementation, communications and multicore architectures, which pave the way for future research in this multidisciplinary area.

  • 15.
    Abari, Farzad Foroughi
    Blekinge Institute of Technology, School of Engineering, Department of Signal Processing.
    Optimization of Audio Processing algorithms (Reverb) on ARMv6 family of processors2008Independent thesis Advanced level (degree of Master (Two Years))Student thesis
    Abstract [en]

    Audio processing algorithms are increasingly used in cell phones and today’s customers are placing more demands on cell phones. Feature phones, once the advent of mobile phone technology, nowadays do more than just providing the user with MP3 play back or advanced audio effects. These features have become an integral part of medium as well as low-end phones. On the other hand, there is also an endeavor to include as improved quality as possible into products to compete in market and satisfy users’ needs. Tackling the above requirements has been partly satisfied by the advance in hardware design and manufacturing technology. However, as new hardware emerges into market the need for competence to write efficient software and exploit the new features thoroughly and effectively arises. Even though compilers are also keeping up with the new tide space for hand optimized code still exist. Wrapped in the above goal, an effort was made in this thesis to partly cover the competence requirement at Multimedia Section (part of Ericsson Mobile Platforms) to develope optimized code for new processors. Forging persistently ahead with new products, EMP has always incorporated the latest technology into its products among which ARMv6 family of processors has the main central processing role in a number of upcoming products. To fully exploit latest features provided by ARMv6, it was required to probe its new instruction set among which new media processing instructions are of outmost importance. In order to execute DSP-intensive algorithms (e.g. Audio Processing algorithms) efficiently, the implementation should be done in low-level code applying available instruction set. Meanwhile, ARMv6 comes with a number of new features in comparison with its predecessors. SIMD (Single Instruction Multiple Data) and VFP (Vector Floating Point) are the most prominent media processing improvements in ARMv6. Aligned with thesis goals and guidelines, Reverb algorithm which is among one of the most complicated audio features on a hand-held devices was probed. Consequently, its kernel parts were identified and implementation was done both in fixed-point and floating-point using the available resources on hardware. Besides execution time and amount of code memory for each part were measured and provided in tables and charts for comparison purposes. Conclusions were finally drawn based on developed code’s efficiency over ARM compiler’s as well as existing code already developed and tailored to ARMv5 processors. The main criteria for optimization was the execution time. Moreover, quantization effect due to limited precision fixed-point arithmetic was formulated and its effect on quality was elaborated. The outcomes, clearly indicate that hand optimization of kernel parts are superior to Compiler optimized alternative both from the point of code memory as well as execution time. The results also confirmed the presumption that hand optimized code using new instruction set can improve efficiency by an average 25%-50% depending on the algorithm structure and its interaction with other parts of audio effect. Despite its many draw backs, fixed-point implementation remains yet to be the dominant implementation for majority of DSP algorithms on low-power devices.

  • 16.
    Abbaraju, Nanda
    Jönköping University, School of Engineering.
    Sending and Receiving Data between Mobile and Data Logger2008Independent thesis Advanced level (degree of Master (One Year)), 20 credits / 30 HE creditsStudent thesis
  • 17.
    Abbas, Azhar
    Karlstad University, Faculty of Technology and Science.
    GPIB- kommunikation och PID reglering med LabVIEW2009Independent thesis Basic level (university diploma), 15 credits / 22,5 HE creditsStudent thesis
    Abstract [sv]

    LabVIEW ger en snabb och enkel tillgång till att styra instrument och en mycket stor databas med drivrutiner för DAQ-kort och olika datorgränssnitt (GPIB, serie, osv.).

    Många instrument och datorer kan anslutas till GPIB-bussen.  Detta kan ge en praktisk modell för utveckling av instrumentets styrprogram i LabVIEW med hjälp av GPIB-gränssnittet.

    Ett program i LabVIEW 8.2 med hjälp av GPIB-bussen kan kopplas till t.ex. multimetern (HP-34401A) för att mäta och visa multimeters noggrannhet. Men på grund av fel i drivrutiner för GPIB-gränssnittet kunde jag inte köra programmet med GPIB-bussen.

    Genom att använda LabVIEW 8.2 med hjälp av DAQ-kort kan en PID-regleringsalgoritm simuleras. PID konstrueras med virtuella instrument som innehåller alla nödvändiga komponenter och utrustning som krävs för att reglera någon linjär eller olinjär process exempelvis att nivåreglera två tankar i serie. Här stöter vi på alla de grundläggande regulatorer och får möjlighet att bygga PID med LabVIEW på ett enkelt sätt. Det finns två metoder för att bygga PID. Den första är med matematiska funktioner och den andra är med ’’Simulations functions control’’. Arbetet visar att bägge metoderna fungerar bra för att lösa uppgiften jämfört med färdiga PID-controls på LabVIEW.

  • 18.
    Abbas, Muhammad
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On the Implementation of Integer and Non-Integer Sampling Rate Conversion2012Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The main focus in this thesis is on the aspects related to the implementation of integer and non-integer sampling rate conversion (SRC). SRC is used in many communication and signal processing applications where two signals or systems having different sampling rates need to be interconnected. There are two basic approaches to deal with this problem. The first is to convert the signal to analog and then re-sample it at the desired rate. In the second approach, digital signal processing techniques are utilized to compute values of the new samples from the existing ones. The former approach is hardly used since the latter one introduces less noise and distortion. However, the implementation complexity for the second approach varies for different types of conversion factors. In this work, the second approach for SRC is considered and its implementation details are explored. The conversion factor in general can be an integer, a ratio of two integers, or an irrational number. The SRC by an irrational numbers is impractical and is generally stated for the completeness. They are usually approximated by some rational factor.

    The performance of decimators and interpolators is mainly determined by the filters, which are there to suppress aliasing effects or removing unwanted images. There are many approaches for the implementation of decimation and interpolation filters, and cascaded integrator comb (CIC) filters are one of them. CIC filters are most commonly used in the case of integer sampling rate conversions and often preferred due to their simplicity, hardware efficiency, and relatively good anti-aliasing (anti-imaging) characteristics for the first (last) stage of a decimation (interpolation). The multiplierless nature, which generally yields to low power consumption, makes CIC filters well suited for performing conversion at higher rate. Since these filters operate at the maximum sampling frequency, therefore, are critical with respect to power consumption. It is therefore necessary to have an accurate and efficient ways and approaches that could be utilized to estimate the power consumption and the important factors that are contributing to it. Switching activity is one such factor. To have a high-level estimate of dynamic power consumption, switching activity equations in CIC filters are derived, which may then be used to have an estimate of the dynamic power consumption. The modeling of leakage power is also included, which is an important parameter to consider since the input sampling rate may differ several orders of magnitude. These power estimates at higher level can then be used as a feed-back while exploring multiple alternatives.

    Sampling rate conversion is a typical example where it is required to determine the values between existing samples. The computation of a value between existing samples can alternatively be regarded as delaying the underlying signal by a fractional sampling period. The fractional-delay filters are used in this context to provide a fractional-delay adjustable to any desired value and are therefore suitable for both integer and non-integer factors. The structure that is used in the efficient implementation of a fractional-delay filter is know as Farrow structure or its modifications. The main advantage of the Farrow structure lies in the fact that it consists of fixed finite-impulse response (FIR) filters and there is only one adjustable fractional-delay parameter, used to evaluate a polynomial with the filter outputs as coefficients. This characteristic of the Farrow structure makes it a very attractive structure for the implementation. In the considered fixed-point implementation of the Farrow structure, closed-form expressions for suitable word lengths are derived based on scaling and round-off noise. Since multipliers share major portion of the total power consumption, a matrix-vector multiple constant multiplication approach is proposed to improve the multiplierless implementation of FIR sub-filters.

    The implementation of the polynomial part of the Farrow structure is investigated by considering the computational complexity of different polynomial evaluation schemes. By considering the number of operations of different types, critical path, pipelining complexity, and latency after pipelining, high-level comparisons are obtained and used to short list the suitable candidates. Most of these evaluation schemes require the explicit computation of higher order power terms. In the parallel evaluation of powers, redundancy in computations is removed by exploiting any possible sharing at word level and also at bit level. As a part of this, since exponents are additive under multiplication, an ILP formulation for the minimum addition sequence problem is proposed.

  • 19.
    Abbas, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure2013In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 4, 926-937 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, the fixed-point implementation of adjustable fractional-delay filters using the Farrow structure is considered. Based on the observation that the sub-filters approximate differentiators, closed-form expressions for the L-2-norm scaling values at the outputs of each sub-filter as well as at the inputs of each delay multiplier are derived. The scaling values can then be used to derive suitable word lengths by also considering the round-off noise analysis and optimization. Different approaches are proposed to derive suitable word lengths including one based on integer linear programming, which always gives an optimal allocation. Finally, a new approach for multiplierless implementation of the sub-filters in the Farrow structure is suggested. This is shown to reduce register complexity and, for most word lengths, require less number of adders and subtracters when compared to existing approaches.

  • 20.
    Abbas, Muhammad
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Scaling of fractional delay filters based on the Farrow structure2009In: Proceedings of IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009, Piscataway: IEEE , 2009, 489-492 p.Conference paper (Refereed)
    Abstract [en]

    In this work we consider scaling of fractional delay filters using the Farrow structure. Based on the observation that the subfilters approximate the Taylor expansion of a differentiator, we derive estimates of the L2-norm scaling values at the outputs of each subfilter as well as at the inputs of each delay multiplier. The scaling values can then be used to derive suitable wordlengths in a fixed-point implementation.

  • 21.
    Abbas, Naeem
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Runtime Parallelisation Switching for MPEG4 Encoder on MPSoC2008Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
    Abstract [en]

    The recent development for multimedia applications on mobile terminals raised the need for flexible and scalable computing platforms that are capable of providing considerable (application specific) computational performance within a low cost and a low energy budget. The MPSoC with multi-disciplinary approach, resolving application mapping, platform architecture and runtime management issues, provides such multiple heterogeneous, flexible processing elements. In MPSoC, the run-time manager takes the design time exploration information as an input and selects an active Pareto point based on quality requirement and available platform resources, where a Pareto point corresponds to a particular parallelization possibility of target application. To use system’s scalability at best and enhance application’s flexibility a step further, the resource management and Pareto point selection decisions need to be adjustable at run-time. This thesis work experiments run-time Pareto point switching for MPEG-4 encoder. The work involves design time exploration and then embedding of two parallelization possibilities of MPEG-4 encoder into one single component and enabling run-time switching between parallelizations, to give run-time control over adjusting performance-cost criteria and allocation de-allocation of hardware resources at run-time. The newer system has the capability to encode each video frame with different parallelization. The obtained results offer a number of operating points on Pareto curve in between the previous ones at sequence encoding level. The run-time manager can improve application performance up to 50% or can save memory bandwidth up to 15%, according to quality request.

  • 22. Abbasi, A. G.
    et al.
    Muftic, Sead
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
    Schmölzer, Gernot
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
    CryptoNET: A model of generic security provider2010In: International Journal of Internet Technology and Secured Transactions, ISSN 1748-569X, E-ISSN 1748-5703, Vol. 2, no 3-4, 321-335 p.Article in journal (Refereed)
    Abstract [en]

    The model and design of a generic security provider provides a comprehensive set of security services, mechanisms, encapsulation methods, and security protocols for Java applications. The model is structured in four layers; each layer provides services to the upper layer and the top layer provide services to applications. The services reflect security requirements derived from a wide range of applications; from small desktop applications to large distributed enterprise environments. Based on the abstract model, this paper describes design and implementation of an instance of the provider comprising various generic security modules: symmetric key cryptography, asymmetric key cryptography, hashing, encapsulation, certificates management, creation and verification of signatures, and various network security protocols. This paper also describes the properties for extensibility, flexibility, abstraction, and compatibility of the Java security provider.

  • 23. Abbasi, A. G.
    et al.
    Muftic, Sead
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
    Schmölzer, Gernot
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
    A model and design of a security provider for Java applications2009In: International Conference for Internet Technology and Secured Transactions, ICITST 2009, 2009, 5402592- p.Conference paper (Refereed)
    Abstract [en]

    The model and design of a generic security provider provides a comprehensive set of security services, mechanisms, encapsulation methods, and security protocols for Java applications. The model is structured in four layers; each layer provides services to the upper layer and the top layer provide services to applications. The services reflect security requirements derived from a wide range of applications; from small desktop applications to large distributed enterprise environments. Based on the abstract model, this paper describes design and implementation of an instance of the provider comprising various generic security modules: symmetric key cryptography, asymmetric key cryptography, hashing, encapsulation, certificates management, creation and verification of signatures, and various network security protocols. This paper also describes the properties extensibility, flexibility, abstraction, and compatibility of the Java Security Provider.

  • 24.
    Abbasi, Abdul Ghafoor
    et al.
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
    Muftic, Sead
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
    Mumtaz, Shahzad Ahmed
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture (Closed 20120101), Communication Systems, CoS (closed 2012-01-01).
    Security extensions of windows environment based on FIPS 201 (PIV) smart card2011In: World Congr. Internet Secur., WorldCIS, 2011, 86-92 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes security extensions of various Windows components based on usage of FIPS 201 (PIV) smart cards. Compared to some other similar solutions, this system has two significant advantages: first, smart cards are based on FIPS 201 standard and not on some proprietary technology; second, smart card security extensions represent an integrated solution, so the same card is used for security of several Microsoft products. Furthermore, our smart card system uses FIPS 201 applet and middleware with smart card APIs, so it can also be used by other developers to extend their own applications with smart card functions in a Windows environment. We support the following security features with smart cards: start-up authentication (based on PIN and/or fingerprint), certificate-based domain authentication, strong authentication, and protection of local resources. We also integrated our middleware and smart cards with MS Outlook and MS Internet Explorer.

  • 25.
    Abbasi, Jasim Aftab
    Umeå University, Faculty of Science and Technology, Department of Applied Physics and Electronics.
    Test of Rapid Control System Development using TargetLink2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The aim of this thesis is to employ and evaluate an evaluation board with the standard microprocessor freescale MPC5554EVB board for implementation of control algorithms which are created in Matlab/Simulink instead of using dSPACE prototyping hardware. The Simulink real-time model shall be compiled to the MPC5554EVB board. TargetLink is a powerful software tool which allows an automatic generation of efficient C code from Simulink and facilitates model-based control design. The goal of this thesis is to learn how to use TargetLink in a control design workflow from model to real code and what are the limitations of a microprocessor platform and to evaluate the capabilities of TargetLink to generate a working code for a generic microprocessor.

  • 26.
    Abbasi, Mahdi
    University of Gävle, Department of Technology and Built Environment.
    Characterization of a 5GHz Modular Radio Frontend for WLAN Based on IEEE 802.11p2008Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The number of vehicles has increased significantly in recent years, which causeshigh density in traffic and further problems like accidents and road congestions.A solution regarding to this problem is vehicle-to-vehicle communication, wherevehicles are able to communicate with their neighboring vehicles even in the absenceof a central base station, to provide safer and more efficient roads and toincrease passenger safety.The goal of this thesis is to investigate basic physical layer parameters of ainter-vehicle communication system, like emission power, spectral emission, errorvector magnitude, guard interval, ramp-up/down time, and third order interceptpoint. I also studied the intelligent transportation system’s channel layout inEurope, how the interference of other systems are working in co-channel and adjacentchannels, and some proposals to use the allocated frequency bands. On theother hand, the fundamentals of OFDM transmission and definitions of OFDMkey parameters in IEEE 802.11p are investigated.The focus of this work is on the measurement of transmitter frontend parametersof a new testbed designed and fabricated in order to be used at inter-vehiclecommunication based on IEEE 802.11p.

  • 27.
    ABBASI, MUHAMMAD MOHSIN
    KTH, School of Electrical Engineering (EES), Signal Processing.
    Solving Sudoku by Sparse Signal Processing2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Sudoku is a discrete constraints satisfaction problem which is modeled as an underdetermined linear

    system. This report focuses on applying some new signal processing approaches to solve sudoku and

    comparisons to some of the existing approaches are implemented. As our goal is not meant for

    sudoku only in the long term, we applied approximate solvers using optimization theory methods. A

    Semi Definite Relaxation (SDR) convex optimization approach was developed for solving sudoku. The

    idea of Iterative Adaptive Algorithm for Amplitude and Phase Estimation (IAA-APES) from array

    processing is also being used for sudoku to utilize the sparsity of the sudoku solution as is the case in

    sensing applications. LIKES and SPICE were also tested on sudoku and their results are compared with

    l1-norm minimization, weighted l1-norm, and sinkhorn balancing. SPICE and l1-norm are equivalent

    in terms of accuracy, while SPICE is slower than l1-norm. LIKES and weighted l1-norm are equivalent

    and better than SPICE and l1-norm in accuracy. SDR proved to be best when the sudoku solutions are

    unique; however the computational complexity is worst for SDR. The accuracy for IAA-APES is

    somewhere between SPICE and LIKES and its computation speed is faster than both.

  • 28.
    Abbasi, Muneeb Mehmood
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Jabbar, Mohammad Abdul
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Design and Performance Analysis of Low-Noise Amplifier with Band-Pass Filter for 2.4-2.5 GHz2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Low power wireless electronics is becoming more popular due to durability, portability and small dimension. Especially, electronic devices in instruments, scientific and medical (ISM) band is convenient from the spectrum regulations and technology availability point of view. In the communication engineering society, to make a robust transceiver is always a matter of challenges for the better performance.

    However, in this thesis work, a new approach of design and performance analysis of Low-Noise Amplifier with Band-Pass filter is performed at 2.45 GHz under the communication electronics research group of Institute of Science and Technology (ITN). Band-Pass Filtered Low-Noise Amplifier is designed with lumped components and transmission lines. Performances of different designs are compared with respect to noise figure, gain, input and output reflection coefficient. In the design process, a single stage LNA is designed with amplifier, ATF-58143. Maximally flat band-pass (BPF) filters were designed with lumped components and distributed elements. Afterwards, BPF is integrated with the LNA at the front side of LNA to get a compact Band-Pass Filtered Low-Noise Amplifier with good performance.

    Advanced Design System (ADS) tool was used for design and simulation, and each design was tuned to get the optimum value for noise figure, gain and input reflection coefficient. LNA stand-alone gives acceptable value of noise figure and gain but the bandwidth was too wide compared to specification. Band-Pass Filtered Low-Noise Amplifier with lumped components gives also considerable values of noise and gain. But the gain was not so flat and the bandwidth was also wide. Then, Band-Pass Filtered Low-Noise Amplifier was designed with transmission lines where the optimum value of noise figure and gain was found. The gain was almost flat over the whole band, i.e., 2.4-2.5 GHz compared to LNA stand-alone and Band-Pass Filtered Low-Noise Amplifier designed with lumped components. It is observed that deviations of results from schematic to layout level are considerable, i.e., electromagnetic simulation is needed to predict the Band-Pass Filtered Low-Noise Amplifier performance.

    Prototype of LNA, Band-Pass Filtered Low-Noise Amplifier with lumped and transmission lines are made at ITN’s PCB laboratory. Due to unavailability of exact values of Murata components and for some other technical reasons, the measured values of Band-Pass Filtered Low-Noise Amplifier with lumped components and transmission lines are deviated compared to predicted values from simulation.

  • 29.
    Abbaspour Asadollah, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bugs and Debugging of Concurrent and Multicore Software2016Licentiate thesis, comprehensive summary (Other academic)
  • 30.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, Sigrid
    Ericsson AB, Kista, Sweden.
    Towards Classification of Concurrency Bugs Based on Observable Properties2015In: Proceedings - 1st International Workshop on Complex Faults and Failures in Large Software Systems, COUFLESS 2015, 2015, 41-47 p.Conference paper (Refereed)
    Abstract [en]

    In software engineering, classification is a way to find an organized structure of knowledge about objects. Classification serves to investigate the relationship between the items to be classified, and can be used to identify the current gaps in the field. In many cases users are able to order and relate objects by fitting them in a category. This paper presents initial work on a taxonomy for classification of errors (bugs) related to concurrent execution of application level software threads. By classifying concurrency bugs based on their corresponding observable properties, this research aims to examine and structure the state of the art in this field, as well as to provide practitioner support for testing and debugging of concurrent software. We also show how the proposed classification, and the different classes of bugs, relates to the state of the art in the field by providing a mapping of the classification to a number of recently published papers in the software engineering field.

  • 31.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Inam, Rafia
    Ericsson AB, Kista, Sweden.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Survey on Testing for Cyber Physical System2015In: Testing Software and Systems: 27th IFIP WG 6.1 International Conference, ICTSS 2015, Sharjah and Dubai, United Arab Emirates, November 23-25, 2015, Proceedings, 2015, 194-207 p.Conference paper (Refereed)
    Abstract [en]

    Cyber Physical Systems (CPS) bridge the cyber-world of computing and communications with the physical world and require development of secure and reliable software. It asserts a big challenge not only on testing and verifying the correctness of all physical and cyber components of such big systems, but also on integration of these components. This paper develops a categorization of multiple levels of testing required to test CPS and makes a comparison of these levels with the levels of software testing based on the V-model. It presents a detailed state-of-the-art survey on the testing approaches performed on the CPS. Further, it provides challenges in CPS testing.

  • 32.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Saadatmand, Mehrdad
    SICS Swedish ICT, Västerås, Sweden.
    Eldh, Sigrid
    Ericsson AB, Kista, Sweden.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Model for Systematic Monitoring and Debugging of Starvation Bugs in Multicore Software2016In: 2016 ASE Workshop on Specification, Comprehension, Testing and Debugging of Concurrent Programs SCTDCP2016, 2016Conference paper (Refereed)
    Abstract [en]

    With the development of multicore hardware, concurrent, parallel and multicore software are becoming increasingly popular. Software companies are spending a huge amount of time and resources to nd and debug the bugs. Among all types of software bugs, concurrency bugs are also important and troublesome. This type of bugs is increasingly becoming an issue particularly due to the growing prevalence of multicore hardware. In this position paper, we propose a model for monitoring and debugging Starvation bugs as a type of concurrency bugs in multicore software. The model is composed into three phases: monitoring, detecting and debugging. The monitoring phase can support detecting phase by storing collected data from the system execution. The detecting phase can support debugging phase by comparing the stored data with starvation bug's properties, and the debugging phase can help in reproducing and removing the Starvation bug from multicore software. Our intention is that our model is the basis for developing tool(s) to enable solving Starvation bugs in software for multicore platforms.

  • 33.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, Sigrid
    Ericsson AB, Kista, Sweden .
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Afza, Wasif
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    10 Years of research on debugging concurrent and multicore software: a systematic mapping studyIn: Software quality journal, ISSN 0963-9314, E-ISSN 1573-1367Article in journal (Refereed)
    Abstract [en]

    Debugging – the process of identifying, localizing and fixing bugs – is a key activity in software development. Due to issues such as non-determinism and difficulties of reproducing failures, debugging concurrent software is significantly more challenging than debugging sequential software. A number of methods, models and tools for debugging concurrent and multicore software have been proposed, but the body of work partially lacks a common terminology and a more recent view of the problems to solve. This suggests the need for a classification, and an up-to-date comprehensive overview of the area. 

    This paper presents the results of a systematic mapping study in the field of debugging of concurrent and multicore software in the last decade (2005– 2014). The study is guided by two objectives: (1) to summarize the recent publication trends and (2) to clarify current research gaps in the field.

    Through a multi-stage selection process, we identified 145 relevant papers. Based on these, we summarize the publication trend in the field by showing distribution of publications with respect to year , publication venues , representation of academia and industry , and active research institutes . We also identify research gaps in the field based on attributes such as types of concurrency bugs, types of debugging processes , types of research  and research contributions.

    The main observations from the study are that during the years 2005–2014: (1) there is no focal conference or venue to publish papers in this area, hence a large variety of conferences and journal venues (90) are used to publish relevant papers in this area; (2) in terms of publication contribution, academia was more active in this area than industry; (3) most publications in the field address the data race bug; (4) bug identification is the most common stage of debugging addressed by articles in the period; (5) there are six types of research approaches found, with solution proposals being the most common one; and (6) the published papers essentially focus on four different types of contributions, with ”methods” being the type most common one.

    We can further conclude that there is still quite a number of aspects that are not sufficiently covered in the field, most notably including (1) exploring correction  and fixing bugs  in terms of debugging process; (2) order violation, suspension  and starvation  in terms of concurrency bugs; (3) validation and evaluation research  in the matter of research type; (4) metric  in terms of research contribution. It is clear that the concurrent, parallel and multicore software community needs broader studies in debugging.This systematic mapping study can help direct such efforts.

  • 34.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, Sigrid
    Ericsson AB, Kista, Sweden.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Paul Enoiu, Eduard
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Study on Concurrency Bugs in an Open Source Software2016In: IFIP Advances in Information and Communication Technology, vol. 472, 2016, Vol. 472, 16-31 p.Conference paper (Refereed)
    Abstract [en]

    Concurrent programming puts demands on software debugging and testing, as concurrent software may exhibit problems not present in sequential software, e.g., deadlocks and race conditions. In aiming to increase efficiency and effectiveness of debugging and bug-fixing for concurrent software, a deep understanding of concurrency bugs, their frequency and fixingtimes would be helpful. Similarly, to design effective tools and techniques for testing and debugging concurrent software understanding the differences between non-concurrency and concurrency bugs in real-word software would be useful.

  • 35.
    Abbaspour, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Proposing Combined Approaches to Remove ECG Artifacts from Surface EMG Signals2015Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Electromyography (EMG) is a tool routinely used for a variety of applications in a very large breadth of disciplines. However, this signal is inevitably contaminated by various artifacts originated from different sources. Electrical activity of heart muscles, electrocardiogram (ECG), is one of sources which affects the EMG signals due to the proximity of the collection sites to the heart and makes its analysis non-reliable. Different methods have been proposed to remove ECG artifacts from surface EMG signals; however, in spite of numerous attempts to eliminate or reduce this artifact, the problem of accurate and effective de-noising of EMG still remains a challenge. In this study common methods such as high pass filter (HPF), gating method, spike clipping, hybrid technique, template subtraction, independent component analysis (ICA), wavelet transform, wavelet-ICA, artificial neural network (ANN), and adaptive noise canceller (ANC) and adaptive neuro-fuzzy inference system (ANFIS) are used to remove ECG artifacts from surface EMG signals and their accuracy and effectiveness is investigated. HPF, gating method and spike clipping are fast; however they remove useful information from EMG signals. Hybrid technique and ANC are time consuming. Template subtraction requires predetermined QRS pattern. Using wavelet transform some artifacts remain in the original signal and part of the desired signal is removed. ICA requires multi-channel signals. Wavelet-ICA approach does not require multi-channel signals; however, it is user-dependent. ANN and ANFIS have good performance, but it is possible to improve their results by combining them with other techniques. For some applications of EMG signals such as rehabilitation, motion control and motion prediction, the quality of EMG signals is very important. Furthermore, the artifact removal methods need to be online and automatic. Hence, efficient methods such as ANN-wavelet, adaptive subtraction and automated wavelet-ICA are proposed to effectively eliminate ECG artifacts from surface EMG signals. To compare the results of the investigated methods and the proposed methods in this study, clean EMG signals from biceps and deltoid muscles and ECG artifacts from pectoralis major muscle are recorded from five healthy subjects to create 10 channels of contaminated EMG signals by adding the recorded ECG artifacts to the clean EMG signals. The artifact removal methods are also applied to the 10 channels of real contaminated EMG signals from pectoralis major muscle of the left side. Evaluation criteria such as signal to noise ratio, relative error, correlation coefficient, elapsed time and power spectrum density are used to evaluate the performance of the proposed methods. It is found that the performance of the proposed ANN-wavelet method is superior to the other methods with a signal to noise ratio, relative error and correlation coefficient of 15.53, 0.01 and 0.98 respectively.

  • 36.
    Abbaspour, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Daniel, Sundmark
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Runtime Verification for Detecting Suspension Bugs in Multicore and Parallel Software2017In: Proceedings - 10th IEEE International Conference on Software Testing, Verification and Validation Workshops, ICSTW 2017, 2017, 77-80 p.Conference paper (Refereed)
    Abstract [en]

    Multicore hardware development increases the popularity of parallel and multicore software, while testing and debugging the software become more difficult, frustrating and costly. Among all types of software bugs, concurrency bugs are both important and troublesome. This type of bugs is increasingly becoming an issue, particularly due to the growing prevalence of multicore hardware. Suspension-based-locking bug is one type of concurrency bugs. This position paper proposes a model based on runtime verification and reflection technique in the context of multicore and parallel software to monitor and detect suspension-based-locking bugs. The model is not only able to detect faults, but also diagnose and even repair them. The model is composed of four layers: Logging, Monitoring, Suspension Bug Diagnosis and Mitigation. The logging layer will observe the events and save them into a file system. The monitoring layer will detect the presents of bugs in the software. The suspension bug diagnosis will identify Suspension bugs by comparing the captured data with the suspension bug properties. Finally, the mitigation layer will reconfigure the software to mitigate the suspension bugs. A functional architecture of a runtime verification tool is also proposed in this paper. This architecture is based on the proposed model and is comprised of different modules. 

  • 37.
    Abbaspour, Sara
    et al.
    Amirkabir University of technology,Tehran, Iran.
    Fallah, Ali
    Amirkabir University of technology,Tehran, Iran.
    Removing ECG Artifact from the Surface EMG Signal Using Adaptive Subtraction Technique2014In: Biomedical Physics and Engineering, ISSN 2251-7200, Vol. 4, no 1, 33-38 p.Article in journal (Refereed)
    Abstract [en]

    Background: The electrocardiogram artifact is a major contamination in the electromyogram signals when electromyogram signal is recorded from upper trunk muscles and because of that the contaminated electromyogram is not useful. Objective: Removing electrocardiogram contamination from electromyogram signals. Methods: In this paper, the clean electromyogram signal, electrocardiogram artifact and electrocardiogram signal were recorded from leg muscles, the pectoralis major muscle of the left side and V4, respectively. After the pre-processing, contaminated electromyogram signal is simulated with a combination of clean electromyogram and electrocardiogram artifact. Then, contaminated electromyogram is cleaned using adaptive subtraction method. This method contains some steps; (1) QRS detection, (2) formation of electrocardiogram template by averaging the electrocardiogram complexes, (3) using low pass filter to remove undesirable artifacts, (4) subtraction. Results: Performance of our method is evaluated using qualitative criteria, power spectrum density and coherence and quantitative criteria signal to noise ratio, relative error and cross correlation. The result of signal to noise ratio, relative error and cross correlation is equal to 10.493, 0.04 and %97 respectively. Finally, there is a comparison between proposed method and some existing methods. Conclusion: The result indicates that adaptive subtraction method is somewhat effective to remove electrocardiogram artifact from contaminated electromyogram signal and has an acceptable result.

  • 38.
    Abbaspour, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Fallah, Ali
    Amirkabir University of Technology, Tehran, Iran.
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Gholamhosseini, Hamid
    Auckland University of Technology, Auckland, New Zealand.
    A Novel Approach for Removing ECG Interferences from Surface EMG signals Using a Combined ANFIS and Wavelet2015In: Journal of Electromyography & Kinesiology, ISSN 1050-6411, E-ISSN 1873-5711, Vol. 26, 52-59 p.Article in journal (Refereed)
    Abstract [en]

    In recent years, the removal of electrocardiogram (ECG) interferences from electromyogram (EMG) signals has been given large consideration. Where the quality of EMG signal is of interest, it is important to remove ECG interferences from EMG signals. In this paper, an efficient method based on a combination of adaptive neuro-fuzzy inference system (ANFIS) and wavelet transform is proposed to effectively eliminate ECG interferences from surface EMG signals. The proposed approach is compared with other common methods such as high-pass filter, artificial neural network, adaptive noise canceller, wavelet transform, subtraction method and ANFIS. It is found that the performance of the proposed ANFIS-wavelet method is superior to the other methods with the signal to noise ratio and relative error of 14.97 dB and 0.02 respectively and a significantly higher correlation coefficient (p < 0.05).

  • 39.
    Abbaspour, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Gholamhosseini, H.
    School of Engineering, Auckland University of TechnologyAuckland, New Zealand .
    Linden, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Evaluation of wavelet based methods in removing motion artifact from ECG signal2015In: IFMBE Proceedings, 2015, 1-4 p.Conference paper (Refereed)
    Abstract [en]

    Accurate recording and precise analysis of the electrocardiogram (ECG) signals are crucial in the pathophysiological study and clinical treatment. These recordings are often corrupted by different artifacts. The aim of this study is to propose two different methods, wavelet transform based on nonlinear thresholding and a combination method using wavelet and independent component analysis (ICA), to remove motion artifact from ECG signals. To evaluate the performance of the proposed methods, the developed techniques are applied to the real and simulated ECG data. The results of this evaluation are presented using quantitative and qualitative criteria. The results show that the proposed methods are able to reduce motion artifacts in ECG signals. Signal to noise ratio (SNR) of the wavelet technique is equal to 13.85. The wavelet-ICA method performed better with SNR of 14.23.

  • 40.
    Abbaspour, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Gholamhosseini, Hamid
    Auckland University of Technology, New Zealand.
    ECG Artifact Removal from Surface EMG Signal Using an Automated Method Based on Wavelet-ICA2015In: Studies in Health Technology and Informatics, Volume 211, 2015, 91-97 p.Conference paper (Refereed)
    Abstract [en]

    This study aims at proposing an efficient method for automated electrocardiography (ECG) artifact removal from surface electromyography (EMG) signals recorded from upper trunk muscles. Wavelet transform is applied to the simulated data set of corrupted surface EMG signals to create multidimensional signal. Afterward, independent component analysis (ICA) is used to separate ECG artifact components from the original EMG signal. Components that correspond to the ECG artifact are then identified by an automated detection algorithm and are subsequently removed using a conventional high pass filter. Finally, the results of the proposed method are compared with wavelet transform, ICA, adaptive filter and empirical mode decomposition-ICA methods. The automated artifact removal method proposed in this study successfully removes the ECG artifacts from EMG signals with a signal to noise ratio value of 9.38 while keeping the distortion of original EMG to a minimum.

  • 41.
    Abboud, Mohamad Moulham
    Linnaeus University, Faculty of Technology, Department of Physics and Electrical Engineering.
    Simulation of 3ph induction motor in Matlab with Direct and Soft starting methods.2015Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    Asynchronous machines are considered nowadays the most commonly used electrical machines, which are mainly used as electrical induction motors. Starting the induction motor is the most important and dangerous step. The theory behind this project is based on representing the real motor by a set of equations and values in Matlab using the subsystem feature, forming a corresponding idealistic motor in a way where all the physical effects are similar. The motor is started under different loads in two methods: Direct and Soft starting. Each method is studied and discussed using supporting simulation of currents, torque, speed, efficiency and power factor curves.

  • 42.
    Abboud, Mohamad Moulham
    Halmstad University, School of Business, Engineering and Science, Biological and Environmental Systems (BLESS), Energy Science.
    Simulation of 3ph induction motor in Matlab with VVVF starting method2016Independent thesis Advanced level (degree of Master (One Year)), 40 credits / 60 HE creditsStudent thesis
    Abstract [en]

    Nowadays, three-phase induction motors are widely used on industrial and other types of processes. Therefore, accurate knowledge of an induction motor performance is very essential to have an idea of its operation conditions. This study is a sequel of a previous one, where Direct and Soft starting methods of three-phase motors has been simulated and compared. As in the previous study, the theory behind this one is based on representing the real motor by aset of equations and values in Matlab, forming a corresponding idealistic motor in a way where all the physical effects are similar. The motor is started under three different frequencies in the VVVF method using supporting simulation of the current, torque, speed,efficiency and power factor curves. The results of the three starting methods are then discussed and compared.

  • 43. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. Ohio State University, Columbus, United States .
    High throughput architecture for high performance NoC2009In: ISCAS: 2009 IEEE International Symposium on Circuits and Systems, IEEE , 2009, 2241-2244 p.Conference paper (Refereed)
    Abstract [en]

    High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.

  • 44. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    High throughput architecture for CLICHÉ network on chip2009In: Proceedings - IEEE International SOC Conference, SOCC 2009, 2009, 155-158 p.Conference paper (Refereed)
    Abstract [en]

    High Throughput Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of High Throughput CLICHÉ switch is decreased by 18% as compared to CLICHÉ switch. The total metal resources required to implement High Throughput CLICHÉ design is increased by 7% as compared to the total metal resources required to implement CLICHÉ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHÉ architecture.

  • 45. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Korzec, D.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Ohio State University, Columbus, OH, United States .
    Power characteristics of networks on chip2010In: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, IEEE , 2010, 3721-3724 p.Conference paper (Refereed)
    Abstract [en]

    Power characteristics of different Network on Chip (NoC) topologies are developed. Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch links and repeaters for BFT represents only 1% of the total power dissipation of the network. In addition of providing high throughput, the BFT is a power efficient topology for NoCs.

  • 46. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Korzec, D.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Ohio State University, Columbus, OH, United States .
    Asynchronous BFT for low power networks on chip2010In: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, IEEE , 2010, 3240-3243 p.Conference paper (Refereed)
    Abstract [en]

    Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (αdata satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the αdata equals 0.2 and the activity factor of the control signals is equal to 1/64 of the αdata. The total metal resources required to implement Asynchronous design is decreased by 12%.

  • 47. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Korzec, D.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Power efficient networks on chip2009In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 2009, 105-108 p.Conference paper (Refereed)
    Abstract [en]

    a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduce. The power consumption oy the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover. The power reduction technique is applied to different NoC architectures. The technique reduce. The power consumption oy the network by up to 41%. Whe. The power consumption oy the whole network includin. The interswich links and repeaters is taken into account. The overall power consumption is decreased by up to 33% at the maximum operating frequency oy the switch. The BFT architecture consume. The minimum power as compared to other NoC architectures.

  • 48. Abd Elghany, M. A.
    et al.
    El-Moursy, M. A.
    Korzec, D.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Ohio State University, United States .
    High throughput architecture for OCTAGON network on chip2009In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, IEEE , 2009, 101-104 p.Conference paper (Refereed)
    Abstract [en]

    High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increase. The throughput oy the network by 17% while preservin. The average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared to the total metal resources required to implement OCTAGON design. The extra power consumption required to achiev. The proposed architecture is 2% oy the total power consumption oy the OCTAGON architecture.

  • 49.
    Abdalla, Munir A
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Fröjdh, Christer
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Petersson, Sture
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    A CMOS APS for dental X-ray imaging using scintillating sensors2001In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, ISSN 0168-9002, Vol. 460, no 1, 197-203 p.Article in journal (Refereed)
    Abstract [en]

    In this paper we present an integrating CMOS Active Pixel Sensor (APS) circuit to be used with scintillator type X-ray sensors for intra oral dental X-ray imaging systems. Different pixel architectures were constructed to explore their performance characteristics and to study the feasibility of the development of such systems using the CMOS technology. A prototype 64×80 pixel array has been implemented in a CMOS 0.8 μm double poly n-well process with a pixel pitch of 50 μm. A spectral sensitivity measurement for the different pixels topologies, as well as measured X-ray direct absorption in the different APSs are presented. A measurement of the output signal showed a good linearity over a wide dynamic range. This chip showed that the very low sensitivity of the CMOS APSs to direct X-ray exposure adds a great advantage to the various CMOS advantages over CCD-based imaging systems.

  • 50.
    Abdalla, Munir A
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Fröjdh, Christer
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Petersson, Sture
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    An integrating CMOS APS for X-ray imaging with an in-pixel preamplifier2001In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, ISSN 0168-9002, E-ISSN 1872-9576, Vol. 466, no 1, 232-236 p.Article in journal (Refereed)
    Abstract [en]

    We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in the CMOS pixel. The pixel features an integrating capacitor in the feedback loop of a preamplifier of a finite gain in order to increase the optical sensitivity. To verify the effectiveness of this in-pixel preamplification, a prototype 32 x 80 element CMOS active pixel array was implemented in a 0.8 mum CMOS double poly, n-well process with a pixel pitch of 50 mum. Measured results confirmed the improved optical sensitivity performance of the APS. Various measurements on device performance are presented.

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