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  • 651.
    Wrona, Michal
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Tractability Frontier for Dually-Closed Ord-Horn Quantified Constraint Satisfaction Problems2014In: MATHEMATICAL FOUNDATIONS OF COMPUTER SCIENCE 2014, PT I, Springer Berlin/Heidelberg, 2014, Vol. 8634, p. 535-546Conference paper (Refereed)
    Abstract [en]

    A temporal constraint language is a relational structure with a first-order definition in the rational numbers with the order. We study here the complexity of the Quantified Constraint Satisfaction Problem (QCSP) for Ord-Horn languages: probably the most widely studied family of all temporal constraint languages.

    We restrict ourselves to a natural subclass that we call dually-closed Ord-Horn languages. The main result of the paper states that the QCSP for a dually-closed Ord-Horn language is either in P or it is coNP-hard.

  • 652.
    Xu, Yang
    et al.
    Lund University, Sweden.
    Årzen, Karl-Erik
    Lund University, Sweden.
    Cervin, Anton
    Lund University, Sweden.
    Bini, Enrico
    Scuola Superiore Sant’Anna, Italy.
    Tanasa, Bogdan
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Exploiting Job Response-Time Information in the Co-Design of Real-Time Control Systems2015In: 2015 IEEE 21ST INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 247-256Conference paper (Refereed)
    Abstract [en]

    We consider a real-time system of multiple tasks, each task having a plant to control. The overall quadratic control cost is to be optimized. We exploit the periodicity of the task response time, which corresponds to a periodic delay pattern in the feedback control loop. Perturbed periods are used as a tool to find a finite hyper period. We present an analytical procedure to design a periodic linear-quadratic-Gaussian (LQG) controller for tasks with fixed execution times as well as a numerical solution to the periodic -- stochastic LQG problem for tasks with variable execution times. The controllers are evaluated using simulations in real-time scheduling and control co-design examples.

  • 653.
    Yang, Ming-Jie
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Design and Implementation of a Compiler for an XML-based Hardware Description Language to Support Energy Optimization2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    GPU-based heterogeneous system architectures are popular as they combine the advantages of CPU with the benefits of GPU. Development of high-performance and power-efficient software for heterogeneous system architecture needs to take both hardware and software specifications into consideration, which leads the software development process to be more complicated. To simplify the software development process, Architecture Description Languages (ADLs) came out. By modeling the target architecture components into structural formats, programmers can adapt their software to the platforms which they used.

    XPDL is a modular and extensible XML-based platform description language which is mainly designed to support optimization.The purposes of this thesis are to design the query API (Application Programming Interface) and develop a compiler which translates the XPDL descriptors to libraries that implement the API to support programmers for the development of adaptive high-performance and energy-optimized software.

    In this thesis, we design and develop a compiler to generate the API according to the XPDL descriptors.The main workflow of the designed compiler is following: first, the toolchain validates the XPDL descriptors against XSDs. Second, it parses the descriptors into DOM trees and transforms them into XPDL model trees. Next, the compiler links all XPDL model trees together, which results in the intermediate representation (IR). Then, any unspecified node values which means the unknown attributes, are handled by microbenchmark generator and executor. In the end, the code generator generates the libraries which expose the API according to the information in the IR. Finally, a few example codes are discussed to show how the API can be used to develop performance adaptive applications on heterogeneous systems.

  • 654.
    Yildiz, George
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Wallström, Fredrik
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Evaluation of Couchbase As a Tool to Solve a Scalability Problem with Shared Geographical Objects2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Sharing a large amount of data between many mobile devices can lead to scalability problems. One of these scalability problems is that the data becomes too large to store on mobile devices and that many updates are sent to each device. In this thesis, Couchbase is evaluated as a tool to solve this problem where the data has a geographical position. The scalability problem is solved by partitioning the data with the help of Couchbase channels and Google’s tile-based mapping system. Synchronising and storing only data of interest for each user has been in focus. The result showed that it was effective to use a Couchbase solution together with Google’s tile-based mapping system to reduce the amount of data that was required to be stored for each user. It was shown to be more effective to store objects encoded as base64 data instead of their binary data representation for the data set used in this study. The reason for this is because Couchbase stores Binary Large Objects (BLOBs) as separate files and the BLOBs in the data set had much smaller file size than what the disk sector size was. A test to find how the synchronisation time was affected by the number of channels was conducted. It showed that the synchronisation time increased linearly with an increasing number of channels when the objects were stored in separate files. When the objects were encoded as base64 data, the number of channels used had a minor effect on the synchronisation time. The conclusion is that the approach presented in this study has been effective. However, the results are data dependent and therefore it is recommended to rerun similar tests in order to decide the number of channels to use when partitioning the data.

  • 655.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Lund University, Sweden.
    Scenario-Based Network Design for P16872013In: SSoCC'13, 2013Conference paper (Other academic)
    Abstract [en]

    To improve testability of integrated circuits against manufacturing defects, and to better handle the complexity of modern designs during debugging and characterization, it is common to embed testing, debugging, configuration, and monitoring features (called on-chip instruments) within the chip. IEEE P1687 proposes a flexible network for accessing and operating such on-chip instruments from outside the chip, and facilitates reusing instrument access procedures in different usage scenarios throughout the chip's life-cycle-spanning from chip prototyping to in-field test. Efficient access (in terms of time) to on-chip instruments requires careful design of the instrument access network. However, it is shown that a network optimized for one usage scenario, is not necessarily efficient in other scenarios. To address the problem of designing a network which is efficient in terms of instrument access time under multiple scenarios, in this work, we compare a number of network design approaches provided by P1687, in terms of instrument access time and hardware overhead.

  • 656.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Asani, Golnaz
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints2011In: Proceedings of the Asian Test Symposium, IEEE , 2011, p. 525-531Conference paper (Refereed)
    Abstract [en]

    In contrast to IEEE 1149.1, IEEE P1687 allows, through segment insertion bits, flexible scan paths for accessing on-chip instruments, such as test, debug, monitoring, measurement and configuration features. Flexible access to embedded instruments allows test time reduction, which is important at production test. However, the test access scheme should be carefully selected such that resource constraints are not violated and power constraints are met. For IEEE P1687, we detail in this paper session-based and session-less test scheduling, and propose resource and power-aware test scheduling algorithms for the detailed scheduling types. Results using the implementation of our algorithms shows on ITC’02-based benchmarks significant test time reductions when compared to non-optimized test schedules.

  • 657.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Automated Design for IEEE P16872011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011., 2011Conference paper (Other academic)
  • 658.
    Zeng, Haibo
    et al.
    Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, USA.
    Joshi, Prachi
    Department of Electrical and Computer Engineering, Virginia Tech, USA.
    Thiele, Daniel
    Elektrobit Automotive GmbH, Germany.
    Diemer, Jonas
    Symtavision, Braunschweig, Germany.
    Axer, Philip
    NXP Semiconductors, Hamburg, Germany.
    Ernst, Rolf
    Institut für Datentechnik und Kommunikationsnetze, Technische Universität Braunschweig, Germany.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Networked Real-Time Embedded Systems2017In: Handbook of Hardware/Software Codesign / [ed] Soonhoi Ha and Jürgen Teich, Dordrecht: Springer, 2017, p. 753-792Chapter in book (Refereed)
    Abstract [en]

    This chapter gives an overview on various real-time communication protocols, from the Controller Area Network (CAN) that was standardized over twenty years ago but is still popular, to the FlexRay protocol that provides strong predictability and fault tolerance, to the more recent Ethernet-based networks. The design of these protocols including their messaging mechanisms was driven by diversified requirements on bandwidth, real-time predictability, reliability, cost, etc. The chapter provides three examples of real-time communication protocols: CAN as an example of event-triggered communication, FlexRay as a heterogeneous protocol supporting both time-triggered and event-triggered communications, and different incarnations of Ethernet that provide desired temporal guarantees.

  • 659.
    Zhan, Jinyu
    et al.
    Univ Elect Sci and Technol China, Peoples R China.
    Zhang, Xia
    Univ Texas Dallas, TX 75083 USA.
    Jiang, Wei
    Univ Elect Sci and Technol China, Peoples R China.
    Ma, Yue
    Univ Notre Dame, IN 46556 USA.
    Jiang, Ke
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Energy optimization of security-sensitive mixed-criticality applications for distributed real-time systems2018In: Journal of Parallel and Distributed Computing, ISSN 0743-7315, E-ISSN 1096-0848, Vol. 117, p. 115-126Article in journal (Refereed)
    Abstract [en]

    Existing studies on mixed-criticality systems are usually safety-oriented, which seriously ignore the security and energy related requirements. In this paper we are interested in the design of security-sensitive mixed-criticality real-time systems. We first establish the system model to capture security-critical applications in mixed-criticality systems. Higher security-criticality protection always results in significant time and energy overhead in mixed-criticality systems. Thus, this paper proposes a system-level design framework for energy optimization of security-sensitive mixed-criticality system with hard real-time constraints. Since the time complexity of finding optimal solutions grows exponentially as problem size grows, a GA (Genetic Algorithm) based on efficient heuristic algorithm is devised to address the system-level optimization problem. Extensive experiments and a real-life case study have been conducted to show the efficiency of the proposed technique, which can obtain balanced minimal energy consumption while satisfying strict security and timing constraints. The proposed approach can save up to 28.9% energy consumption compared with other three candidates. (C) 2018 Elsevier Inc. All rights reserved.

  • 660.
    Zhang, Xia
    et al.
    University of Electronic Science and Technology, China.
    Zhang, Jinyu
    University of Electronic Science and Technology, China.
    Jiang, Wei
    University of Electronic Science and Technology, China.
    Ma, Yue
    University of Electronic Science and Technology, China.
    Jiang, Ke
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Design Optimization of Security-Sensitive Mixed-Criticality Real-Time Embedded Systems2013Conference paper (Refereed)
    Abstract [en]

    In this paper we are interested in securitysensitive mixed-criticality real-time systems. Existing researches on mixed-criticality systems usually are safety-oriented, which seriously ignore the security requirements. We firstly establish the system model to capture security-critical applications in mixed-criticality systems. Higher security-criticality protection always results in significant time and energy overhead in mixedcriticality systems. Thus, this paper proposes a system-level design framework for energy optimization of security-sensitive mixed-criticality system. Since the time complexity of finding optimal solutions grows exponentially as problem size grows, a GA based efficient heuristic algorithm is devised to address the system-level optimization problem. Extensive experiments demonstrate the efficiency of the proposed technique, which can obtain balanced minimal energy consumption while satisfying strict security and timing constraints.

  • 661.
    Zhang, Ying
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Li, Huawei
    Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China.
    Li, Xiaowei
    Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China.
    Automatic Test Program Generation Using Executing Trace Based Constraint Extraction for Embedded Processors2013In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 21, no 7, p. 1220-1233Article in journal (Refereed)
    Abstract [en]

    Software-based self-testing (SBST) has been a promising method for processor testing, but the complexity of the state-of-art processors still poses great challenges for SBST. This paper utilizes the executing trace collected during executing training programs on the processor under test to simplify mappings and functional constraint extraction for ports of inner components, which facilitate structural test generation with constraints at gate level, and automatic test instruction generation (ATIG) even for hidden control logic (HCL). In addition, for sequential HCL, we present a test routine generation technique on the basis of an extended finite state machine, so that structural patterns for combinational subcircuits in the sequential HCL can be mapped into the test routines to form a test program. Experimental results demonstrate that the proposed ATIG method can achieve good structural fault coverage with compact test programs on modern processors.

  • 662.
    Zhang, Ying
    et al.
    School of Software Engineering, Tongji University, China.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Jiang, Jianhui
    School of Software Engineering, Tongji University, China.
    Li, Huawei
    State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China.
    Fujita, Masahiro
    VLSI Design and Education Center, University of Tokyo, Japan .
    Temperature-Aware Software-Based Self-Testing for Delay Faults2015In: Proc. Design, Automation and Test in Europe Conference (DATE’15), Grenoble, France, Mar. 9-13, 2015., 2015Conference paper (Refereed)
    Abstract [en]

    Delay defects under high temperature have been one of the most critical factors to affect the reliability of computer systems, and the current test methods don’t address this problem properly. In this paper, a temperature-aware software-based selftesting (SBST) technique is proposed to self-heat the processors within a high temperature range and effectively test delay faults under high temperature. First, it automatically generates highquality test programs through automatic test instruction generation (ATIG), and avoids over-testing caused by nonfunctional patterns. Second, it exploits two effective powerintensive program transformations to self-heat up the processors internally. Third, it applies a greedy algorithm to search the optimized schedule of the test templates in order to generate the test program while making sure that the temperature of the processor under test is within the specified range. Experimental results show that the generated program is successful to guarantee delay test within the given temperature range, and achieves high test performance with functional patterns.

  • 663.
    Zhang, Ying
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Automatic Test Program Generation for Out-of-Order Superscalar Processors2012In: 21st IEEE Asian Test Symposium (ATS12), Niigata, Japan, November 19-22, 2012., IEEE, 2012Conference paper (Refereed)
    Abstract [en]

    This paper presents a high-level automatic test instruction generation (HATIG) technical that allows, for the first time, to test the scheduling unit of an out-of-order super scalar processor. This technique leverages on existing bounded model checking tools in order to generate software-based self-testing programs from a global EFSM model of the processor under test. The experimental results have demonstrated the efficiency of the proposed technique.

  • 664.
    Zhou, Yuanbin
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Samii, Soheil
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. General Motors, USA.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Scheduling optimization with partitioning for mixed-criticality systems2019In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 98, p. 191-200Article in journal (Refereed)
    Abstract [en]

    Modern real-time embedded and cyber-physical systems comprise a large number of applications, often of different criticalities, executing on the same computing platform. Partitioned scheduling is used to provide temporal isolation among tasks with different criticalities. Isolation is often a requirement, for example, in order to avoid the case when a low criticality task overruns or fails in such a way that causes a failure in a high criticality task. When the number of partitions increases in mixed criticality systems, the size of the schedule table can become extremely large, which becomes a critical bottleneck due to design time and memory constraints of embedded systems. In addition, switching between partitions causes CPU overhead due to preemption. In this paper, we propose a design framework comprising the trade-off between schedule table size and system utilization, as well as a re-scheduling algorithm to reduce the effect of preemptions on utilization. Extensive experiments demonstrate the effectiveness of the proposed algorithms and design framework.

  • 665.
    Zhou, Yuanbin
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Samii, Soheil
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. General Motors, USA.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Partitioned and overhead-aware scheduling of mixed-criticality real-time systems2019In: 24th Asia and South Pacific Design Automation Conference, New York: Association for Computing Machinery (ACM), 2019, p. 39-44Conference paper (Refereed)
    Abstract [en]

    Modern real-time embedded and cyber-physical systems comprise a large number of applications, often of different criticalities, executing on the same computing platform. Partitioned scheduling is used to provide temporal isolation among tasks with different criticalities. Isolation is often a requirement, for example, in order to avoid the case when a low criticality task overruns or fails in such a way that causes a failure in a high criticality task. When the number of partitions increases in mixed criticality systems, the size of the schedule table can become extremely large, which becomes a critical bottleneck due to design time and memory constraints of embedded systems. In addition, switching between partitions at runtime causes CPU overhead due to preemption. In this paper, we propose a design framework comprising a hyper-period optimization algorithm, which reduces the size of schedule table and preserves schedulability, and a re-scheduling algorithm to reduce the number of preemptions. Extensive experiments demonstrate the effectiveness of proposed algorithms and design framework.

  • 666.
    Ögren, Mikael
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Wikblad, Ludwig
    Linköping University, Department of Computer and Information Science, Software and Systems.
    En testprocess för webbutvecklingsprojekt med små team2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Finding a suitable approach for testing in small development teams is a challenge. Many small companies view traditional test processes and test process improvement models as too resource intensive for their needs. Minimal Test Practice Framework (MTPF) is a framework for testing which purpose is to provide a minimalistic approach to test improvement. The goal of this study was to examine how MTPF can be adapted to a small development team without incurring a time cost that the team would experience as too high. The study was performed in the department Web \& Mobile of the company Exsitec. At the department teams of 2-6 people develop web applications to business customers. During the study a testprocess was developed in close cooperation with the developers of the department with the aim of adapting it as well as possible to the needs of the department. The study was performed as action research in three phases, according to the method Cooperative Method Development, in a project with two developers. During the first phase all developers in the department were interviewed to establish an understanding of the environment for the study. During the second phase a set of possible improvements was developed together with the developers. During the third phase some of these improvements were implemented and evaluated. By focusing on unit testing central business logic in the application the developed test process improved the developers confidence in the code quality without being perceived as too resource intensive.

  • 667.
    Öhberg, Tomas
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Auto-tuning Hybrid CPU-GPU Execution of Algorithmic Skeletons in SkePU2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The trend in computer architectures has for several years been heterogeneous systems consisting of a regular CPU and at least one additional, specialized processing unit, such as a GPU.The different characteristics of the processing units and the requirement of multiple tools and programming languages makes programming of such systems a challenging task. Although there exist tools for programming each processing unit, utilizing the full potential of a heterogeneous computer still requires specialized implementations involving multiple frameworks and hand-tuning of parameters.To fully exploit the performance of heterogeneous systems for a single computation, hybrid execution is needed, i.e. execution where the workload is distributed between multiple, heterogeneous processing units, working simultaneously on the computation.

    This thesis presents the implementation of a new hybrid execution backend in the algorithmic skeleton framework SkePU. The skeleton framework already gives programmers a user-friendly interface to algorithmic templates, executable on different hardware using OpenMP, CUDA and OpenCL. With this extension it is now also possible to divide the computational work of the skeletons between multiple processing units, such as between a CPU and a GPU. The results show an improvement in execution time with the hybrid execution implementation for all skeletons in SkePU. It is also shown that the new implementation results in a lower and more predictable execution time compared to a dynamic scheduling approach based on an earlier implementation of hybrid execution in SkePU.

  • 668.
    Öhlin, Petra
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Prioritizing Tests with Spotify’s Test & Build Data using History-based, Modification-based & Machine Learning Approaches2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis intends to determine the extent to which machine learning can be used to solve the regression test prioritization (RTP) problem. RTP is used to order tests with respect to probability of failure. This will optimize for a fast failure, which is desirable if a test suite takes a long time to run or uses a significant amount of computational resources. A common machine learning task is to predict probabilities; this makes RTP an interesting application of machine learning. A supervised learning method is investigated to train a model to predict probabilities of failure, given a test case and a code change. The features investigated are chosen based on previous research of history- based and modification-based RTP. The main motivation for looking at these research areas is that they resemble the data provided by Spotify. The result of the report shows that it is possible to improve how tests run with RTP using machine learning. Nevertheless, a much simpler history- based approach is the best performing approach. It is looking at the history of test results, the more failures recorded for the test case over time, the higher priority it gets. Less is sometimes more. 

  • 669.
    Östman, Nicklas
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Lindström, Rasmus
    Linköping University, Department of Computer and Information Science, Software and Systems.
    Vertically Scaling Agile: A Multiple-Case Study2017Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The conceptual framework of agile software development is an ever-growing movement in the software industry. However, recent studies have shown that large, less software-focused companies, where software development is primarily used for in-house IT-solutions, struggle with giving up traditional command-control type of management. This hits hard on some of the most important principles of agile software development and in many cases this phenomenon has inevitably led to large gaps between development teams and more managerial parts of the organization. This thesis has aimed to study this gap and investigate how it affects software development teams’ ability to carry out their work.

    By comparing three software teams that were internally highly similar but with varying external conditions, impact on the teams’ behaviour based on their different environments was studied. The study was carried out using a multiple-case study approach with primary data sources consisting of survey gathered data from all team members and interviews with a subset of the team members. The results gathered from this study suggest that agile development teams are extremely dependent on a well-functioning interface to business related parts of an organization. Regarding teams’ ability to make decisions and being agile in their way of working, the results primarily isolate impediments with roots in an unwillingness to adhere to and lack of understanding of agile principles.

    In this thesis, our gathered results were also correlated with a modern framework called Flow in order to confirm its relevance regarding analyzing software development teams in large-scale environments. 

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