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  • 551.
    Tajammul, Muhammad Adeel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shami, Muhammad Ali
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Segmented bus based path setup scheme for a distributed memory architecture2012In: Proceedings - IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012, IEEE , 2012, p. 67-74Conference paper (Refereed)
    Abstract [en]

    This paper proposes a composite instruction for path setup and partitioning of a network on chip using segmented buses. The network connects a distributed memory to a coarse grained reconfigurable architecture. The scheme decreases the partitioning and routing instruction in sequencers (S) for the nodes (N) from Nx3 to a single instruction. This reduction in instruction also bear a small performance benefit as less instructions are scheduled onto the network. Furthermore, it is possible to optimizing the system under application specificconstraints. A simple use-case with experiments is defined to show for design trade-offs for these optimization decisions.

  • 552.
    Tajammul, Muhammad Adeel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shami, Muhammad Ali
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Moorthi, Sridharan
    NIT, Trichi, India.
    NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture2011In: 24th Annual Conference on VLSI Design, IEEE Computer Society, 2011, p. 232-237Conference paper (Refereed)
  • 553.
    Tajammul, Muhammad Adeel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shami, Muhammad Ali
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Moorthi, Sridharan Moorthi
    NIT,Trichy,India .
    A NoC based distributed memory architecture with programmable and partitionable capabilities2010In: 28th Norchip Conference, NORCHIP 2010, 2010Conference paper (Refereed)
    Abstract [en]

    The paper focuses on the design of a Network-on-chip based programmable and partitionable distributed memory architecture which can be integrated with a Coarse Grain Reconfigurable Architecture (CGRA). The proposed interconnect enables better interaction between computation fabric and memory fabric. The system can modify its memory to computation element ratio at runtime. The extensive capabilities of the memory system are analyzed by interfacing it with a Dynamically Reconfigurable Resource Array (DRRA), a CGRA. The interconnect can provide multiple interfaces which supports upto 8 GB/s per interface.

  • 554. Tammemae, Kalle
    et al.
    O’Nils, Mattias
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    Hardware/Software Cosynthesis for Reconfigurable Systems1996In: Proceedings of IEE Colloquium Hardware-Software Cosynthesis for Reconfigurable Systems, 1996Conference paper (Refereed)
  • 555.
    Tammemäe, Kalle
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    O’Nils, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems1996In: Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 1996, p. 193-199Conference paper (Refereed)
  • 556.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Empowering the Engineering Education2010Conference paper (Other academic)
  • 557.
    Tuuna, S.
    et al.
    Turku Centre for Computer Science (TUCS).
    Nigussie, E.
    Turku Centre for Computer Science (TUCS).
    Isoaho, J.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Modeling of energy dissipation in RLC current-mode signaling2012In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 20, no 6, p. 1146-1151Article in journal (Refereed)
    Abstract [en]

    In this paper, energy dissipation in resistance-inductance-capacitance (RLC) current-mode signaling is modeled. The energy dissipation is derived separately for driver, wire, and receiver termination. The effects of rise time and clock cycle are included. A realizable Pi-model for the driving-point impedance of an RLC current-mode transmission line is derived. The output current of an RLC current-mode transmission line is also derived. The model is extended to multiple parallel coupled interconnects with inductive and capacitive coupling between them. The model is verified by comparing it to HSPICE in 65-nm technology and applied to differential current-mode signaling.

  • 558.
    Uddin, Saif
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An improved transmission scheme for error-prone inter-chip Network-on-Chip communication links implemented on FPGAs2013In: 10th FPGAworld Conference - Academic Proceedings 2013, FPGAworld 2013, 2013Conference paper (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is an alternative to traditional busses for faster interconnect mechanism. The aim is to have infinite scalability, and this implies the possibility to extend the on-chip NoC communication protocol off-chip. To gain wholesome advantage of Network-on-Chip (NoC), off-chip extensions should also have similar communication throughput compared to the on-chip network. Faster data-rate is the single most demanded requirement of modern applications. There is a continuous drive to fulfill this escalating demand as much as possible. Two of the most prominent limiting factors in achieving this purpose are 'reduced accuracy' and 'protocol handling', especially in case of systems which do not have synchronous communication. Efficient optimizations are needed in multiple areas to upgrade the speed of data transfer. This paper presents an improved off-chip network solution to a slower and error-prone board-bridge part of a Network-on-Chip (NoC). The new solution increases the accuracy and speed of the plesiochronous off-chip extension to the NoC. The Network-on-Chip has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards in 4x4 configuration in such a way that each board hosts a Quad-core NoC.

  • 559.
    Uddin, Saif
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach2012In: NORCHIP, 2012, IEEE , 2012, p. 6403128-Conference paper (Refereed)
    Abstract [en]

    To make systems infinitely scalable is the holy grail of chip design and crux that needs to be solved in order to invent a sustainable design methodology. Network-on-Chip (NoC) has been suggested as this solution as it replaces the traditional buses for on-chip interconnection purposes. However, to reach infinite scalability, off-chip extensions to the NoC protocols are needed in order to maintain scalability at an affordable cost of manufacturability. Going off-chip introduces more levels of complexity when it comes to testing, not only should the chip testing be speedy, the off-chip connections must also be testable in a fast manner, the fastest way being a set of BISTs testing the whole structure in parallel. In this paper, we present a BIST approach for testing an off-chip NoC protocol used in a 4x4 Network-on-Chip configuration. It has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards, each board hosting a Quad-core NoC.

  • 560.
    Ungureanu, George
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Reinhold, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zapka, Werner
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Parallel software design enabling high-speed reliability testing of inkjet printheads2013In: International Conference on Digital Printing Technologies, 2013, p. 60-65Conference paper (Refereed)
    Abstract [en]

    With new functional applications emerging in the digital printing industry, the need for quantitative knowledge of the reliability of drop-on-demand inkjet printheads increases. Continuous ink circulation using TF Technology™and the resulting channel self-recovery is one of the technologies which decrease the down-time of a single nozzle, but in turn increase the difficulty of an accurate reliability test. Current measuring techniques, namely the a-posteriori verification of printouts on paper proved to be inappropriate. This paper proposes a novel software approach, exploiting signal processing techniques, strong control loops and powerful system design methodologies in order to allow for the correct detection of single missing droplets at run-time. This new system is meant to relieve the effects of the indefinite environment and sources of human error. Preliminary results and the proof-ofconcept demonstrates both the system's and the design method's versatility and potential.

  • 561.
    Vanfretti, Luigi
    et al.
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Baudette, Maxime
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Al-Khatib, Iyad
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Almas, Muhammad Shoaib
    KTH, School of Electrical Engineering (EES), Electric Power Systems.
    Gjerde, Jan Ove
    Testing and Validation of a Fast Real-Time Oscillation Detection PMU-Based Application for Wind-Farm Monitoring2013In: 2013 First International Black Sea Conference on Communications and Networking (BlackSeaCom), IEEE conference proceedings, 2013, p. 216-221Conference paper (Refereed)
    Abstract [en]

    This article provides an overview of a monitoring application, its testing and validation process. The application was developed for the detection of sub-synchronous oscillations in power systems, utilizing real-time measurements from phasor measurement units (PMUs). It uses two algorithms simultaneously to both detect the frequency at which the oscillatory event occurs and the level of energy in the oscillations. The application has been developed and tested in the framework of SmarTS Lab, an environment capable of hardware-in-the-loop (HIL) simulation. The necessary components of the real-time chain of data acquisition are presented in this paper, as well as testing and validation results, to demonstrate the accuracy of the monitoring tool and the feasibility of fast prototyping for real-time PMU measurements based applications using the SmarTS Lab environment.

  • 562.
    Vasile, Massimiliano
    et al.
    Univ. of Strathclyde.
    Cartmell, Matthew
    Univ. of Glasgow.
    Zerihun Dejene, Firew
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Drysdale, T.
    Alaniz Flores, Monica
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Gulzar, Muhammad
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ismail, N.
    Khalid, Muhammad Usman
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, M.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Maddock, C.
    Mallol, Pau
    KTH, School of Engineering Sciences (SCI), Mechanics, Structural Mechanics.
    Mathieson, A.
    McRobb, M.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Purcell, O.
    Reynolds, P.
    Ritterbusch, Rafael
    KTH, School of Engineering Sciences (SCI), Mechanics.
    Sandqvist, William
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Summerer, L.
    Tanveer, Muhammad Usman
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tibert, Gunnar
    KTH, School of Engineering Sciences (SCI), Mechanics, Structural Mechanics.
    Whyte, G.
    Zafar, W.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, J.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    The Suaineadh Project: a Stepping Stone Towards the Deployment of Large Flexible Structures in Space2010In: Proceedings of the 61st International Astronautical Congress, the International Astronautical Federation , 2010, p. IAC-10-C3.4-Conference paper (Refereed)
    Abstract [en]

    The Suaineadh project aims at testing the controlled deployment and stabilization of space web. The deployment system is based on a simple yet ingenious control of the centrifugal force that will pull each of the four daughters sections apart. The four daughters are attached onto the four corners of a square web, and will be released from their initial stowed configuration attached to a central hub. Enclosed in the central hub is a specifically designed spinning reaction wheel that controls the rotational speed with a closed loop control fed by measurements from an onboard inertial measurement sensor. Five other such sensors located within the web and central hub provide information on the surface curvature of the web, and progression of the deployment. Suaineadh is currently at an advanced stage of development: all the components are manufactured with the subsystems integrated and are presently awaiting full integration and testing. This paper will present the current status of the Suaineadh project and the results of the most recent set of tests. In particular, the paper will cover the overall mechanical design of the system, the electrical and sensor assemblies, the communication and power systems and the spinning wheel with its control system.

  • 563.
    Wan, Qiansu
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Yang, Geng
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Electrical performance of inkjet printed flexible cable for ECG monitoring2011Conference paper (Refereed)
    Abstract [en]

    This paper presents electrical performance of paper based inkjet printed flexible cable for wearable electrocardiogram (ECG) monitoring. The cable is fabricated by inkjet printing of nano-silver wires on paper which connect bio electric electrodes with wireless transmission of ECG signals to the central medical device. The cable consists of printed metal traces and a shielding line in the middle. The experiment results show that a reliable performance with high quality ECG data can be transmitted on the inkjet printed flexible cable.

  • 564. Wang, Jiazhen
    et al.
    Xu, Jun
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. Fudan University, Shanghai, China.
    Ren, Junyan
    Design of an analog front-end for ambulatory biopotential measurement systems2010In: Journal of Semiconductors, ISSN 1674-4926, Vol. 31, no 10, p. 105004-Article in journal (Refereed)
    Abstract [en]

    A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms (0.48-2000 Hz). The chip is fabricated via a SMIC 0.18 μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.

  • 565.
    Wang, Peng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A novel low-power fully-differential current-reuse cascaded CG-CS-LNA for 6-9-GHz UWB receivers2010In: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, 2010, p. 1188-1191Conference paper (Refereed)
    Abstract [en]

    This paper proposes a novel low-power fully-differential ultra-wideband (UWB) low noise amplifier (LNA) for 6-9-GHz UWB receivers in digital 90nm CMOS. The capacitive cross-coupled common-gate (CG) stage is cascaded with a cross-coupled common-source (CS) second stage to perform the wideband input impedance matching, low noise figure (NF), low power, and flat-high-wideband gain which is due to the stagger tuning amplification. The DC power consumption is further reduced by the current-reuse topology. The simulation results achieve the minimum NF of 2.55dB, maximum voltage gain of 24.8dB with 3-dB bandwidth of 6-9-GHz, and IIP3 of 3.57dBm at 9GHz. The return loss is less than -12dB in the desired band because of the CG stage as the input stage. The proposed UWB LNA consumes 2.3mW core DC power at 1V supply voltage.

  • 566.
    Wang, Peng
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Sarmiento Mendoza, David
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A 3.1-4.8-GHz energy-detector front-end for non-coherent OOK impulse-radio UWB2010In: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, IEEE , 2010, p. 485-488Conference paper (Refereed)
    Abstract [en]

    This paper proposes a 0-33.3Mb/s front-end of the energy detector for 3.1-4.8-GHz impulse-radio ultra-wideband (IR-UWB). Fully differential architecture with the non-coherent on-off-keying (OOK) modulation is adopted. Targeting at - 98dBm sensitivity, the low noise amplifier (LNA) is designed to achieve <3.5dB noise figure, <-10dB S11, and >15dB gain. Interleaved integrating scheme relaxes the implementation of digital circuits. Thanks to the duty-cycling, the front-end achieves 420pJ/bit energy efficiency for OOK modulation. The bias is generated by band-gap circuits. The layout design and verification are completed with Cadence Spectre using UMC 90nm CMOS.

  • 567.
    Weerasekera, Roshan
    et al.
    Centre for Microsystems Engineering, Faculty of Science and Technology, Lancaster University.
    Grange, M.
    Centre for Microsystems Engineering, Faculty of Science and Technology, Lancaster University.
    Pamunuwa, Dinesh
    Centre for Microsystems Engineering, Faculty of Science and Technology, Lancaster University.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits2010In: Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, 2010, p. 1325-1328Conference paper (Refereed)
    Abstract [en]

    This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.

  • 568.
    Weldezion, Awet Yemane
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Grange, M.
    Pamunuwa, D.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns2013In: 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013, IEEE , 2013, p. 6702365-Conference paper (Refereed)
    Abstract [en]

    This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.

  • 569.
    Weldezion, Awet Yemane
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Weerasekara, Roshan
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Design Space Exploration of Clock-pumping Techniques to Reduce Through-Silicon-Via (TSV) Manufacturing Cost In 3-D Integration2012In: Proceedings of the 2012 IEEE 14th Electronics Packaging Technology Conference, EPTC 2012, IEEE , 2012, p. 19-22Conference paper (Refereed)
    Abstract [en]

    In this paper, we explore the cost of clock pumping techniques implemented for scalable 3-D Integrated Systems in the complexity of interconnect, circuit, and architecture level changes. Their effect in terms of area and power for comparable performance is estimated. Our results show that by using 50% of the number of TSVs, we achieve the same performance as standard implementation with insignificant area and power overhead from the overall system cost. The proposed pumping technique can be used as one of the components in 3-D systems design for several applications that require logic-on-logic or memory-on-logic stacking.

  • 570. Westman, Fredrik
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Tommy
    Hedqvist, Christer
    Hemani, Ahmed
    A Robust CMOS Bluetooth Radio/Modem System-on-Chip2002In: IEEE Circuit and Systems Magazine, p. 7-9Article in journal (Refereed)
  • 571. Wu, Yue
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kim, Hong-Sun
    Ismail, Mohammed
    Olsson, Håkan
    Analysis of Non-linearities of CMOS Low Noise Amplifier1999In: Proc. 17th Norchip Conference, 1999, p. 189-196Conference paper (Refereed)
  • 572. Wu, Yue
    et al.
    Kim, Hong-Sun
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ismail, Mohammed
    Olsson, Håkan
    Nonlinearity Analysis of a Short Channel CMOS Circuit for RF IC Applications1999In: Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration:Systems on a Chip, Kluwer Academic Publishers, 1999, p. 61-68Conference paper (Refereed)
  • 573.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Heterogeneous Integration of Silicon and Printed Electronics for Intelligente Sensing Devices2014Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Driven by the exploding popularity of the Internet-of-Things (IoT), the demand for thin, flexible, lightweight intelligent sensingdevices is growing rapidly. Two attractive examples are intelligent packaging and wearable healthcare monitoring devices, which help to connect and track / monitor everything / everybody at any time and in any place. The remarkably swift development of flexible and printed electronics is promoting new possibilities for cost-effective manufacturing of such devices. However, compared with silicon-based circuits, state-of-the-art all-printed circuits are encountering low integration density, long switching time and corresponding high cost per function. Therefore, a heterogeneous platform is in great demand, which employs a cost-effective, large-area manufacturing technique while keeping the same complex functionality and processing capability as silicon-based systems. Due to temperature and mechanical reasons, traditional silicon integration methods, such as solder bonding and wire bonding, are not suitable for flexible printed electronics. This thesis aims to develop a generally applicable hetero-geneous integration platform for the realization of intelligent sensing devices on flexible substrates.

    First, inkjet printing technique is introduced and studied. As the basic and key element, inkjet printing technology is employed to fabricate interconnections as well as electrodes of the printed sensors. Novel flexible media, plastic and paper, are evaluated as the substrates of printed electronic systems from two aspects: the electrical characteristics and performance reliability. In addition to widely used inkjet/photo paper, packaging paper is presented as a promising candidate for intelligent packaging applications due to the advantages in terms of lower price, higher temperature endurance and better reliability against 85◦/85% RH aging.

    Second, the heterogeneous integration platform enabled byinkjet printing is presented. Benefiting from the non-contact, accurate alignment and fine resolution features, this integration technique has the advantages of simplified fabrication process and multi-substrate compatibility. The design rules have been studied and the integration process is optimized for silicon chips with/without packaging.

    Finally, to verify the suitability, the heterogeneous integration platform is applied to two representative applications, each with unique emphasis and requirements.

    For intelligent packaging, low-cost is one crucial requirement. Paper substrate is selected because it is cost-effective, recyclableand a commonly-used packaging material in industry. In order to fit into non-regular shape pack-ages, the intelligent packaging needs to be bent or folded, which brings about reliability concern for paper electronics. Therefore, bending and folding tests are applied to reveal the capability and the limitation of paper electronics in terms of flexibility. For applications such as fresh food tracking, humidity is an important physical quantity to monitor during transportation and storage. Therefore, a resistive humidity sensor based on multi-walled carbon nanotubes is fabricated and integrated. A commercial packaged microcontroller is used to sense and store the resistance of the sensor and control the LEDs to indicate the ambient humidity level. By integratingthe microcon-troller, LEDs and a switch with the printed sensor and battery, a prototype of a paper-based humidity sensor card is implemented.

    For the healthcare application, user comfort is an essential element. Future long-term healthcare devices require a bio-sensing system which is small, thin, lightweight and wearable, has a long-battery life, and is easy to customize. The heterogeneous platform offers a promising solution for such systems from three aspects. 1) A fully integrated system-on-chip (SoC) is embedded to detect and process the bio-signal. The SoC solution features tiny size and low-power consumption, which contribute to system miniaturization and long battery lifetime. 2) Inkjet printing offers a cost-effective approach to fabricate personalized electrodes. 3) Inkjet printed interconnections enable the direct integration of the bare die instead of the packaged chip. This significantly reduces the physical size of the system, simplifies the manufacture process and lowers the cost. The concept is demonstrated by aminiaturized wearable Bio-Patch with the size of 4.5 cm×2.5 cm.

  • 574.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Feng, Yi
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mantysalo, Matti
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Integration of f-MWCNT Sensor and Printed Circuits on Paper Substrate2013In: IEEE Sensors Journal, ISSN 1530-437X, E-ISSN 1558-1748, Vol. 13, no 10, p. 3948-3956Article in journal (Refereed)
    Abstract [en]

    The integration of sensors endows the packages with intelligence and interactivity. This paper is considered the most suitable substrate of smart packages because it is cost-effective, light, flexible, and recyclable. However, common concern exists regarding the reliability of paper-based system against bending and folding. In this paper, inkjet-printing of silver nanoparticles is used to form circuit pattern as well as interconnections for system integration on paper substrate. A humidity sensor made by functionalized multiwalled carbon nanotubes is fabricated on the same substrate. We evaluate the electrical performance of paper electronics and the reliability against bending and folding. The results reveal the capability and the limitation of paper electronics in terms of flexibility. The concept of a paper-based smart electronic system and the manufacture process are demonstrated by an interactive humidity sensor card prototype.

  • 575.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mantysalo, Matti
    TUT.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Feng, Yi
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lopez, Ana
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Inkjet Printing in System Integration: Printed Humidity Sensor-Box2012In: 2012 Flexible Electronics & Displays Conference, 2012Conference paper (Refereed)
  • 576.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mäntysalo, Matti
    TUT.
    Lopez, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Feng, Yi
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Electrical performance and reliability evaluation of inkjet-printed Ag interconnections on paper substrates2012In: Materials letters (General ed.), ISSN 0167-577X, E-ISSN 1873-4979, Vol. 88, p. 68-72Article in journal (Refereed)
    Abstract [en]

    Printing technology, especially inkjet printing, enables mass manufacturing of electronics on various substrate materials. Paper is one potential carrier for printed electronics to realize low-cost, flexible, recyclable smart packages. However, concerns exist regarding commonly used photo paper substrate, in terms of price and reliability against environmental variation. In this work, for the first time, ordinary low-cost and high-moisture-resistance package paper is investigated as an alternative to be the substrate of printed electronics. The surface morphology and electrical performance of inkjet printed interconnections on six different paper substrates from two categories (inkjet paper and package paper) are examined and compared. The printed interconnections on inkjet papers show smaller sheet resistance and better repeatability than those on package papers. However, low-cost package paper stands higher temperature and exhibits better reliability during 85°C/85 RH aging test. Package paper is suitable for smart package applications that have relaxed requirements of conductivity and high requests of moisture resistance.

  • 577.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shen, Jue
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Co-design of flip chip interconnection with anisotropic conductive adhesives and inkjet-printed circuits for paper-based RFID tags2011In: 2011 61st Electronic Components and Technology Conference, ECTC 2011, IEEE conference proceedings, 2011, p. 1752-1757Conference paper (Other academic)
    Abstract [en]

    In this paper we study the radio frequency performance of interconnect using anisotropic conductive film (ACF). A series of experiments are conducted in order to measure and model the electrical characteristics of inkjet-printed circuits on paper substrate as well as the impedance parameters of ACF interconnect at high frequency. Four-point measurement structure, time domain reflectometry (TDR), vector network analyzer (VNA) and de-embedded technology are used to ensure the accuracy of experiments. Equivalent circuit models are built based on the experimental results. Finally, these models are considered as parts of the matching network and circuit design for the RFID receiver, which can be co-designed for developing paper-based electronic systems. It is found that since the difference between RFID tags with and without ACF interconnects is negligible, the influence of ACF interconnects can be ignored for paper-based UHF RFID tag. ACF is a feasible interconnect material for paper-based RFID tags.

  • 578.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yang, Geng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mantysalo, Matti
    TUT.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A system-on-chip and paper-based inkjet printed electrodes for a hybrid wearable bio-sensing system2012In: Engineering in Medicine and Biology Society (EMBC), 2012 Annual International Conference of the IEEE, IEEE , 2012, p. 5026-5029Conference paper (Refereed)
    Abstract [en]

    This paper presents a hybrid wearable bio-sensing system, which combines traditional small-area low-power and high-performance System-on-Chip (SoC), flexible paper substrate and cost-effective Printed Electronics. Differential bio-signals are measured, digitized, stored and transmitted by the SoC. The total area of the chip is 1.5 × 3.0 mm2. This enables the miniaturization of the wearable system. The electrodes and interconnects are inkjet printed on paper substrate and the performance is verified in in-vivo tests. The quality of electrocardiogram signal sensed by printed electrodes is comparable with commercial electrodes, with noise level slightly increased. The paper-based inkjet printed system is flexible, light and thin, which makes the final system comfortable for end-users. The hybrid bio-sensing system offers a potential solution to the next generation wearable healthcare technology.

  • 579.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yang, Geng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mäntysalo, Matti
    Xu, Lin-Lin
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Heterogeneous integration of bio-sensing system-on-chip and printed electronics2012In: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, ISSN 2156-3357, Vol. 2, no 4, p. 672-682Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a heterogeneous integration platform for bio-sensing applications, which seamlessly integrates low-power silicon-based circuits with cost-effective printed electronics. A prototype of wearable Bio-Sensing Node is fabricated to investigate the suitability of this integration approach. A customized mixed-signal system-on-chip (SoC) with the size of 1.5× 3.0 mm2 is utilized to amplify, digitize, buffer, and transmit the sensed bio-signals. Inkjet printing technology is employed to print nano-particle silver ink on a flexible substrate to fabricate chip-on-flex, electrodes as well as interconnections. This additive and digital fabrication technology enables fast prototype of the customized electrode pattern. Its high accuracy and fine resolution features allow the direct integration of the bare die (the pad size of 65 μ m and pitch size of 90 μ m) on the flexible substrate, which significantly miniaturizes the wearable system. The optimal size and layout of printed electrodes are investigated through the in vivo test for electrocardiogram recording applications. The total size of the implemented Bio-Sensing Node is 4.5× 2.5 cm2, which is comparable with a commercial electrode. This inkjet printed heterogeneous integration approach offers a promising solution for the next-generation cost-effective personalized wearable healthcare monitoring devices.

  • 580.
    Xie, Li
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yang, Geng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Xu, Linlin
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Seoane, Fernando
    KTH, School of Technology and Health (STH), Medical Engineering, Medical sensors, signals and systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. State Key Laboratory of ASICs and Systems, Fudan University, 200433, Shanghai, China .
    Characterization of dry biopotential electrodes2013In: Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS, 2013, p. 1478-1481Conference paper (Refereed)
    Abstract [en]

    Driven by the increased interest in wearable long-term healthcare monitoring systems, varieties of dry electrodes are proposed based on different materials with different patterns and structures. Most of the studies reported in the literature focus on proposing new electrodes and comparing its performance with commercial electrodes. Few papers are about detailed comparison among different dry electrodes. In this paper, printed metal-plate electrodes, textile based electrodes, and spiked electrodes are for the first time evaluated and compared under the same experimental setup. The contact impedance and noise characterization are measured. The in-vivo electrocardiogram (ECG) measurement is applied to evaluate the overall performance of different electrodes. Textile electrodes and printed electrodes gain comparable high-quality ECG signals. The ECG signal obtained by spiked electrodes is noisier. However, a clear ECG envelope can be observed and the signal quality can be easily improved by backend signal processing. The features of each type of electrodes are analyzed and the suitable application scenario is addressed.

  • 581. Xu, Shaohui
    et al.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhu, Yiping
    Wang, Lianwei
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chu, Paul K.
    Modeling and Optimization of Thermoelements by a Combined Analytical and Numerical Method2014In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 43, no 2, p. 404-413Article in journal (Refereed)
    Abstract [en]

    A combined analytical and numerical process has been developed to model and optimize thermoelements. In this way, the performance of commercial n- and p-type thermoelectric materials can be optimized to deliver the maximum output power and conversion efficiency. The validity of the method is demonstrated using a silicon germanium unicouple.

  • 582. Xu, T. C.
    et al.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A study of Through Silicon Via impact to 3D Network-on-Chip design2010In: 2010 International Conference on Electronics and Information Engineering, ICEIE 2010, 2010, Vol. 1, p. V1333-V1337Conference paper (Refereed)
    Abstract [en]

    The adoption of a 3D Network-on-Chip (NoC) design depends on the performance and manufacturing cost of the chip. Therefore, a study of Through Silicon Via (TSV), that connects different layers of a 3D chip, is crucial. In this paper, we analysis the impact of TSV design in 3D NoCs. A 3D NoC with five layers is modeled based on modern 2D chips. We discuss the TSV number required for a 3D NoC. Different placements of half and quarter layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in full and half layer-layer connection are reduced by 5.24% and 2.18% respectively, compared with quarter design. Our analysis and experiment results provide a guideline for designing TSVs in 3D NoCs to leverage the trade-off between performance and manufacturing cost.

  • 583.
    Xu, T. C.
    et al.
    Turku Centre for Computer Science (TUCS).
    Liljeberg, P.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    An Optimized Network-on-Chip Design for Data Parallel FFT2012In: Procedia Engineering, ISSN 1877-7058, E-ISSN 1877-7058, Vol. 30, p. 311-318Article in journal (Refereed)
    Abstract [en]

    In this paper, we propose an optimized Network-on-Chip (NoC) design for data parallel FFT applications. NoC based architecture is proposed for future multicore processors due to its scalability. FFT is widely used in digital systems. The implementation of FFT on conventional architectures have been studied. However, the evaluation of data parallel FFT in a NoC platform has not been well addressed. We analyse data parallel FFT in terms of traffic patterns and propose an optimized NoC design. Experiments show that, the execution time of our optimized design is 12.13% faster than the original

  • 584. Xu, T. C.
    et al.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip2011In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011, 2011, p. 105-110Conference paper (Refereed)
    Abstract [en]

    In this paper, we analyze the performance impact of different number of Through Silicon Vias (TSVs) in 3D Network-on-Chip (NoC). The adoption of a 3D NoC design depends on the performance and manufacturing cost of the chip. Therefore, a study of the placement of the TSV, that connects different layers of a 3D chip, is crucial. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We discuss the number of TSVs required for a 3D NoC. Different placements of layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in two configurations (full and quarter connection) are reduced by 14.78% and 7.38% respectively, compared with the one-eighth connection design. The improvement of performance is a trade-off of manufacturing cost. Our analysis and experiment results provide a guideline for selecting optimal number of TSVs in 3D NoCs.

  • 585. Xu, T. C.
    et al.
    Yin, A. W.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A study of 3d network-on-chip design for data parallel h. 264 coding2011In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 35, no 7, p. 603-612Article in journal (Refereed)
    Abstract [en]

    In this paper, we implement, analyze and compare different Network-on-Chip (NoC) architectures aiming at higher efficiencies for MPEG-4/H.264 coding. Two-dimensional (2D) and three-dimensional (3D) NoCs based on Non-Uniform Cache Access (NUCA) are analyzed. We present results using a full system simulator with realistic workloads. Experiments show the average network latencies in two 3D NoCs are reduced by 28% and 34% respectively, comparing with 20 design. It is also shown that heat dissipation is a trade-off in improving performance of 3D chips. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications.

  • 586.
    Yang, Geng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Jian
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System2012In: Proceedings -Design, Automation and Test in Europe, DATE, 2012, p. 443-448Conference paper (Refereed)
    Abstract [en]

    This paper presents a fully integrated application specific integrated circuit (ASIC) sensor for the recording of multiple bio-electric signals. It consists of an analog front-end circuit with tunable bandwidth and programmable gain, a 6-input 8-bit successive approximation register analog to digital converter (SAR ADC), and a reconfigurable digital core. The ASIC is fabricated in a 0.18-μm 1P6M CMOS technology, occupies an area of 1.5 × 3.0 mm 2, and totally consumes a current of 16.7 μA from a 1.2 V supply. Incorporated with the ASIC, an Intelligent Electrode can be dynamically configured for on-site measurement of different bio-signals. A 2-wire data transmission protocol is also integrated on chip. It enables the serial connection over a group of Intelligent Electrodes, thus minimizes the number of connecting cables. A wearable healthcare system is built upon a printed Active Cable and a scalable number of Intelligent Electrodes. The system allows synchronous processing of maximum 14-channel bio-signals. The ASIC performance has been successfully verified in in-vivo bio-electric recording experiments.

  • 587.
    Yang, Geng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Jian
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A Hybrid Low Power Biopatch for Body Surface Potential Measurement2013In: IEEE Journal of Biomedical and Health Informatics, ISSN 2168-2194, Vol. 17, no 3, p. 591-599Article in journal (Refereed)
    Abstract [en]

    This paper presents a wearable biopatch prototype for body surface potential measurement. It combines three key technologies, including mixed-signal system on chip (SoC) technology, inkjet printing technology, and anisotropic conductive adhesive (ACA) bonding technology. An integral part of the biopatch is a low-power low-noise SoC. The SoC contains a tunable analog front end, a successive approximation register analog-to-digital converter, and a reconfigurable digital controller. The electrodes, interconnections, and interposer are implemented by inkjet-printing the silver ink precisely on a flexible substrate. The reliability of printed traces is evaluated by static bending tests. ACA is used to attach the SoC to the printed structures and form the flexible hybrid system. The biopatch prototype is light and thin with a physical size of 16 cm x 16 cm. Measurement results show that low-noise concurrent electrocardiogram signals from eight chest points have been successfully recorded using the implemented biopatch.

  • 588.
    Yang, Geng
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Design of a self-organized Intelligent Electrode for synchronous measurement of multiple bio-signals in a wearable healthcare monitoring system2010In: 2010 3rd International Symposium on Applied Sciences in Biomedical and Communication Technologies, ISABEL 2010, 2010Conference paper (Other academic)
    Abstract [en]

    This paper presents an Intelligent Electrodes and Active Cable based wearable medical system. Within each Intelligent Electrode, an Application Specific Integrated Circuit (ASIC) is integrated which includes a gain-bandwidth selectable analog front-end circuit, an 8-bit SAR ADC and a digital controller. The key of the ASIC is the analog front-end circuit with tunable gain and bandwidth which can be configured for Electrocardiogram (ECG), Electroencephalogram (EEG) or Electromyogram (EMG) measurement. Common mode interference is effectively rejected due to the circuit’s high Common Mode Rejection Ratio (CMRR), which is higher than 135 dB up to 100 Hz and better than 110dB up to 1 kHz. Since a dedicated data transmission protocol is implemented on chip, the Intelligent Electrodes can establish a self-organized network and perform synchronous measurements for multiple bio-signals.

  • 589.
    Yang, Geng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Wan, Qiansu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Bio-Chip ASIC and Printed Flexible Cable on Paper Substrate for Wearable Healthcare Applications2011In: Proceeding ISABEL '11 Proceedings of the 4th International Symposium on Applied Sciences in Biomedical and Communication Technologies, 2011Conference paper (Refereed)
    Abstract [en]

    In this paper, we describe two cutting-edge technologies for the emerging wearable healthcare applications: application specific integrated circuit (ASIC) and printed electronics on a flexible paper substrate. The ASIC enables a compact integration of active circuit blocks on a chip. Due to its tiny size, the ASIC makes the wearable unit unobtrusive and maximizes the wearer's comfort. The electrical performance of a paper based inkjet printed flexible cable is also exhibited. Combining the two technologies together, an example of electrocardiogram (ECG) signal recording is presented.

  • 590.
    Yang, Geng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mantysalo, Matti
    Zhou, Xiaolin
    Pang, Zhibo
    Xu, Li Da
    Kao-Walter, Sharon
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A Health-IoT Platform Based on the Integration of Intelligent Packaging, Unobtrusive Bio-Sensor, and Intelligent Medicine Box2014In: IEEE Transactions on Industrial Informatics, ISSN 1551-3203, E-ISSN 1941-0050, Vol. 10, no 4, p. 2180-2191Article in journal (Refereed)
    Abstract [en]

    In-home healthcare services based on the Internet-of-Things (IoT) have great business potential; however, a comprehensive platform is still missing. In this paper, an intelligent home-based platform, the iHome Health-IoT, is proposed and implemented. In particular, the platform involves an open-platform-based intelligent medicine box (iMedBox) with enhanced connectivity and interchangeability for the integration of devices and services; intelligent pharmaceutical packaging (iMedPack) with communication capability enabled by passive radio-frequency identification (RFID) and actuation capability enabled by functional materials; and a flexible and wearable bio-medical sensor device (Bio-Patch) enabled by the state-of-the-art inkjet printing technology and system-on-chip. The proposed platform seamlessly fuses IoT devices (e. g., wearable sensors and intelligent medicine packages) with in-home healthcare services (e. g., telemedicine) for an improved user experience and service efficiency. The feasibility of the implemented iHome Health-IoT platform has been proven in field trials.

  • 591.
    Yang, Geng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mäntysalo, Matti
    Department of Electronics, Tampere University of Technology.
    Chen, Jian
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Bio-Patch Design and Implementation Based on a Low-Power System-on-Chip and Paper-Based Inkjet Printing Technology2012In: IEEE transactions on information technology in biomedicine, ISSN 1089-7771, E-ISSN 1558-0032, Vol. 16, no 6, p. 1043-1050Article in journal (Refereed)
    Abstract [en]

    This paper presents the prototype implementation of a Bio-Patch using fully integrated low-power System-on-Chip (SoC) sensor and paper-based inkjet printing technology. The SoC sensor is featured with programmable gain and bandwidth to accommodate a variety of bio-signals. It is fabricated in a 0.18-µm standard CMOS technology, with a total power consumption of 20 µW from a 1.2 V supply. Both the electrodes and interconnections are implemented by printing conductive nano-particle inks on a flexible photo paper substrate using inkjet printing technology. A Bio-Patch prototype is developed by integrating the SoC sensor, a soft battery, printed electrodes and interconnections on a photo paper substrate. The Bio-Patch can work alone or operate along with other patches to establish a wired network for synchronous multiple-channel bio-signals recording. The measurement results show that electrocardiogram and electromyogram are successfully measured in in-vivo tests using the implemented Bio-Patch prototype.

  • 592.
    Yang, Geng
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Evaluation of non-contact flexible electrodes connected with a customized IC-steps towards a fully integrated ECG sensor2013In: NORCHIP, 2013, IEEE , 2013, p. 6702023-Conference paper (Refereed)
    Abstract [en]

    This study investigates the performance of a noncontact capacitive bioelectric sensor for electrocardiogram (ECG) measurement. A straightforward comparison is made on the measured ECG signals using conventional pre-gelled electrodes and the developed non-contact electrodes on a hairy chest, with the same bio-sensing readout circuits. The measurement results show that pre-gelled electrodes have difficulties in the measurement of ECG signal from a hairy chest. A pair of non-contact electrodes are designed and implemented on flexible copper foil. With the help of high performance readout circuits, ECG signal is successfully measured via implemented non-contact electrodes from a hairy chest. Discussions are made based on the preliminary in-vivo measurement results. It is believed that this non-contact ECG measurement approach brings a promising solution for the future fully integrated wearable ECG sensors.

  • 593.
    Yao, Chen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Jian
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A High-Resolution Time-to-Digital Converter Based on Parallel Delay Elements2012In: ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems, IEEE Solid-State Circuits Society, 2012, p. 3158-3161Conference paper (Refereed)
    Abstract [en]

    This paper presents a flash-type Time to Digital Converter (TDC) based on parallel delay elements in 65-nm CMOS process technology. By using parallel delay elements the conversion resolution of the TDC becomes equal to the difference of delay elements rather than the delay time of each element. A Sensed Amplifier Flip Flop (SAFF) ensures narrow sampling window. Operating at 1.2-V supply, this TDC shows 3ps resolution with 0.5LSB of INL and 0.33LSB of DNL respectively and consumes average power 442 mu W.

  • 594.
    Yao, Yuan
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems2014In: 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE , 2014, p. 343-348Conference paper (Refereed)
    Abstract [en]

    Flow regulation is a traffic shaping technique, which can be used to improve communication performance with better utilization of network resources in chip multi-processors (CMPs). This paper presents fuzzy flow regulation. Being different from the static flow regulation policy, our system makes regulation decisions fully dynamically according to traffic dynamism and the state of interconnection network. The central idea is to use fuzzy logic to mimic the behavior of an expert that can recognize the network status and then intelligently control the admission of input flows. As the experiment results show, the maximum improvement in average delay reaches 53.0% against static regulation and 37.4% against no regulation. The maximum improvement in average throughput reaches 37.5% against static regulation and 23.8% against no regulation.

  • 595. Yin, A. W.
    et al.
    Xu, T. C.
    Yang, B.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Change Function of 2D/3D Network-on-Chip2011In: 11th IEEE International Conference on Computer and Information Technology, CIT 2011, 2011, p. 181-188Conference paper (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) has been widely accepted as one of the most promising on-chip communication architectures for many-core Systems-on-Chip (SoC). With billions of transistors integrated on a single chip, inter-component communication becomes more and more complicated and power hungry. By leveraging the existing technologies of computer networks, NoC enables the on-chip communication to be simpler and more predictable. With the unceasing increase of the number of on-chip components, issues such as communication delay, system throughput, power consumption and large die area start to emerge in traditional two dimensional (2D) integrated circuits (ICs). During the recent years, more attentions than ever have been focused on three dimensional (3D) ICs in both industry and academia. However, 3D ICs are known to have higher cost in several aspects, including heat dissipation, yield, testing, etc., than their 2D counterparts. In this paper, we propose a method based on the economic term of change function to analyze the profitability of using 3D rather than 2D NoCs. We compare the benefits and costs between 2D and 3D NoCs and judgments are made based on the quantized results of these comparisons.

  • 596.
    Ykman-Couvreur, Ch.
    et al.
    IMEC.
    Lambrecht, J.
    IMEC.
    Verkest, D.
    IMEC.
    Svantesson, Bengt
    KTH, School of Information and Communication Technology (ICT).
    Kumar, Shashi
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Wolf, F.
    Technische Universität Braunschweig.
    System exploration and synthesis from SDL of an ATM switch component1999In: ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International, 1999, p. 119-124Conference paper (Refereed)
    Abstract [en]

    We describe the complete hardware synthesis of an ATM switch component, characterized by concurrent and dynamic processes, very high bit-rate data streams, and intensive data storage and transfer. The methodology used to synthesize it bridges the gap between an SDL system specification and an optimized single-chip implementation of communicating hardware processors, that satisfies stringent constraints on area, performance, and power. The novelty of this methodology is that through stepwise exploration, and gradual incorporation of timing constraints, it supports new optimization methods in view of memory and concurrency management, and expensive late iterations are avoided

  • 597. You, Yintao
    et al.
    Yang, Kunlong
    Yuan, Sijian
    Dong, Shiqi
    Zhang, Huotian
    Huang, Qinglan
    Gillin, William P.
    Zhan, Yiqiang
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    An organic multilevel non-volatile memory device based on multiple independent switching modes2014In: Organic electronics, ISSN 1566-1199, E-ISSN 1878-5530, Vol. 15, no 9, p. 1983-1989Article in journal (Refereed)
    Abstract [en]

    The demand for higher data density memory structures is greater today than ever before. Multilevel resistive organic memory devices (OMD) provide an ideal solution, in being easily fabricated, cost-effective and at the same time promising high storage capacity. However, conventional methods for multilevel OMDs impose demanding requirements on material properties and attain only limited performance. We hereby provide an alternative design concept that combines multiple switching modes in one device to realize multilevel function. The device possesses a simple structure by using a ferroelectric phase-separated blend as the active layer. Two switching modes, the ferroelectric switching and the metallic filament switching, are realized simultaneously in this device, and enable a ternary storage function. The cross-section scanning electron microscope (SEM) images provide a strong evidence of the formation and annihilation of the metallic filament.

  • 598.
    Zhai, Chuanying
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Software defined radio IR-UWB positioning platform for RFID and WSN application2012In: Ultra-Wideband (ICUWB), 2012 IEEE International Conference on, IEEE , 2012, p. 501-505Conference paper (Refereed)
    Abstract [en]

    This paper presents a software defined radio (SDR) platform for Impulse Ultra-Wideband (IR-UWB) sensing and positioning applications. The platform is composed by a software simulator (SW) and a hardware testbed (HW). The software simulator based on Matlab offers reconfigurable modules/functions of UWB systems with a graphic user interface (GUI). Correspondingly, the testbed is implemented by an oscilloscope and a set of off-the-shelf components. The oscilloscope (Lecroy WaveMaster 816Zi-A) features high-speed real-time sampling (i.e., 40 GS/s with 16 GHz analog bandwidth) with 4 independent channels, enabling a multi-antenna multichannel receiver network in UWB bands, with signal processing capability at the Nyquist rate. The SW and HW are seamlessly integrated by the build-in software in the oscilloscope. It allows rapid prototypes of various algorithms to be verified in real environments. Finally, a case study on UWB ranging for localization is given to demonstrate the feasibility and usability of the proposed platform.

  • 599.
    Zhai, Chuanying
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zhou, Qin
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A Software Defined Radio platform for passive UWB-RFID localization2012In: 2012 IEEE International Conference on Wireless Information Technology and Systems, ICWITS 2012, IEEE , 2012, p. 6417741-Conference paper (Refereed)
    Abstract [en]

    Radio-Frequency-Identification (RFID) with high sensing and positioning capability is the key technology enabler for the vision of the context-aware and location-aware computing towards the Internet-of-Things. However, the existing passive RFID in Ultra-High-Frequency (UHF) based on backscattering scheme can only provide limited ranging resolution and insufficient localization accuracy. Besides, it is sensitive to narrowband interference and multipath environment. Alternatively, Ultra-Wideband (UWB) has been recognized as a promising technology for the next generation RFIDs [1,2]. The Impulse-radio UWB (IR-UWB) implementations employ sub-nanosecond duration pulses without carrier, thus significantly reducing hardware complexity and power consumption. The wideband of the signals provide the potential of fine resolution in dense multipath scenarios. As one of the most attractive characteristics, UWB RFID potentially provides centimeter-level localization accuracy thanks to the ultrashort pulses with high time domain resolution by using time-of-arrival (ToA) estimation of the signal. There has been many works using UWB as active RFID tags for positioning and tracking application [3,4]. Moreover, in order to introduce UWB to passive RFID systems, UHF powered UWB-RFID system with asymmetric links has been proposed in [5]. Based on this UHF/UWB hybrid architecture, the positioning feasibility and ToA estimation has been studied in [6] in algorithm level.

  • 600. Zhan, Y.
    et al.
    Mei, Y.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Materials capability and device performance in flexible electronics for the Internet of Things2014In: Journal of Materials Chemistry C, ISSN 2050-7534, Vol. 2, no 7, p. 1220-1232Article in journal (Refereed)
    Abstract [en]

    The Internet of Things (IoT) has a broad vision of connecting every single object in the world to form one network. Flexible electronic devices, including RFIDs, sensors, memory devices, displays and power sources, are considered to be the technological basis of the IoT. The development of flexible electronic devices has been extremely rapid in the last decade. Many novel applications have been demonstrated, showing a strong potential impact on human life. In this review, we will summarize the recent progress in the research of flexible electronic devices and related flexible material within the framework of the IoT.

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