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  • 51.
    Sadeghifar, Mohammad Reza
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten. Ericsson AB, Sweden.
    Gustafsson, Oscar
    Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics2019Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 99, nr 2, s. 287-298Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Optimization problem formulation for semi-digital FIR digital-to-analog converter (SDFIR DAC) is investigated in this work. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital sigma modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in SDFIR DAC optimization problem formulation. It is shown in this work, that hardware cost of the SDFIR DAC, can be significantly reduced by introducing flexible coefficient precision while the SDFIR DAC is not over designed either. Different use-cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metrics are used in different use cases of optimization problem formulation and solved to find out the optimum set of analog FIR taps. A new method with introducing the variable coefficient precision in optimization procedure was proposed to avoid non-convex optimization problems. It was shown that up to 22% in the total number of unit elements of the SDFIR filter can be saved when targeting the analog metric as the optimization objective subject to magnitude constraint in pass-band and stop-band.

  • 52.
    Sharma, Vishal
    et al.
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
    Gopal, Maisagalla
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
    Singh, Pooran
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
    Vishvakarma1, Santosh Kumar
    Nanoscale Devices, VLSI Circuit and System Design Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore .
    Chouhan, Shailesh
    Luleå tekniska universitet, Institutionen för system- och rymdteknik, EISLAB.
    A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications2019Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 98, nr 2, s. 331-346Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    With the increased requirement of on-chip data computations in internet of things based applications, the embedded on-chip SRAM memory has been under its renovation stage to overcome the classical problems like stability and poor energy efficiency. In this work, a data-dependent-power-supply mechanism for a new 11T SRAM cell is proposed with ultra-low leakage and improved read/write stability against the process–voltage–temperature variations. The proposed cell consumes static power in the fraction of picowatt range and has considerable enhancement in the value of write static noise margin (WSNM). In addition, the use of associated read decoupling approach, with the column-based read buffer, further improves the read stability of the proposed cell and make it comparable with the hold stability value. The percentage reduction in the leakage power of proposed 11T cell is 99.97%">99.97% 99.97% , 99.93%">99.93% 99.93% and 99.97%">99.97% 99.97% , while the WSNM 1 is 6.98×">6.98× 6.98× , 3.12×">3.12× 3.12× and 1.46×">1.46× 1.46× , and WSNM 0 is 5.55×">5.55× 5.55× , 1.25×">1.25× 1.25× and 1.16×">1.16× 1.16× larger when operating at 0.4 V and compared to the conventional 6T and threshold voltage techniques based VTH_9T and data aware write assist (DAWA) 12T SRAM cell structures respectively. Iread/Ileak">I read /I leak  Iread/Ileak ratio for the proposed cell has improved by 6.55×">6.55× 6.55× , 6.22×">6.22× 6.22× and 5.11×">5.11× 5.11× when compared with the 6T, VTH_9T and DAWA12T SRAM to increase the memory density. Further, the post-layout Monte Carlo simulation results (2000 samples) confirm the robustness of the proposed cell against the process variations.

  • 53. Shi, C. L.
    et al.
    Wu, Y.
    Lin, C. H.
    Ismail, Mohammed
    Design and power optimization of high-speed pipeline ADC for wideband CDMA applications2001Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 26, nr 3, s. 229-238Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents a 7-bit 64 MS/s pipeline A/D converter suitable for wideband CDMA applications. Targeting at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed. Switched-Opamp technique is used to further reduce power consumption. This ADC is implemented in 0.5 mum standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s.

  • 54.
    Strak, Adam
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Gothenberg, Andreas
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Analysis of clock jitter effects in wideband sigma-delta modulators for RF-applications2004Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 41, nr 03-feb, s. 223-236Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents a theoretical overview and analysis of clock jitter in a switched capacitor (SC) Sigma-Delta (SigmaDelta) Analog-to-Digital Converter ( ADC). We start by defining three different types of jitter effects and proceed to analyze their impact, both mathematically and by simulations. The main jitter assumption throughout this analysis is that it is stochastic white Gaussian noise. Using this assumption, the SigmaDelta performance is characterized in terms of Signal-to-Jitter-Noise-Ratio (SJNR) for each jitter effect. Non-uniform sampling effects have, to some extent, been characterized in litterature ( S. R. Norsworthy, R. Schreier and G. C. Temes, Delta-Sigma Data Converters - Theory, Design and Simulation, IEEE Press, NewJersey, 1997). However, varying phase-length effects are also a main focus in this work since they can have a significant impact on the total ADC performance depending on settling accuracy and characteristic. Furthermore, because SC circuits usually operate on a two-phase clock, jitter may give rise to a secondary effect, phase overlap, which does not appear when dealing with a single-phase clock. This effect severely degrades the resolution of a SigmaDelta and therefore a thorough understanding of the interaction of jitter on the two phases is necessary.

  • 55.
    Sundström, Timmy
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS2010Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, nr 3, s. 215-222Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade‐offs. The redundancy removes the need to control comparator offsets, allowing the large process‐variation induced mismatch of small devices in nanometer technologies. This enables the use of small‐sized, ultra‐low‐power comparators with clock‐gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low‐power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.

  • 56.
    Svensson, Christer
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    The blocker challenge when implementing software defined radio receiver RF frontends2010Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, nr 2, s. 81-89Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Key blocker requirements of software defined radio receivers are identified from first principles. Three challenges are derived from these requirements, the need for passive filter banks or tunable passive filters, a very highly linear RF front-end and a high performance analog-to-digital converter. Each of these challenges is analyzed regarding possible solutions in the context of state-of-the art technology.

  • 57.
    Svensson, Christer
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Power consumption of analog circuits: a tutorial2010Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 65, nr 2, s. 171-184Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    A systematic approach to the power consumption of analog circuits is presented. The power consumption is related to basic circuit requirements, as dynamic range, bandwidth, noise figure and sampling speed and is considering basic device and device scaling behavior. Several kinds of circuits are treated, as samplers, amplifiers, filters and oscillators. The objective is to derive lower bounds to power consumption in analog circuits, to be used as design targets when designing power-constrained analog systems.

  • 58.
    Svärd, Daniel
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    Jansson, Christer
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska högskolan.
    Alvandpour, Atila
    Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
    A readout IC for an uncooled microbolometer infrared FPA with on-chip self-heating compensation in 0.35 mu m CMOS2013Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, nr 1, s. 29-44Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper describes a readout integrated circuit architecture for an infrared focal plane array intended for infrared network-attached video cameras in surveillance applications. The focal plane array consists of 352 x 288 uncooled thin-film microbolometer detectors with a pitch of 25 mu m, enabling ambient temperature operation. The circuit features a low-noise readout path, detector resistance mismatch correction and a non-linear ramped current pulse scheme for the electrical biasing of the detectors in order to relax the dynamic range requirement of amplifiers and the ADC in the readout channel, imposed by detector process variation and self-heating during readout. The design is implemented in a 0.35-mu m standard CMOS process and two versions of a smaller 32 x 32-pixel test chip have been fabricated and measured for evaluation. The latest test chip achieves a dynamic range of 97 dB and an input-referred RMS noise voltage of 6.4 mu V yielding an estimated NETD value of 26 mK with f/1 optics. At a frame rate of 60 FPS the chip dissipates 170 mW of power from a 3.4 V supply.

  • 59. Tang, Y. W.
    et al.
    Aktas, A.
    Ismail, Mohammed
    Bibyk, S.
    A high-speed low-power divide-by-15/16 dual modulus prescaler in 0.6 mu m CMOS2001Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 28, nr 2, s. 195-200Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    A new high-speed low-power dual modulus prescaler (DMP) topology is proposed. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4/5 divider, it has a higher speed by eliminating the NAND-gate introduced critical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFF's) required. Based on this topology, a divide-by-15/16 DMP is implemented in the 0.6 mum standard CMOS process. Simulation result shows that a maximum operating frequency of 2.15 GHz is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circuit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltage with 570 MHz input frequency.

  • 60.
    Tao, Sha
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rodriguez, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A 60 GHz receiver front-end in 65 nm CMOS2011Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 67, nr 1, s. 61-71Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of -13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm x 0.44 mm.

  • 61. Tarim, T. B.
    et al.
    Ismail, Mohammed
    Statistical design of a 10 bit current division network2001Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 29, nr 3, s. 221-229Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The statistical design of the 10 bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in the circuit is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuit is fabricated through the MOSIS 2 mum process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.

  • 62. Tarim, T. B.
    et al.
    Ismail, Mohammed
    Statistical design of the four-MOSFET structure2001Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 28, nr 1, s. 115-121Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor W and L values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 mum process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.

  • 63. Tarim, T. B.
    et al.
    Kuntman, H. H.
    Ismail, Mohammed
    Statistical design of low power square-law CMOS cells for high yield2000Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 23, nr 3, s. 237-248Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.

  • 64.
    Wang, Yinan
    et al.
    National University of Def Technology, Peoples R China.
    Johansson, Håkan
    Linköpings universitet, Institutionen för systemteknik, Kommunikationssystem. Linköpings universitet, Tekniska fakulteten.
    Xu, Hui
    National University of Def Technology, Peoples R China.
    Diao, Jietao
    National University of Def Technology, Peoples R China.
    Bandwidth-efficient calibration method for nonlinear errors in M-channel time-interleaved ADCs2016Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, nr 2, s. 275-288Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In order to enhance the effective resolution of time-interleaved analog-to-digital converters (TI-ADCs), both linear and nonlinear channel mismatches should be carefully calibrated. This paper concentrates on a bandwidth-efficient background calibration method for nonlinear errors in M-channel TI-ADCs. It utilizes the least-mean square algorithm as well as a certain degree of oversampling to achieve adaptive mismatch tracking. The calibration performance and computational complexity are investigated and evaluated through behavioral-level simulations. Furthermore, a calibration strategy for narrow-band input signals is proposed and verified as an improvement of the basic calibration structure for such signals.

  • 65.
    Wanhammar, Lars
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Vesterbacka, Mark
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Guest editorial2008Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 54, nr 2, s. 75-76Artikel i tidskrift (Övrigt vetenskapligt)
  • 66.
    Wikner, Jacob
    Linköpings universitet, Institutionen för systemteknik, Elektroniska Kretsar och System. Linköpings universitet, Tekniska fakulteten.
    Introduction to the special issue on NorCAS 2017, the 3rd Nordic circuits and systems conference2019Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 98, nr 3, s. 417-418Artikel i tidskrift (Övrigt vetenskapligt)
    Abstract [en]

    n/a

  • 67.
    Wikner, Jacob
    et al.
    Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
    Tan, Nianxiong
    Globespan Semiconducter, Inc., Red Bank, NJ, USA.
    Influence of Circuit Imperfections on the Performance of DACs1999Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 18, nr 1, s. 7-20Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Digital-to-analog converters are crucial building blocks for telecommunication applications. For this kind of applications, the traditional static performance requirements do not apply. The dynamic performance is of the greatest importance. This paper discusses the aspects of the performance of CMOS digital-to-analog converters and models the influence of non-idealities of circuit components (such as output impedance, mismatch, circuit noise, etc.) on the frequency-domain performance. Both deterministic and stochastic effects are modeled. The purpose of this modeling is to provide an insightful design guide for high dynamic performance CMOS digital-to-analog converters.

  • 68. Wu, Y.
    et al.
    Ismail, Mohammed
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Olsson, Håkan
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    A SiGeHBT translinear harmonic mixer2002Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 31, nr 1, s. 65-67Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    A novel even-order harmonic mixer is proposed. Based on the translinear loop of BJT/HBTs, frequency doubling and single-to-differential conversion circuits have been employed in the design of harmonic mixer. The proposed mixer has been verified in a SiGe HBT process by SpectreRF simulations.

  • 69. Wu, Y.
    et al.
    Shi, C. L.
    Ding, X. H.
    Ismail, Mohammed
    Olsson, Håkan
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Design of CMOS VHF/RF biquadratic filters2002Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 33, nr 3, s. 239-248Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper, a class of CMOS biquadratic filter suitable to work at VHF/RF frequency range is presented. The proposed circuit has a simple structure which is analyzed and designed according to a universal G(m)-C biquad filter. Simulation and experimental results show that these filters can work in GHz range and have wide tuning range.

  • 70. Younus, M. D. I.
    et al.
    Ismail, Mohammed
    Phase calibration technique for mismatch optimization in image-reject receivers2006Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 46, nr 2, s. 165-168Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents phase calibration technique without using any external tone for weaver image-reject receiver. Error signal (phase mismatch information) is generated using a simple algorithm and this signal is used for mismatch elimination. Calibration system has been implemented using simulink which shows an image rejection ratio of 59.5 dB can be achieved for RF signal operating at 1.8 GHz.

  • 71. Zhang, Ling
    et al.
    Kim, Hyung Joon
    Nadig, Vinay
    Ismail, Mohammed
    A 1.8 V tri-mode Sigma Delta modulator for GSM/WCDMA/WLAN wireless receiver2006Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, nr 3, s. 323-341Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The next generation of cellular systems will be increasingly similar to a data communication system. Not only will it transfer voice and multimedia data, it will also be integrated with WLAN to access Internet whenever possible. Thus these cellular systems need highly integrated multi-standard receivers. The design of the A/D converter in such receivers is a big challenge. A GSM/WCDMA/WLAN tri-mode receiver is first designed on the system level. A reconfigurable Sigma Delta modulator, which is suitable for GSM/WCDMA/WLAN receiver, is then proposed in this paper. According to the different signal bandwidth and Dynamic Range (DR) specifications, this Sigma Delta modulator is reconfigured to achieve the required dynamic range with less power consumption. The prototype is implemented in TSMC 0.18-mu m CMOS process with 1.8 V power supply. The circuit achieves signal-to-noise-and-distortion-ratio of 82 dB for GSM, 75 dB for WCDMA and 58 dB for WLAN.

  • 72.
    Zheng, Li-Rong
    et al.
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Design and analysis of power integrity in deep submicron system-on-chip circuits2002Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 30, nr 1, s. 15-29Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper proposes a new design methodology and new models for power integrity analysis in deep submicron system-on-chip circuit design. The placement plan and interconnect plan are the first design steps, preceding a priori signal and power integrity estimations. The initial power distribution is refined progressively from early mode to final placement and layout. In order to improve accuracy and efficiency in early stage estimates, a multilevel dynamic interconnect model and a fast power distribution model are employed, which consequently result in a drastic reduction of the number of iterations through the design cycle. HSPICE simulations verify the efficiency and the accuracy of the method. Finally, some noise-reduced power distribution techniques such as self-decoupling and area array power/ground pin distribution are discussed, and measurement result for effective power distribution is presented.

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