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  • 51.
    Navas, Byron
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Camera and LCM IP-Cores for NIOS SOPC System2009Inngår i: 6th FPGAworld Conference, Academic Proceedings 2009, New York: ACM , 2009, s. 18-23Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents the development of IP-Cores to integrate the Terasic DC2 Camera and LCM (LCD Module) daughter boards into an Altera Nios System, so that the image can be further processed by embedded software or custom hardware instructions. Among other challenges overcome during this work are clock-domain crossing, synchronizing FIFO design, variable and pipelined burst control, multi-masters contention for system memory and image frame buffer switching. In addition, we designed software device drivers, and API functions intended for graphics, image processing and video control; which are part of the IP deliverables. In a brief, this work describes some concepts and methodologies involved in the creation of IP-Cores for an Altera SOPC; it also presents the results of the designed CAM-IP and LCM-IP Cores working in an application demo, which constitutes a real solution and a reference design.

  • 52.
    Navas, Byron
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Reinforcement Learning Based Self-Optimization of Dynamic Fault-Tolerant Schemes in Performance-Aware RecoBlock SoCs2015Rapport (Annet vitenskapelig)
    Abstract [en]

    Partial and run-time reconfiguration (RTR) technology has increased the range of opportunities and applications in the design of systems-on-chip (SoCs) based on Field-Programmable Gate Arrays (FPGAs). Nevertheless, RTR adds another complexity to the design process, particularly when embedded FPGAs have to deal with power and performance constraints uncertain environments. Embedded systems will need to make autonomous decisions, develop cognitive properties such as self-awareness and finally become self-adaptive to be deployed in the real world. Classico-line modeling and programming methods are inadequate to cope with unpredictable environments. Reinforcement learning (RL) methods have been successfully explored to solve these complex optimization problems mainly in workstation computers, yet they are rarely implemented in embedded systems. Disruptive integration technologies reaching atomic-scales will increase the probability of fabrication errors and the sensitivity to electromagnetic radiation that can generate single-event upsets (SEUs) in the configuration memory of FPGAs. Dynamic FT schemes are promising RTR hardware redundancy structures that improve dependability, but on the other hand, they increase memory system traffic. This article presents an FPGA-based SoC that is self-aware of its monitored hardware and utilizes an online RL method to self-optimize the decisions that maintain the desired system performance, particularly when triggering hardware acceleration and dynamic FT schemes on RTR IP-cores. Moreover, this article describes the main features of the RecoBlock SoC concept, overviews the RL theory, shows the Q-learning algorithm adapted for the dynamic fault-tolerance optimization problem, and presents its simulation in Matlab. Based on this investigation, the Q-learning algorithm will be implemented and verified in the RecoBlock SoC platform.

  • 53.
    Navas, Byron
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    The RecoBlock SoC Platform: A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks2013Inngår i: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, s. 833-838Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Run-time reconfigurable (RTR) FPGAs combine the flexibility of software with the high efficiency of hardware. Still, their potential cannot be fully exploited due to increased complexity of the design process. Consequently, to enable an efficient design flow, we devise a set of prerequisites to increase the flexibility and reusability of current FPGA-based RTR architectures. We apply these principles to design and implement the RecoBlock SoC platform, which main characterization is (1) a RTR plug-and-play IP-Core whose functionality is configured at run-time; (2) flexible inter-block communication configured via software, and (3) built-in buffers to support data-driven streams and inter-process communications. We illustrate the potential of our platform by a tutorial case study using an adaptive streaming application to investigate different combinations of reconfigurable arrays and schedules. The experiments underline the benefits of the platform and shows resource utilization.

  • 54.
    Navas, Byron
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCs2015Inngår i: Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, artikkel-id 7238103Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Traditional embedded systems are evolving into power-and-performance-domain self-aware intelligent systems in order to overcome complexity and uncertainty. Without human control, they need to keep operative states in applications such as drone-based delivery or robotic space landing. Nowadays, the partial and run-time reconfiguration (RTR) of FPGA-based Systems-on-chip (SoC) can enable dynamic hardware acceleration or self-healing structures, but this conversely increases system-memory traffic. This paper introduces the basis of cognitive reconfigurable hardware and presents the design of an FPGA-based RTR SoC that becomes conscious of its monitored hardware and learns to make decisions that maintain a desired system performance, particularly when triggering hardware acceleration and dynamic fault-tolerant (FT) schemes on RTR cores. Self-awareness is achieved by evaluating monitored metrics in critical AXI-cores, supported by hardware performance counters. We suggest a reinforcement-learning algorithm that helps the system to search out when and which reconfigurable FT-scheme can be triggered. Executing random sequences of an embedded benchmark suite simulates unpredictability and bus traffic. The evaluation shows the effectiveness and implications of our approach.

  • 55.
    Navas, Byron
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. ESPE Universidad de Las Fuerzas Armadas, Ecuador .
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    On providing scalable self-healing adaptive fault-tolerance to RTR SoCs2014Inngår i: Proceedings of ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on, 2014, s. 1-6Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The dependability of heterogeneous many-core FPGA based systems are threatened by higher failure rates caused by disruptive scales of integration, increased design complexity, and radiation sensitivity. Triple-modular redundancy (TMR) and run-time reconfiguration (RTR) are traditional fault-tolerant (FT) techniques used to increase dependability. However, hardware redundancy is expensive and most approaches have poor scalability, flexibility, and programmability. Therefore, innovative solutions are needed to reduce the redundancy cost but still preserve acceptable levels of dependability. In this context, this paper presents the implementation of a self-healing adaptive fault-tolerant SoC that reuses RTR IP-cores in order to self-assemble different TMR schemes during run-time. The presented system demonstrates the feasibility of the Upset-Fault-Observer concept, which provides a run-time self-test and recovery strategy that delivers fault-tolerance over functions accelerated in RTR cores, at the same time reducing the redundancy scalability cost by running periodic reconfigurable TMR scan-cycles. In addition, this paper experimentally evaluates the trade-off of the implemented reconfigurable TMR schemes by characterizing important fault tolerant metrics i.e., recovery time (self-repair and self-replicate), detection latency, self-assembly latency, throughput reduction, and increase of physical resources.

  • 56.
    Navas, Byron
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    The Upset-Fault-Observer: A Concept for Self-healing Adaptive Fault Tolerance2014Inngår i: Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2014, IEEE Computer Society, 2014, s. 89-96Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Advancing integration reaching atomic-scales makes components highly defective and unstable during lifetime. This demands paradigm shifts in electronic systems design. FPGAs are particularly sensitive to cosmic and other kinds of radiations that produce single-event-upsets (SEU) in configuration and internal memories. Typical fault-tolerance (FT) techniques combine triple-modular-redundancy (TMR) schemes with run-time-reconfiguration (RTR). However, even the most successful approaches disregard the low suitability of fine-grain redundancy in nano-scale design, poor scalability and programmability of application specific architectures, small performance-consumption ratio of board-level designs, or scarce optimization capability of rigid redundancy structures. In that context, we introduce an innovative solution that exploits the flexibility, reusability, and scalability of a modular RTR SoC approach and reuse existing RTR IP-cores in order to assemble different TMR schemes during run-time. Thus, the system can adaptively trigger the adequate self-healing strategy according to execution environment metrics and user-defined goals. Specifically the paper presents: (a) the upset-fault-observer (UFO), an innovative run-time self-test and recovery strategy that delivers FT on request over several function cores but saves the redundancy scalability cost by running periodic reconfigurable TMR scan-cycles, (b) run-time reconfigurable TMR schemes and self-repair mechanisms, and (c) an adaptive software organization model to manage the proposed FT strategies.

  • 57.
    Navas, Byron
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Towards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysis2013Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Adoption of reconfigurable computing is limited in part by the lack of simplified, economic, and reusable solutions. The significant speedup and energy saving can increase performance but also design complexity; in particular for heterogeneous SoCs blending several CPUs, GPUs, and FPGA-Accelerator Cores. On the other hand, implementing complex algorithms in hardware requires modeling and verification, not only HDL generation. Most approaches are too specific without looking for reusability. Therefore, we present a solution based on: (1) a design methodology to develop algorithms accelerated in reconfigurable/non-reconfigurable IP-Cores, using common access tools, and contemplating verification from model to embedded software stages; (2) a generic accelerator core design that enables relocation and reuse almost independently of the algorithm, and data-flow driven execution models; and (3) a performance analysis of the acceleration mechanisms included in our system (i.e., accelerator core, burst I/O transfers, and reconfiguration pre-fetch). In consequence, the implemented system accelerates algorithms (e.g., FIR and Kalman filters) with speedups up to 3 orders of magnitude, compared to processor implementations.

  • 58. Paone, E.
    et al.
    Robino, Fransesco
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Palermo, G.
    Zaccaria, V.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Silvano, C.
    Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints2015Inngår i: Proceedings -Design, Automation and Test in Europe, DATE, IEEE conference proceedings, 2015, s. 736-741Konferansepaper (Fagfellevurdert)
    Abstract [en]

    When targeting an OpenCL application to platforms with multiple heterogeneous accelerators, task tuning and mapping have to cope with device-specific constraints. To address this problem, we present an innovative design flow for the customization and performance optimization of OpenCL applications on heterogeneous parallel platforms. It consists of two phases: 1) a tuning phase that optimizes each application kernel for a given platform and 2) a task-mapping phase that maximizes the overall application throughput by exploiting concurrency in the application task graph. The tuning phase is suitable for customizing parameterized OpenCL kernels considering device-specific constraints. Then, the mapping phase improves task-level parallelism for multi-device execution accounting for the overhead of memory transfers - overheads implied by multiple OpenCL contexts for different device vendors. Benefits of the proposed design flow have been assessed on a stereo-matching application targeting two commercial heterogeneous platforms.

  • 59.
    Penolazzi, Sandro
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Inferring energy and performance cost of RTOS in priority-driven scheduling2010Inngår i: 5th International Symposium on Industrial Embedded Systems, SIES 2010, 2010, s. 1-8Konferansepaper (Annet vitenskapelig)
  • 60.
    Penolazzi, Sandro
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Predicting bus contention effects on energy and performance in multi-processor SoCs2011Inngår i: 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, 2011, s. 1196-1199Konferansepaper (Annet vitenskapelig)
  • 61.
    Penolazzi, Sandro
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Predicting energy and performance overhead of Real-Time Operating Systems2010Inngår i: Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, 2010, s. 15-20Konferansepaper (Annet vitenskapelig)
  • 62.
    Raudvere, Tarvo
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A Synchronization Algorithm for Local Temporal Refinements in Perfectly Synchronous Models with Nested Feedback Loops2007Inngår i: GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, NEW YORK: ASSOC COMPUTING MACHINERY , 2007, s. 353-358Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Due to the abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification methods. In synchronous models, a local temporal refinement that increases the delay in a single computation block may affect the functionality of the entire model. To preserve the system's functionality after temporal refinements we provide a synchronization algorithm that applies also to models with nested feedback loops. The algorithm adds pure delay elements to the model in order to balance the delay caused by refinement and to assure concurrent data arrival at computation blocks. It is done so that the refined model stays latency equivalent to the original model. The advantages of our approach are that (a) we remain fully within the synchronous model of computation, (b) we preserve the functionality of the existing computation blocks, and (c) we do not require additional computation resources, wrapper circuits or schedulers.

  • 63.
    Raudvere, Tarvo
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Application and. verification of local nonsemantic-preserving transformations in system-design2008Inngår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 27, nr 6, s. 1091-1103Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Due to the increasing abstraction gap between the initial system model and a final implementation, the verification of the respective models against each other is a formidable task. This paper addresses the verification problem by proposing a stepwise application of combined refinement and verification activities in the context of synchronous model of computation. An implementation model is developed from the system model by applying pre-defined design transformations which are as follows: 1) semantic preserving or 2) nonsemantic preserving. Nonsemantic-preserving transformations introduce lower level implementation details, which are necessary to yield an efficient implementation. Our approach divides the verification tasks into two activities: 1) the local correctness of a refined block is checked by using formal verification tools and predefined properties, which are developed for each nonsemantic-preserving transformation, and 2) the global influence of the refinement to the entire system is studied through static analysis. We illustrate the design refinement and verification approach with three transformations: 1) a communication refinement mapping a synchronous channel to an asynchronous one including a handshake mechanism; 2) a computation refinement, which introduces resource sharing in a combinational computation block; and 3) a synchronization demanding refinement, where an algorithm analyzes the influence of a local refinement to the temporal properties of the entire system and restores the system's correct temporal behavior if necessary.

  • 64.
    Raudvere, Tarvo
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Synchronization after design refinements with sensitive delay elements2007Inngår i: Proceedings of the International Conference on HW/SW Codesign and System Synthesis, 2007Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at a high level of abstraction. In synchronous models, a local refinement increasing the delay in a single computation block may affect the functionality of the entire model. We provide a synchronization algorithm that preserves the system's functionality after design refinements, by using additional synchronization delays and making some delays sensitive to their input values. The refined and synchronized model stays latency equivalent to the original model. The advantages of our approach are the following: (a) we remain fully within the synchronous model of computation, (b) we preserve the functionality of the existing computation blocks, and (c) we do not require additional computation resources, specific communication protocols, wrapper circuits around computation blocks or schedulers.

  • 65.
    Raudvere, Tarvo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Sander, Ingo
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Singh, Ashish Kumar
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Gurov, Dilian
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    The ForSyDe semantics2002Inngår i: Proceedings of Swedish System-on-Chip Conference, 2002Konferansepaper (Fagfellevurdert)
  • 66.
    Raudvere, Tarvo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Sander, Ingo
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Singh, Ashish Kumar
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Verification of Design Decisions in ForSyDe2003Inngår i: Proceedings of the CODES-ISSS Conference, 2003Konferansepaper (Fagfellevurdert)
  • 67.
    Raudvere, Tarvo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Singh, Ashish Kumar
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Sander, Ingo
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Polynomial abstraction for verification of sequentially implemented combinational circuits2004Inngår i: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS / [ed] Gielen, G; Figueras, J, LOS ALAMITOS: IEEE COMPUTER SOC , 2004, s. 690-691Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Todays integrated circuits with increasing complexity cause the well known state space explosion problem in verification tools. In order to handle this problem a much simpler abstract model of the design has to be created for verification. We introduce the polynomial abstraction technique, which efficiently simplifies the verification task of sequential design blocks whose functionality can be expressed as a polynomial. Through our technique, the domains of possible values of data input signals can be reduced. This is done in such a way that the abstract model is still valid for model checking of the design functionality in terms of the system's control and data properties. We incorporate polynomial abstraction into the ForSyDe methodology, for the verification of clock domain design refinements.

  • 68.
    Raudvere, Tarvo
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Singh, Ashish Kumar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    System level verification of digital signal processing applications based on the polynomial abstraction technique2005Inngår i: ICCAD-2005: International Conference On Computer Aided Design, Digest Of Technical Papers, IEEE , 2005, s. 285-290Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Polynomial abstraction has been developed for data abstraction of sequential circuits, where the functionalily can be expressed as polynomials. The method, based on the fundamental theorem of algebra, abstracts a possibly infinite domain of input values, into a much smaller and finite one, whose size is calculated according to the degree of the respective polynomial. The abstract model preserves the system's control and data properties, which can be verified by model checking. Experiments show that our approach does not only allow an automatic verification, but also gives considerably better results than existing methods.

  • 69.
    Rosvall, Kathrin
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Khalilzad, Nima
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Ungureanu, George
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Throughput propagation in constraint-based design space exploration for mixed-criticality systems2017Inngår i: ACM International Conference Proceeding Series, Association for Computing Machinery (ACM), 2017, artikkel-id 3023977Konferansepaper (Fagfellevurdert)
    Abstract [en]

    When designing complex mixed-critical systems on multiprocessor platforms, a huge number of design alternatives has to be evaluated. Therefore, there is a need for tools which systematically find and analyze the ample alternatives and identify solutions that satisfy the design constraints. The recently proposed design space exploration (DSE) tool DeSyDe uses constraint programming (CP) to find implementations with performance guarantees for multiple applications with potentially mixed-critical design constraints on a shared platform. A key component of the DeSyDe tool is its throughput analysis component, called a throughput propagator in the context of CP. The throughput propagator guides the exploration by evaluating each design decision and is therefore executed excessively throughout the exploration. This paper presents two throughput propagators based on different analysis methods for DeSyDe. Their performance is evaluated in a range of experiments with six different application graphs, heterogeneous platform models and mixed-critical design constraints. The results suggest that the MCR throughput propagator is more efficient.

  • 70.
    Rosvall, Kathrin
    et al.
    KTH, Skolan för elektroteknik och datavetenskap (EECS).
    Mohammadat, Tage
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Ungureanu, George
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Öberg, Johnny
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Elektronik och inbyggda system.
    Sander, Ingo
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors2018Konferansepaper (Fagfellevurdert)
    Abstract [en]

    System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.

  • 71.
    Rosvall, Kathrin
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    A constraint-based design space exploration framework for real-time applications on MPSoCs2014Inngår i: Proceedings -Design, Automation and Test in Europe, DATE 2014, IEEE Computer Society, 2014, s. 1-6Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Design space exploration (DSE) is a critical step in the design process of real-time multiprocessor systems. Combining a formal base in form of SDF graphs with predictable platforms providing guaranteed QoS, the paper proposes a flexible and extendable DSE framework that can provide performance guarantees for multiple applications implemented on a shared platform. The DSE framework is formulated in a declarative style as interprocess communication-aware constraint programming (CP) model. Apart from mapping and scheduling of application graphs, the model supports design constraints on several cost and performance metrics, as e.g. memory consumption and achievable throughput. Using constraints with different compliance level, the framework introduces support for mixed criticality in the CP model. The potential of the approach is demonstrated by means of experiments using a Sobel filter, a SUSAN filter, a RASTA-PLP application and a JPEG encoder.

  • 72.
    Rosvall, Kathrin
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms2018Inngår i: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 23, nr 2, artikkel-id 21Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Due to its complexity, the problem of mapping and scheduling streaming applications on heterogeneous MPSoCs under real-time and performance constraints has traditionally been tackled by incomplete heuristic algorithms. In recent years, approaches based on Constraint Programming (CP) have shown promising results as complete methods for finding optimal mappings, in particular concerning throughput. However, so far none of the available CP approaches consider the tradeoff between throughput and buffer requirements or throughput and power consumption. This article integrates tradeoff awareness into the CP model and introduces a two-step solving approach that utilizes the advantages of heuristics, while still keeping the completeness property of CP. With a number of experiments considering several streaming applications and different platform models, the article illustrates not only the efficiency of the presented model but also its suitability for solving different problems with various combinations of performance constraints.

  • 73.
    Sander, Ingo
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Acosta, Alfonso
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Hardware Design and Synthesis in ForSyDe2009Inngår i: Proceedings of Hardware Design and Functional Languages, 2009Konferansepaper (Fagfellevurdert)
  • 74.
    Sander, Ingo
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Attarzadeh Niaki, Seyed Hosein
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Towards a Formal Software Synthesis Methodology for Embedded Multiprocessor Systems2011Inngår i: Proceedings of First International Software Technology Exchange Workshop 2011, 2011Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper addresses the increasing complexity of software design for multiprocessor embedded systems by proposing a designmethodology that combines a formal foundation based on the theory of models of computation (MoCs) and the industrial systemdesign language SystemC. The ForSyDe methodology provides thedesigner with SystemC class libraries that lead to executable system models, from which abstract analyzable models can be extracted. Using these abstract models, the design exploration andsynthesis process can make use of existing MoC theory by for instance incorporating efficient scheduling and buffer optimizationtechniques. The choice of SystemC as modeling language allowsfor an efficient implementation, since system model functions canbe directly compiled to target processors.

  • 75.
    Sander, Ingo
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Jantsch, A.
    Attarzadeh-Niaki, S. -H
    ForSyDe: System design using a functional language and models of computation2017Inngår i: Handbook of Hardware/Software Codesign, Springer Netherlands, 2017, s. 99-140Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    The ForSyDe methodology aims to push system design to a higher level of abstraction by combining the functional programming paradigm with the theory of Models of Computation (MoCs). A key concept of ForSyDe is the use of higher-order functions as process constructors to create processes. This leads to well-defined and well-structured ForSyDe models and gives a solid base for formal analysis. The book chapter introduces the basic concepts of the ForSyDe modeling framework and presents libraries for several MoCs and MoC interfaces for the modeling of heterogeneous systems, including support for the modeling of run-time reconfigurable processes. The formal nature of ForSyDe enables transformational design refinement using both semantic-preserving and nonsemantic-preserving design transformations. The chapter also introduces a general synthesis concept based on process constructors, which is exemplified by means of a hardware synthesis tool for synchronous ForSyDe models. Most examples in the chapter are modeled with the Haskell version of ForSyDe. However, to illustrate that ForSyDe is languageindependent, the chapter also contains a short overview of SystemC-ForSyDe.

  • 76.
    Sander, Ingo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Formal Design Based on the Synchronous Approach, Functional Models and Skeletons1999Inngår i: Proceedings of the Twelfth International Conference on VLSI Design, 1999Konferansepaper (Fagfellevurdert)
  • 77.
    Sander, Ingo
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Modelling Adaptive Systems in ForSyDe2008Inngår i: Electronical Notes in Theoretical Computer Science, ISSN 1571-0661, E-ISSN 1571-0661, Vol. 200, nr 2, s. 39-54Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Emerging architectures such as partially reconfigurable FPGAs provide a huge potential for adaptivity in the area of embedded systems. Since many system functions are only executed at particular points of time they can share an adaptive component with other system functions, which can significantly reduce the design costs. However, adaptivity adds another dimension of complexity into system design since the system behaviour changes during the course of adaptation. This imposes additional requirements on the design process, in particular system verification. In this paper we illustrate how adaptivity is treated as first-class citizen inside the ForSyDe design framework. ForSyDe is a transformational system design methodology, where an initial abstract system model is refined by the application of semantic-preserving and non-semantic preserving design transformations into a detailed model that can be mapped to an implementation. Since ForSyDe is based on the functional paradigm we can model adaptivity by using functions as signal values, which we use as the base for our concept of adaptive processes. Depending on the level of adaptivity we categorise four classes of adaptive process, spanning from parameter adaptive to interface adaptive process. We illustrate our concepts by two typical examples for adaptivity, where we also show the application of design transformations.

  • 78.
    Sander, Ingo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    System modeling and transformational design refinement in ForSyDe2004Inngår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 23, nr 1, s. 17-32Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The scope, of the Formal System Design (ForSyDe) methodology is high-level modeling and refinement of systems-on-a-chip and embedded systems. Starting with a formal specification model, that captures the functionality of the system at a high abstraction level, it provides formal design-transformation methods for a transparent refinement process of the system model into an implementation model that is optimized for synthesis. The main contribution of this paper is the ForSyDe modeling technique and the formal treatment of transformational design refinement. We introduce process constructors, that cleanly separate the computation part of a process from the synchronization and communication part. We develop the characteristic function for each process type and use it to define semantic preserving and design decision transformations. These transformations are characterized by name, the format of the original process network, the transformed process network, and a design implication. The implication expresses the relation between original and transformed process network by means of the characteristic function. The objective of the refinement process is a model that can be implemented cost efficiently. To this end, process constructors and processes have a hardware and software interpretation which shall facilitate accurate performance and cost estimations. In a study of a digital equalizer example, we illustrate the modeling and refinement process and focus in particular on refinement of the clock domain, communication refinement, and resource sharing.

  • 79.
    Sander, Ingo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    System Synthesis Based on a Formal Computational Model and Skeletons1999Inngår i: Proceedings of the IEEE Computer Society Annual Workshop on VLSI, 1999Konferansepaper (Fagfellevurdert)
  • 80.
    Sander, Ingo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    System Synthesis Utilizing a Layered Functional Model1999Inngår i: Proceedings of the 7th International Workshop on Hardware/Software Codesign, 1999, s. 136-141Konferansepaper (Fagfellevurdert)
  • 81.
    Sander, Ingo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Transformation Based Communication and Clock Domain Refinement for System Design2002Inngår i: Proceedings of Design Automation Conference, 2002Konferansepaper (Fagfellevurdert)
  • 82.
    Sander, Ingo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Lu, Zhonghai
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Development and application of design transformations in ForSyDe2003Inngår i: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 150, nr 5, s. 313-320Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The formal system design (ForSyDe) methodology has been developed for system level design. Starting with a formal specification model, which captures the functionality of the system at a high level of abstraction, it provides formal design transformation methods for a transparent refinement process of the specification model into an implementation model which is optimised for synthesis. The formal treatment of transformational design refinement is the central contribution of this article. Using the formal semantics of ForSyDe processes we introduce the term characteristic function to be able to define and classify transformations as either semantic preserving or design decision. We also illustrate how we can incorporate classical synthesis techniques that have traditionally been used with control/data-flow graphs as ForSyDe transformations. This approach avoids discontinuities as it moves design refinement into the domain of the specification model.

  • 83.
    Sander, Ingo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Lu, Zhonghai
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    The Development and Application of Formal Design Transformations in ForSyDe2003Inngår i: Proceedings of the Design Automation and Test Europe (DATE), 2003Konferansepaper (Fagfellevurdert)
  • 84.
    Sander, Ingo
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    The Platform as Interface in a SoC Design Curriculum2004Inngår i: Microelectronics Education: Proceedings of the 5th European Worksop on Microelectronics Education, 2004Konferansepaper (Fagfellevurdert)
  • 85.
    Sander, Ingo
    et al.
    KTH, Tidigare Institutioner, KTH Syd.
    Kolodziejski, Piotr
    KTH, Tidigare Institutioner, KTH Syd.
    Leibig, Jean-Pierre
    KTH, Tidigare Institutioner, KTH Syd.
    Using a digital recording machine as the main thread in a project based electrical engineering curriculum2001Inngår i: Proceedings of the 31st ASEE/IEEE Frontiers in Education Conference (FIE 2001), 2001, Vol. 3, s. 14-19Konferansepaper (Fagfellevurdert)
  • 86.
    Sander, Ingo
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zhu, Jun
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Herrholz, Andreas
    Hartmann, Philipp A.
    Nebel, Wolfgang
    High-Level Estimation and Trade-Off Analysis for Adaptive Real-Time Systems2009Inngår i: 2009 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, 2009, s. 2985-2988Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accurate design cost estimates at an early design stage. Given the size and computation time of a set of configurations, which can be derived through logic synthesis, our method gives estimates for configuration parameters, such as bitstream sizes, computation mid reconfiguration times. To fulfil the system's throughput requirements, the required FIFO buffer sizes are then calculated using a hybrid analysis approach based on integer linear programming and simulation. Finally, we are able to calculate the total design cost as the sum of the costs for the FPGA area, the required configuration memory and the FIFO buffers. We demonstrate our method by analysing non-obvious trade-offs for a static and dynamic implementation of adaptivity.

  • 87.
    Thid, Rikard
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Flexible bus and NoC performance analysis with configurable synthetic workloads2006Inngår i: DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings / [ed] Muthukumar, V, 2006, s. 681-688Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis method assists in the selection of a communication infrastructure early in the design process. The method uses (1) synthetic workload models which are similar to timed Petri nets and (2) the b-model for self-similar workloads. This allows the exploration of larger portions of the design space than possible with traditional stochastic models. The method is illustrated with tutorial examples where both a No C and a bus based platform are analyzed.

  • 88.
    Ungureanu, George
    et al.
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    de Medeiros, Jose E. G.
    Univ Brasilia, Elect Engn Dept, Brasilia, DF, Brazil..
    Sander, Ingo
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Bridging Discrete and Continuous Time Models with Atoms2018Inngår i: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE , 2018, s. 277-280Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Recent trends in replacing traditionally digital components with analog counterparts in order to overcome physical limitations have led to an increasing need for rigorous modeling and simulation of hybrid systems. Combining the two domains under the same set of semantics is not straightforward and often leads to chaotic and non-deterministic behavior due to the lack of a common understanding of aspects concerning time. We propose an algebra of primitive interactions between continuous and discrete aspects of systems which enables their description within two orthogonal layers of computation. We show its benefits from the perspective of modeling and simulation, through the example of an RC oscillator modeled in a formal framework implementing this algebra.

  • 89.
    Ungureanu, George
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Reinhold, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zapka, Werner
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Parallel software design enabling high-speed reliability testing of inkjet printheads2013Inngår i: International Conference on Digital Printing Technologies, 2013, s. 60-65Konferansepaper (Fagfellevurdert)
    Abstract [en]

    With new functional applications emerging in the digital printing industry, the need for quantitative knowledge of the reliability of drop-on-demand inkjet printheads increases. Continuous ink circulation using TF Technology™and the resulting channel self-recovery is one of the technologies which decrease the down-time of a single nozzle, but in turn increase the difficulty of an accurate reliability test. Current measuring techniques, namely the a-posteriori verification of printouts on paper proved to be inappropriate. This paper proposes a novel software approach, exploiting signal processing techniques, strong control loops and powerful system design methodologies in order to allow for the correct detection of single missing droplets at run-time. This new system is meant to relieve the effects of the indefinite environment and sources of human error. Preliminary results and the proof-ofconcept demonstrates both the system's and the design method's versatility and potential.

  • 90.
    Wu, Wenbiao
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Sander, Ingo
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Transformational System Design based on a Formal Computational Model and Skeletons2000Inngår i: Proceedings of the Forum on Design Languages, 2000Konferansepaper (Fagfellevurdert)
  • 91.
    Wu, Wenbiao
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Sander, Ingo
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Jantsch, Axel
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Transformational System Design based on a Formal Computational Model and Skeletons2000Inngår i: Proceedings of the Forum on Design Languages, 2000Konferansepaper (Fagfellevurdert)
  • 92.
    Zhu, Jun
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    SDF to Synchronous Cross Domain Analysis in ForSyDe Stream Processing Framework2006Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Stream processing has been a very active field in parallel programming for its suitability to expressthe concurrent architecture in embedded systems. Caused by its concurrent reasoning features,stream programming frameworks are built on some abstract models of computation (MoCs) tohandle the complexity and unpredictability. To allow us focus on the essential issues of time,communication and synchronisation of the parallel tasks, the support from a sound heterogeneousMoCs framework to stream application system is still in need. ForSyDe is our high levelexecutable design framework to express multi-computational-models, based on stream processingconcept. It is a heterogeneous diagram to describe intricate application behaviors, and offers crossdomain analysis features to support multi-domains integration and optimization. A case study inForSyDe framework shows that the communication structure of a stream application in SDFdomain could be migrated to the synchronous domain without any extra work on its computationfunctions. To integrate it with our work on a communication based NoC simulator, we believesome more interesting design exploration work could be done on the analysis of communicationand computation efforts, besides power issues.

  • 93.
    Zhu, Jun
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Buffer Minimization of Real-Time Streaming Applications Scheduling on Hybrid CPU/FPGA Architectures2009Inngår i: DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, 2009, s. 1506-1511Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We address the problem of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. The main contribution is a two-step approach to minimize the buffer requirement for streaming applications with throughput guarantees. A novel declarative way of constraint based scheduling for real-time hybrid SW/HW systems is proposed, while the application throughput is guaranteed by periodic phases in execution. We use a voice-band modem application to exemplify the scheduling capabilities of our method. The experimental results show the advantages of our techniques in both less buffer requirement and higher throughput guarantees compared to the traditional PAPS method.

  • 94.
    Zhu, Jun
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Constrained Global Scheduling of Streaming Applications on MPSoCs2010Inngår i: 2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, s. 223-228Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We present a global scheduling framework for synchronous data flow (SDF) streaming applications on MPSoCs, based on optimized computation and contention-free routing. The global scheduling of processors computing and communication transactions are formulated as constraint based problem, to avoid the scheduling overhead in TDMA-like heuristic schemes. A public domain constraint solver is exploited to solve the NP-complete scheduling efficiently, together with problem specific constraint modeling techniques. Experimental results show that the proposed framework can achieve a high predictable application throughput with minimized buffer cost. For instance, for applications in communication domain, higher throughput (up to 87%) has been observed with less buffer cost, compared to scenarios considering the heuristic scheduling overhead.

  • 95.
    Zhu, Jun
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Energy efficient streaming applications with guaranteed throughput on MPSoCs2008Inngår i: Proceedings of the 7th ACM International Conference on Embedded Software, EMSOFT 2008, 2008, s. 119-128Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The public domain simulators Sim-Panalyzer and Cacti are used to estimate the energy dissipations of the parameterized architectural components. As the main contributions, we schedule the streaming applications on a multi-clock synchronous modeling framework, guarantee the application timing properties by throughput analysis, and customize both processor voltage-frequency levels and memory sizes in the design space to optimize the application pipeline parallelism for energy efficiency. Two widely used heuristic algorithms (i.e., greedy and taboo search) are used during the design optimization process. Our experiments show an energy reduction of 21% without any loss in application throughput compared with an ad-hoc approach.

  • 96.
    Zhu, Jun
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    HetMoC: Heterogeneous Modeling in SystemC2010Inngår i: Proceedings of the Forum on Design Langauges (FDL), 2010, s. 117-122Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We propose a novel heterogeneous model-of-computation (HetMoC) framework in SystemC for embedded computing systems. As the main contribution, we formally define the computation and communication in multiple domains (continuous-time, discrete-event, synchronous/reactive, and untimed) as polymorphic processes and signals, and present domain interfaces to integrate different domains together for heterogeneous process networks. Especially, the continuous-time signals are defined with time continuum, which are distinguished from existing approaches. For implementation, a functional modeling style has been adopted to construct HetMoC. A solver with error estimation has been exploited in numerical approximation, and the time-varying functionalities in adaptive systems have been captured in HetMoC as well. In experiments, based on an adaptive transceiver system case study, HetMoC shows promising capabilities compared with a reference model in SystemC-AMS.

  • 97.
    Zhu, Jun
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Pareto Efficient Design for Reconfigurable Streaming Applications on CPU/FPGAs2010Inngår i: Proceedings of Design Automation and Test in Europe (DATE ’10), 2010, s. 1035-1040Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocates applications with optimized buffer requirement and software/hardware implementation cost. At the same time, application performance is guaranteed with sustainable throughput during run-time reconfigurations. As the main contribution, we formulate the constraint based application allocation, scheduling, and reconfiguration analysis, and propose a design Pareto-point calculation flow. A public domain solver - Gecode is used in solutions finding. The capability of our method has been exemplified by two cases studies on applications from media and communication domains.

  • 98.
    Zhu, Jun
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Performance Analysis of Reconfiguration in Adaptive Real-Time Streaming Applications2008Inngår i: PROCEEDINGS OF THE 2008 IEEE/ACM/IFIP WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA / [ed] Eles P; Pimentel AD, 2008, s. 53-58Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We propose a design optimization framework for adaptive real-time streaming applications. The main contribution is a hybrid approach for performance analysis combining formal analysis and simulation using a two-phase framework. We formulate the scheduling problem of adaptive streaming applications with ILP analysis, and use the simulation based on the synchronous model of computation to ensure throughput guarantees. We finally illustrate the capabilities of our methodology by experiments.

  • 99.
    Zhu, Jun
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications2012Inngår i: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 11, nr 1, s. 12-Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    We propose a performance analysis framework for adaptive real-time synchronous data flow streaming applications on runtime reconfigurable FPGAs. As the main contribution, we present a constraint based approach to capture both streaming application execution semantics and the varying design concerns during reconfigurations. With our event models constructed as cumulative functions on data streams, we exploit a novel compile-time analysis framework based on iterative timing phases. Finally, we implement our framework on a public domain constraint solver, and illustrate its capabilities in the analysis of design trade-offs due to reconfigurations with experiments.

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