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  • 51.
    Morici, Andrea
    et al.
    Universita Politecnica delle Marche.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Turchetti, C.
    Universita Politecnica delle Marche.
    A 3.6 mW 90 nm CMOS 2.4 GHz Receiver Front-End Design for IEEE 802.15.4 WSNs2009In: ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, New York: IEEE , 2009, p. 77-80Conference paper (Refereed)
    Abstract [en]

    In this paper a low-power design of an integrated RF receiver for Wireless Sensor Networks (WSNs) in 90nm CMOS technology is proposed. The receiver is IEEE 802.15.4 physical specifications compliant. It is designed to operate in ISM band at 2.45 GHz center frequency. Target devices for this kind of transceiver are low-cost battery powered smart embedded devices and sensors. The receiver is designed to reduce the count of external components in the final system, integrating on silicon the balun for single-ended to differential conversion. The receiver is composed of an inductorless Low Noise Amplifier (LNA), a buffer stage, I and Q passive mixers and Variable Gain Amplifiers (VGAs) that also act as second order filters. A novel integration of balun into the LNA is described. The system is designed to have direct conversion from RF to 6 MHz low-IF. Voltage supply is 1.2 V with a current consumption of 3 mA including necessary biasing networks, and the total power consumption is 3.6 mW. The complete voltage gain is more than 41.5 dB with a Noise Figure (NF) of 12.6 dB. The receiver layout exhibits an area of only 0.12 mm(2). Simulations are provided, including mismatch scenarios.

  • 52. Park, Seok-Bae
    et al.
    Ismail, Mohammed
    DC offsets in direct conversion multistandard wireless receivers: Modeling and cancellation2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 2, p. 123-130Article in journal (Refereed)
    Abstract [en]

    To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this paper, among many problems in direct conversion receivers, the DC offset problem is studied. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to better understand how the static (or time-invariant) and dynamic (or time-varying) DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed and verified through simulations.

  • 53. Park, Seok-Bae
    et al.
    Wilson, James E.
    Ismail, Mohammed
    Peak detectors for multistandard wireless receivers2006In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 22, no 6, p. 6-9Article in journal (Refereed)
  • 54.
    Ramesh, Chithrupa
    et al.
    KTH, School of Electrical Engineering (EES), Automatic Control.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT).
    Skoglund, Mikael
    KTH, School of Electrical Engineering (EES), Communication Theory.
    System co-optimization in wireless receiver design with TrACS2008In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 57, no 1-2, p. 117-127Article in journal (Refereed)
    Abstract [en]

    System co-optimization of the analog receiver front end circuit and the digital baseband processing could enable receiver designs with lower power budgets, as the signal processing in the digital receiver is asymmetric across circuit topologies. This paper presents a simulation tool that could assist with such co-optimized designs. TrACS (Transceiver Architecture and Channel Simulator) is an RF/DSP co-simulator, capable of providing an application-specific system-level perspective to receiver design. The simulator is especially relevant in the context of energy-constrained wireless sensor node design, where the simulator's system perspective determines the compatibility of circuit topologies, modulation techniques and synchronization methods for various wireless scenarios. A few case studies are presented, which illustrate co-optimization of a ZigBEE receiver using TrACS.

  • 55.
    Ramesh, Chithrupa
    et al.
    KTH, School of Electrical Engineering (EES), Communication Theory.
    Rusu, Ana
    KTH, School of Electrical Engineering (EES), Communication Theory.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Skoglund, Mikael
    KTH, School of Electrical Engineering (EES), Communication Theory.
    TrACS: Transceiver Architecture and Wireless Channel Simulator2007In: SBCCI2007: 20TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, NEW YORK: ASSOC COMPUTING MACHINERY , 2007, p. 128-132Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of a system-level simulator for radio receivers, including receiver circuits, in Matlab. The system level outlook offers a better characterization of circuit design, as the signal processing in the digital receiver is asymmetric across topologies. Also, circuit models in the simulator make it more precise and realistic compared to baseband models, which assume a single-step error-free down conversion. This interpretation is especially relevant in the design of energy-constrained wireless sensor network solutions. The simulator results for binary FSK in AWGN confirm the importance of system level simulation.

  • 56. Rao, K. R.
    et al.
    Wilson, J.
    Ismail, Mohammed
    A CMOS RF front-end for a multistandard WLAN receiver2005In: IEEE Microwave and Wireless Components Letters, ISSN 1531-1309, E-ISSN 1558-1764, Vol. 15, no 5, p. 321-323Article in journal (Refereed)
    Abstract [en]

    This letter describes the design and performance of a dual band tri-mode receiver front-end compliant with the IEEE 802.11a, b, and g standards. The receiver front-end was built in a 0.18-μ m CMOS process and achieves a noise figure of 4.7 dB/5.1 dB for the 2.4-GHz/5-GHz bands, respectively. The receiver front-end provides a dual gain mode of 5 dB/30 dB with an IIP3 of -1 dBm for the low gain mode. The front-end draws 25 mA/27 mA from a 1.8-V supply for the 2.4-GHz/5-GHz bands, respectively.

  • 57. Ravindran, A.
    et al.
    Ramarao, K.
    Vidal, E.
    Ismail, Mohammed
    Compact low voltage four quadrant CMOS current multiplier2001In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 37, no 24, p. 1428-1429Article in journal (Refereed)
    Abstract [en]

    A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 mum technology shows a linearity error lower than 0.9% for signal swings up to +/- 50 muA. The Circuit operates at a supply of +/- 1.5V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz.

  • 58. Ravindran, A.
    et al.
    Vidal, E.
    Yoo, S. J.
    Ramarao, K.
    Ismail, Mohammed
    A differential CMOS current-mode variable gain amplifier with digital dB-linear gain control2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 38, no 03-feb, p. 161-174Article in journal (Refereed)
    Abstract [en]

    A novel CMOS variable gain amplifier operating on current signals with a dB-linear gain control is presented. The gain control is achieved by multiplying a digitally synthesized exponentially varying control current signal by a differential input signal in the current domain. A current amplifier at the output sets the gain to the desired level. Current-mode operation allows for a reduced supply voltage by minimizing the voltage swing at the low impedance nodes of the circuit. Multiple circuit realizations for various blocks are presented allowing for designs meeting different constraints. Experimental realization of the variable gain amplifier shows the validity of the presented approach.

  • 59.
    Rodriguez Duenas, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Duo, Xinzhong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Yamac, Sezi
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    CMOS UWB IR Non-Coherent Receiver for RF-ID Applications2006In: Circuits and Systems, 2006 IEEE North-East Workshop on, 2006, p. 213-216Conference paper (Refereed)
    Abstract [en]

    Ultra Wide Band Impulse-Radio (UWB-IR) bringsthe opportunity of increased bitrates in RFID systems. This paperpresents the implementation of a CMOS non-coherent UWBimpulse receiver targeted for readers in RFID applications. Thereceiver consists of an RF-front-end and an On-Off keying (OOK)10Mbps demodulator, which is implemented using a 0.18umCMOS process. The receiver works for 3.1GHz-5GHz, has asensitivity of -70dBm, and consumes 31mW from a 1.8V supply.

  • 60.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Atallah, Jad G.
    Notre Dame University, Lebanon.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 2.3-GHz to 5.8-GHz CMOS receiver front-end for WiMAX/WLAN2010In: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings, 2010, p. 1068-1071Conference paper (Refereed)
    Abstract [en]

    This paper presents a wideband, direct-conversion radio receiver front-end that targets all WiMAX/WLAN bands from 2.3-GHz to 5.8-GHz. The receiver front-end is fabricated in 0.18-μm CMOS and achieves a gain of 25 dB, noise figure of 6 dB, and IIP3 of -6 dBm while dissipating 28 mW from a 1.8-V power supply. This performance is achieved while using only two integrated inductors.

  • 61.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    ARCHER: an automated RF-IC Rx front-end circuit design tool2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 58, no 3, p. 255-270Article in journal (Refereed)
    Abstract [en]

    This paper presents a tool capable of automatically compiling the circuit of a direct-conversion receiver at the schematics level based on system specifications that include the frequency of operation, gain, noise figure, IIP2 and IIP3 linearity. The front-end of a direct-conversion receiver is built using inductive source degeneration (LSD) LNA and double-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that automatically size the transistors, passive components, and find the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout. Case studies involving WiMAX, UMTS, GSM, Bluetooth and WLAN are presented to reveal the capabilities of the tool in reducing the design time.

  • 62.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    ARCHER: An automated RF-IC Rx front-end circuit design tool2007In: ISSCS 2007: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, NEW YORK: IEEE , 2007, p. 129-132Conference paper (Refereed)
    Abstract [en]

    This paper presents a tool capable of compiling automatically the schematic circuit design of a direct conversion receiver based on system specifications including frequency of operation, gain, noise figured and 123 linearity. The rx front-end of a direct conversion receiver is built using inductive source degeneration (LSD) LNA and single-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that size automatically the transistors, passive components, and finds the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout.

  • 63.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    4G CMOS Nanometer Receivers for Mobile Systems: Challenges and Solutions2009In: ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS,, NEW YORK: IEEE , 2009, p. 73-76Conference paper (Refereed)
    Abstract [en]

    This paper presents the design challenges and solutions for 4G nanometer radio receivers for mobile devices. The specifications for the ZERO-IF/LOW-IF 4G receiver architecture are derived. Limitations due to the use of low-voltage nanometer technologies are described and novel circuit techniques, such as wideband noise reduction, inductoreless peaking, passive mixing, and low flicker noise amplification are proposed. Finally, a 1.2-V 90nm CMOS receiver front-end for the proposed WiMAX/LTE receiver is designed employing novel circuit techniques. The front-end covers 700 MHz - 6 GHz, providing a total gain of 34 dB, noise figure of 4 dB, flicker noise corner of 10 kHz, and a third order intercept point of -10dBm/0dBm, while consuming a total power of 10.2 mW.

  • 64.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    WiMAX/LTE Receiver Front-End in 90nm CMOS2009In: ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, NEW YORK: IEEE , 2009, p. 1036-1039Conference paper (Refereed)
    Abstract [en]

    RFIC design using low-voltage nanometer CMOS technologies offers both advantages and challenges. This paper describes the limitations of using these technologies in receiver front-end design and proposes circuit solutions. Several techniques such as wideband noise reduction, inductoreless peaking, passive mixing, and low flicker noise amplification are reviewed and employed. A receiver front-end that covers 700MHz-6Ghz and supports the WiMAX/LTE standards is designed based on these circuit solutions. The front-end is designed using 1.2V 90nm CMOS and consumes a total power of 10.2mW. The total gain is 32dB, noise figure is 4dB, flicker noise corner is 10kHz, and third order intercept point is -10dBm/0dBm.

  • 65.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zheng, LiRong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A Novel BiST and Calibration Technique for CMOS Down-Converters2008In: Circuits and Systems for Communications, 2008. ICCSC 2008. 4th IEEE International Conference on, 2008, p. 828-832Conference paper (Refereed)
    Abstract [en]

    This paper presents a new digital calibration methodology that allows CMOS Gilbert cell down-converters to meet their block specifications under large process, temperature and power supply variations. The calibration method consists of a novel built-in self test for direct conversion receivers that is able to measure the gain, and the second and third order intermodulation products of the mixer. A random optimizer algorithm based on a least square error function provides digital control of the biasing circuit and the loads of the mixer. The gain and IIP3 are calibrated by regulating the current of the input differential pair and by switching the loads. IIP2 calibration is achieved by using a novel technique that consists of offset voltages cancellation in the switching pairs. The technique is validated by calibrating a 0.18um CMOS mixer in several corner conditions.

  • 66.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    CMOS RF mixer with digitally enhanced IIP22008In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 44, no 2, p. 121-123Article in journal (Refereed)
    Abstract [en]

    A new method to enhance the IIP2 of a double-balanced Gilbert cell mixer through digital calibration is presented. The IIP2 calibration method consists of offset voltage cancellation in the switching pairs. The effectiveness of the method has been proven by calibrating a 0.18 mu m CMOS mixer at several combinations of worst-case mismatch conditions and corners. It has been found that the calibrated mixer can achieve its targeted IIP2 specification even at large process, temperature, and power supply variations.

  • 67.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Digital calibration of gain and linearity in a CMOS RF mixer2008In: Proceedings - IEEE International Symposium on Circuits and Systems, 2008, p. 1288-1291Conference paper (Refereed)
    Abstract [en]

    This paper presents a new digital calibration technique that allows CMOS Gilbert cell down-conversion mixers to meet their block specifications under large process, temperature and power supply variations. The gain and IIP3 are calibrated by regulating the current of the input differential pair and by switching the loads. IIP2 calibration is achieved by using a novel technique that consists of offset voltages cancellation in the switching pairs. The technique is tested by calibrating a 0.18um CMOS mixer in several corner conditions. It is found that by using this calibration technique, the Gilbert cell mixer can achieve yields comparable to digital circuits, hence making it amenable to AMS SoC integration.

  • 68.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    An IIP2 Digital Calibration Technique for Passive CMOS Down-Converters2010In: IEEE INT SYMP CIRC SYST PROC, New York: IEEE , 2010, p. 825-828Conference paper (Refereed)
    Abstract [en]

    The IIP2 requirement in fully integrated direct-conversion receivers using FDD duplexing is prohibitively high and demands the use of an external filter in order to attenuate the leakage from the transmitter. This paper presents a digital calibration technique for passive CMOS down-converters that allows a direct conversion receiver achieve the requirements without external filtering. A Least-Mean-Square optimization algorithm is used in order to reduce the low-frequency second-order intermodulation product. The algorithm controls the digital calibration structures at the biasing of the passive mixer and adapts them until the second order intermodulation drops below the noise level. The method is tested by calibrating a 1.2-V 65nm CMOS passive mixer targeting UMTS/LTE applications at several corner conditions including worst case mismatches in the switching pairs.

  • 69.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Analysis of wideband CMOS low noise amplifiers using current-reuse configuration2006In: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, p. 62-65Conference paper (Refereed)
    Abstract [en]

    This paper introduces a design methodology for a current-reuse wideband CMOS low noise amplifier (LNA). A theoretic analysis of source degeneration current-reuse CMOS LNAs is presented. The advantages and limitations of wideband amplification using this kind of LNA are analyzed. The theoretical results are validated through comparison to simulations using BSIM3v3 models of a 0.18um CMOS process. A design methodology is described through an example LNA that targets the band 2GRz-6GHz.

  • 70.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    CMOS Wideband LNA for WiMAX/WLAN2006Conference paper (Other academic)
  • 71.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A behavioral-based multi-agent optimization algorithm for system level radio design2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 61, no 1, p. 35-46Article in journal (Refereed)
    Abstract [en]

    This paper introduces a multi-agent behavioral-based optimization algorithm for system level radio design. Making multi-standard wireless communication receivers that meet their specs while keeping the requirements of the individual blocks as relaxed as possible is the goal of this algorithm. In order to achieve this goal a "divide and conquer" approach is proposed. Different agents focus on different objectives that are pursued in parallel. Agents adopt different behaviors depending on the status of the environment and their interaction with other agents. Agents are cooperative by default as they try to meet their spec without making changes that affect other agents. However, more aggressive behaviors that lead to global changes can be adopted when needed. The interaction between these simple entities yields an emergent behavior able to deal smoothly with the complexity of the problem at hand.

  • 72.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A frequency plan evaluation tool for multi-standard wireless transceivers2006In: Prime 2006: 2nd Conference on PH.D. Research in MicroElectronic and Electronics, 2006, p. 473-476Conference paper (Refereed)
    Abstract [en]

    This paper introduces a frequency plan evaluation too] for multi-hand, multi-standard wireless transceivers. The implemented algorithm allows RF engineers to systematically analyze the effects of the intermodulation products as well as the harmonic components associated with the input signals, the local oscillator and interfering signals. The effect of the out of-band blockers is also evaluated. This provides very valuable information that helps finding the best intermediate frequency and filter bandwidths to the designer. This evaluation tool is part of a suite of tools called TACT, the purpose of which is to explore the design space of multi-standard radio transceivers. Simulation results on a multi-band WCDMA system verify the validity of the implemented frequency planning scheme.

  • 73.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Automated design of a WCDMA/WLAN multi-standard receiver2006In: ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems: Nice: 10 December 2006 through 13 December 2006, 2006, p. 1320-1323Conference paper (Refereed)
    Abstract [en]

    In this paper we show how TACT, a recently reported [1] radio system design and optimization tool, can be used to optimize the design of a dual mode WCDMA/WLAN receiver. An overview of the underlying frequency planning and receiver budget analysis routines is discussed first. In a case study, a zero-IF WLAN/WCDMA radio receiver is then designed and optimized using the tool. TACT yields optimized design specs for each block in the chain as well as a summary of the system performance obtained. The obtained performance is shown to meet or exceed the requirements of the WCDMA/WLAN standards. As such, the case study validates the benefits of the proposed tool.

  • 74.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Automated receiver design and optimization for 4G wireless communication systems2006In: BMAS 2006: Proceedings of the 2006 IEEE International Behavioral Modeling and Simulation Workshop, 2006, p. 132-137Conference paper (Refereed)
    Abstract [en]

    This paper presents the design methodology and underlying algorithms of a tool developed for automated receiver design and optimization for fourth generation (4G) Wireless Communication Systems. An algorithm to systematically design and optimize the receiver budget for the multi-standard case is introduced. The goal of this algorithm is to find a multistandard receiver budget that meets or exceeds the specs of the addressed wireless standards while keeping the requirements of each of the receiver blocks as relaxed as possible. This tool offers RF engineers a deep insight into the receiver behavior at a very early stage of the design flow. It models the impact of some circuit non-idealities using a high level of abstraction. This reduces the number of design iterations and, thus, the time-to-market of the solution. The reuse of already available intellectual property (IP) blocks is also considered in the tool. This can result in a significant cost reduction of the receiver implementation.

  • 75.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    EDA for RF and analog front-ends in the 4G era: Challenges and solutions2007In: European Conference on Circuit Theory and Design 2007, ECCTD 2007, 2007, p. 24-27Conference paper (Refereed)
    Abstract [en]

    Convergence into 4G wireless communication systems pushes the design of radio receivers beyond limits unconceivable only few years ago. The complexity of RF systems has increased enormously as new communication standards have appeared in the wireless scenario. The convergence trends, enabled by the advances in fabrication technology, have driven the Software Defined Radio (SDR) more and more into the RF and analog front-end. There is a clear need for design automation and advanced simulation techniques at the different levels that go from the system idea to chip fabrication. Reducing the number of design iterations between these levels is key in meeting the increasingly tight time-to-market constraints. As of today, there is not a single tool that covers the complete design flow. Instead, there is an intricate puzzle of design and simulation tools that focus on the various steps that go from system to silicon. The amount of RF and analog EDA tools available is certainly scarce in comparison with their digital counterparts. Most of the design work still depends on the radio engineer, making the process less than optimal. This paper describes some of the challenges faced by today's radio designers and discusses some of the solutions provided by the EDA community.

  • 76.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Receiver design for integrated multi-standard wireless radios2006In: Radio Design in Nanometer Technologies / [ed] Ismail, Mohammed; Rodríguez De Llera González, Delia, Dordrecht: Springer , 2006, p. 145-171Chapter in book (Other academic)
  • 77.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    School of Information and Communication Technology, Royal Institute of Technology, Ohio State University.
    Tackling 4G challenges with "TACT": Design and optimization of 4G radio receivers with a transceiver architecture comparison tool (TACT)2006In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 22, no 6, p. 16-23Article in journal (Refereed)
    Abstract [en]

    Today, engineers are faced with the challenge of programming multistandard capabilities. Achieving digital programmability and flexibility in the analog/radio frequency (RF) components of the system is vital in order to achieve this goal. This is where electronic design automation (EDA) tools are needed. The tools facilitate the design of multiband/multimode receivers at different levels. The multistandard RF Transceiver Architecture Comparison Tool (TACT) is a tool that automates the process of design-space exploration for multistandard transceivers like 4G wireless receivers. TACT proposes an interference-oriented approach when evaluating the performance of each possible intermediate frequency to find the most suitable frequency plan. This evaluation takes into account both signals belonging to the standards as well as out-of-band interferers. TACT's objective is finding a multistandard receiver budget that meets or exceeds the specifications of the addressed wireless standards while keeping the requirements of each of the receiver blocks as relaxed as possible. EDA tools will play an important role in the design and verification of wireless systems in order to achieve the software radio paradigm using 4G radio receivers.

  • 78.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    TACT: A multi-standard RF transceiver architecture comparison tool2005In: Circuits and Systems, 2005. 48th Midwest Symposium on, IEEE conference proceedings, 2005, p. 659-662Conference paper (Refereed)
    Abstract [en]

    One of the main challenges posed by 4G wireless communication systems is achieving flexible, programmable multi-standard radio transceivers with maximum hardware share amongst different standards at a minimum power consumption. Evaluating the feasibility and performance of different multistandard/multi-band radio solutions at an early stage, i.e. system level, is key for succeeding in surmounting this challenge. This entails formulation of the transceiver budget for several RF architectures with different degrees of hardware reuse. This task is complicated by the fact that transceiver blocks can have different implementations that lead to different performances. The tools that are available for use at present have only budget analysis capabilities or address only one standard and/or transceiver architecture at a time. We believe that a new approach to this problem is necessary and propose a novel methodology for evaluating the performance of different multi-standard solutions. This paper introduces TACT, our multi-standard RF Transceiver Architecture Comparison Tool. It will help answering many of the challenges faced by designers when realizing a transceiver budget for multi-standard/multi-band radio transceivers.

  • 79.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Xu, Wangren
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    TACT as a learning tool for radio design2007In: MSE 2007: 2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World, 2007, p. 71-72Conference paper (Refereed)
    Abstract [en]

    TACT is an EDA tool that can be very valuable in an educational context since it can help students in electronics and communications acquiring skills that will be fundamental for their careers. TACT is suite of tools the purpose of which is to explore the design space of multi-standard radio transceivers. The use of this tool can ease and speed up the learning process related to the system level design of chipsets suitable for communication applications. The outputs from TACT can easily be combined with available commercial tools in order to provide a complete design flow from system to silicon. This paper highlights the main features that make of TACT a very useful tool in education.

  • 80.
    Rong, Liang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Gustafsson, E. Martin I.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Systematic design of a flash ADC for UWB applications2007In: 8th International Symposium on Quality Electronic Design, ISQED 2007: San Jose, CA; 26 March 2007 through 28 March 2007, 2007, p. 108-112Conference paper (Refereed)
    Abstract [en]

    This paper presents the systematic design of a 5-bit, 1.2 GSPS interpolative flash ADC for multiband OFDM UWB applications. The proposed ADC architecture employs the proven capacitive interpolation, which greatly reduce the power consumption, by eliminating the need of a power hungry resistive ladder The flash ADC has been implemented in a 0.18 um CMOS process. Circuit level simulations show that the proposed architecture can achieve an SNDR of 25.3 dB, and an SFDR of 29.3 dB, with an input signal frequency of 330 MHz, at a sampling rate of 1.2 GSPS. The ADC core dissipates 130 mW from a 1.8 V supply.

  • 81.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Borodenkov, A.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A triple-mode sigma-delta modulator for multi-standard wireless radio receivers2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 47, no 2, p. 113-124Article in journal (Refereed)
    Abstract [en]

    A 1.8 V sigma-delta modulator with a 4 bit quantizer has been designed for GSM/WCDMA/WLAN receivers in a 0.18 um CMOS process. The modulator makes use of low-distortion sigma-delta modulator architecture and Pseudo-Data-Weighted-Averaging technique to attain high linearity over a wide bandwidth. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. In GSM mode, the modulator achieves 96/104 dB peak SNR/SFDR over 100 kHz bandwidth and dissipates 18 mW at a sampling frequency of 32 MHz. The modulator achieves 92/68 dB peak SFDR and 77/54 dB peak SNR over a 2 MHz/10 MHz bandwidth and dissipates 23/39 mW at a sampling frequency of 64 MHz/160 MHz in WCDMA/WLAN.

  • 82.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Dong, Boxian
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Putting the flex in flexible mobile wireless radios - A wideband continuous-time bandpass sigma-delta ADC for software radios2006In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, ISSN 8755-3996, Vol. 22, no 6, p. 24-30Article in journal (Refereed)
    Abstract [en]

    This article has provided a brief overview of the SigmaDelta ADC conversion technologies for SDRs. The wireless receiver challenges were identified, the ADC design considerations and SigmaDelta solutions were discussed, and a low-distortion CT BP SigmaDelta modulator architecture was presented. The article has shown that the proposed CT BP SigmaDelta modulator is suitable for implementing high-IF ADC, making possible the software radio in handhelds. The major challenges in implementing such a high-IF ADC are the power dissipation and the degree of configurability, programmability, and adaptability that can be achieved by applying digital tuning and adaptive calibration.

  • 83.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Design challenges of wireless mobile radios2007In: ISSCS 2007: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, NEW YORK: IEEE , 2007, p. 133-136Conference paper (Refereed)
    Abstract [en]

    This paper discusses the challenges in designing modern wireless systems with focus on wireless mobile devices. It reviews the radio architectures and the design challenges imposed by the low-power specifications, small size. and low cost in mobile terminals. Finally, the reconfigurable analog-to-digital conversion architectures that could support the multi-standard radio requirements in mobile devices am discussed in the perspective of a low-power CMOS design.

  • 84.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Gustafsson, E. Martin I.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodríguez de Llera González, Delia
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Flexible ADCs for wireless mobile radios2007In: 18th European Conference on Circuit Theory Design, ECCTD 2007: Univ Sevilla, Seville, SPAIN, AUG 26-30, 2007, 2007, p. 172-175Conference paper (Refereed)
    Abstract [en]

    The evolution of wireless mobile devices calls for "all-in-one-device", which support a large number of wireless standards and allows wireless connectivity and roaming. This creates the need for adaptive circuits that are able to reconfigure themselves to trade-off power dissipation for performance, depending on the wireless standard to be supported and the required Quality of Service. Therefore, the key features of such mobile devices are flexibility and adaptability. This paper presents the ADCs suitable for mobile radios, keeping focus on flexible architectures. Finally, a programmable ADCs array, which can digitize signal bands from cellular to UWB is presented.

  • 85.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Computer Science and Communication (CSC), Numerical Analysis and Computer Science, NADA.
    "Analog-to-Digital Conversion Technologies for Software Defined Radios"2006In: Radio design in nanometer technologies / [ed] Mohammed Ismail and Delia Rodriguez, Springer: Springer, 2006, 1, p. 101-121Chapter in book (Refereed)
  • 86.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Low-distortion bandpass Sigma-Delta modulator for wireless radio receivers2005In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 41, no 19, p. 1044-1046Article in journal (Refereed)
    Abstract [en]

    A low-distortion bandpass sigma-delta modulator is proposed. It was found that the key to improving linearity is to add a feedforward signal path in a double-delay resonator bandpass structure. The proposed technique improves the tonal behaviour even at low oversampling ratio and can be applied for any order of modulator. Based on the proposed architecture, a fourth-order single-bit sigma-delta modulator can achieve a dynamic range of 84 dB and a spurious free dynamic range of 98 dB at 10.71 MHz with a signal bandwidth of 200 kHz, making it ideal for a narrowband IF-sampled wireless receiver designed for compliance with GSM/GPRS standards.

  • 87.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Sigma-delta solutions for future wireless handhelds2006In: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, p. 58-61Conference paper (Refereed)
    Abstract [en]

    This paper addresses the different issues in the design of ADCs for future wireless handhelds. It reviews the constraints imposed on the receiver design by the low-power specifications in handhelds. The sigma-delta ADC architectures that can potentially be used for implementing future wireless handhelds are discussed in the perspective of a CMOS implementation. Finally, a 4(th) order 4bit continuous-time bandpass sigma-delta modulator capable of digitizing a WiMAX (20MHz) signal band centered at an IF of 75 MHz is presented. The simulation results shown that the proposed sigma-delta modulator can provide a SNDR of 50.1 dB and a DR of 56 dB at a sampling frequency of 500 MHz.

  • 88.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A modified cascaded sigma-delta modulator with improved linearity2005In: IEEE Computer Society Annual Symposium on VLSI, Proceedings: NEW FRONTIERS IN VLSI DESIGN / [ed] Smailagic, A; Ranganathan, N, 2005, p. 77-82Conference paper (Refereed)
    Abstract [en]

    This paper presents a sigma-delta modulator architecture with improved linearity over a frequency band from DC to 10 MHz. The proposed modulator architecture employs the 2(nd) order 4-bit sigma-delta modulator with feedforward signal path in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). A Data-Weighted-Averaging technique eliminates tones generated by the multibit digital-to-analog converter (DAC) nonlinearity improving the spurious free dynamic range (SFDR) and intermodulation distortion performance. The modulator is designed in 0.18um CMOS process and operates at 1.8V supply voltage. It achieves 62.86 dB signal-to-noise plus distortion ratio (SNDR) in the 10MHz signal bandwidth, a SFDR of 82.2dB and IMD3 of -77.5dB.

  • 89.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Rodríguez de Llera González, Delia
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    The Ohio State University, Columbus.
    Reconfigurable ADCs enable smart radios for 4G wireless connectivity2006In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 22, no 3, p. 6-11Article in journal (Refereed)
    Abstract [en]

    A reconfigurable analog-to-digital converter (ADC) based on a 2-2 modified cascaded sigma-delta (Σ-Δ) modulator designed for a GSM/WCDMA/WLAN/WiMax zero-IF receiver is now available. Employing the second-order feedforward Σ-Δ modulator in a 2-2 modified cascaded configuration, a high linearity over 100 kHz/2 MHz/10 MHz signal bandwidth can be achieved. Application of the P-DWA technique in the first feedback 4-b DAC eliminates the spurious tones associated with the multibit DAC nonlinearity in the WLAN/WiMAX modes.

  • 90.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodríguez de Llera González, Delia
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    The design of a low-distortion sigma-delta ADC for WLAN standards2005In: ISSCS 2005: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, Proceedings, 2005, p. 151-154Conference paper (Refereed)
    Abstract [en]

    A low-distortion sigma-delta analog-to-digital converter (ADC) for Wireless Local Area Network (WLAN) standards is presented. The proposed sigma-delta modulator architecture employs the 4-bit 2(nd) order sigma-delta modulator with swing suppression in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). The modulator is designed in 0.18um CMOS process and operates at 1.8V supply voltage. It achieves a dynamic range of 69.1dB and a spurious free dynamic range (SFDR) of 82.2dB for a 10MHz signal bandwidth, and an oversampling ratio of 8.

  • 91.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Roslind Jose, Babita
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Linearity enhancement in a configurable sigma-delta modulator2005In: IEEE-NEWCAS Conference, 2005. The 3rd International / [ed] IEEE, IEEE conference proceedings, 2005, p. 59-62Conference paper (Refereed)
    Abstract [en]

    A highly linear sigma-delta modulator for dual-standard receivers is presented. The modulator makes use of low-distortion sigma-delta modulator architecture to attain high linearity over a wide bandwidth. The dual-band modulator employs a 2nd order single-bit sigma-delta modulator with feedforward path for GSM mode and a 4th order modified cascaded modulator with single-bit in the first stage and 4-bit in the second for WCDMA mode. The modulator is designed in TSMC 0.18μm CMOS technology and operates at 1.8 supply voltage. It achieves in GSM/WCDMA mode a peak SNDR of 83/75dB, a 96/84dB SFDR and an IMD3 of -93/-82dB for an OSR of 160/16.

  • 92. Shi, C. L.
    et al.
    Wu, Y.
    Lin, C. H.
    Ismail, Mohammed
    Design and power optimization of high-speed pipeline ADC for wideband CDMA applications2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 26, no 3, p. 229-238Article in journal (Refereed)
    Abstract [en]

    This paper presents a 7-bit 64 MS/s pipeline A/D converter suitable for wideband CDMA applications. Targeting at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed. Switched-Opamp technique is used to further reduce power consumption. This ADC is implemented in 0.5 mum standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s.

  • 93.
    Signell, Svante
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Rodríguez de Llera González, Delia
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radio design for future wireless SOC platforms: An overview2004In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, NEW YORK: IEEE , 2004, p. 277-280Conference paper (Refereed)
    Abstract [en]

    As we move to third and fourth generation wireless providing higher data rates at shorter distances in "hotspots", future handhelds will be able to access different wireless infrastructures, e.g. UMTS and WLAN, from the same wireless device, be it a mobile phone, a PDA or a notebook. As a result SoC platforms for convergent 4G must address the challenge of increased complexity particularly as it pertains to the radio transceiver part of a chipset where power consumption and cost are the main differentiators. This paper presents an overview of the challenges faced in designing highly integrated radios in the context of 4G wireless communications. Aside from important issues such as multi antenna design and standards coexistence in the same SoC platform, we focus our overview on a few main thrusts that will be discussed in some details related to designing digitally programmable and con gurable ADCs, PLLs, analog baseband chains and RF front ends as well as techniques for packaging multi band radios and for achieving " rst pass" silicon success.

  • 94.
    Sleiman, Sleiman Bou
    et al.
    Ohio State Univ, Analog VLSI Lab.
    Atallah, Jad G.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Optimal Sigma Delta Modulator Architectures for Fractional-N Frequency Synthesis2010In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 18, no 2, p. 194-200Article in journal (Refereed)
    Abstract [en]

    This paper presents a comparative study of Sigma Delta modulators for use in fractional-N phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.

  • 95.
    Sleiman, Sleiman Bou
    et al.
    Ohio State Univ, Analog VLSI Lab.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Wide-Division-Range High-Speed Fully Programmable Frequency Divider2008In: 2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, NEW YORK: IEEE , 2008, p. 17-20Conference paper (Refereed)
    Abstract [en]

    This paper presents the design and implementation of an all-programmable frequency divider with an ultra-wide division range for use in Phase-Locked Loops. The proposed divider uses a fully modular architecture and dynamic logic - implemented in TSMC 0.18 mu m - and can divide input frequencies up to 7.55GHz by any ratio between 8 and 255 while consuming 11mW from a 1.8V power supply. The divider compares very favorably to other implementations reported in literature in terms of division range and frequency of operation.

  • 96.
    Srinivasar, Sandeep Kowlgi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ultra-low power 2.4 GHz CMOS receiver front-end for sensor nodes2007In: 2007 European Conference On Circuit Theory And Design: Vols 1-3, 2007, p. 595-598Conference paper (Refereed)
    Abstract [en]

    This paper presents a fully integrated receiver front-end for a 2.4GHz RF transceiver. A system level design for the radio front end for which these components are designed is also presented. The proposed receiver front end (Low-Noise Amplifier, Single-to-Differential Converter and Mixer) is based on a direct conversion architecture designed in 0.18 mu m CMOS technology. It takes advantage of on-chip single to differential signal conversion to avoid the use of cost intensive off-chip balun and external passives. The post layout simulations of front end show that the RF front-end achieves a voltage gain of 8dB without the baseband amplifier, a noise figure of 8.9 dB and IIP3 better than -15 dBm. The flicker noise corner is less than 10 KHz, with a nominal DC offset. It consumes less than 1.6 mA from a 1.8V supply.

  • 97. Tang, Y.
    et al.
    Ismail, Mohammed
    Bibyk, S.
    Adaptive Miller capacitor multiplier for compact on-chip PLL filter2003In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 39, no 1, p. 43-45Article in journal (Refereed)
    Abstract [en]

    An adaptive Miller capacitor multiplier is proposed to reduce on-chip phase-locked loop (PLL) capacitor area and improve lock speed. Fabricated in 0.5 mum standard CMOS, an effective capacitance of 576 pF is achieved with a polycapacitor of only 192 pF (62% die area saving) and 0.43 mA current consumption. The lock time is reduced by 36% due to the adaptive loop bandwidth control during PLL settling.

  • 98. Tang, Y. W.
    et al.
    Aktas, A.
    Ismail, Mohammed
    Bibyk, S.
    A high-speed low-power divide-by-15/16 dual modulus prescaler in 0.6 mu m CMOS2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 28, no 2, p. 195-200Article in journal (Refereed)
    Abstract [en]

    A new high-speed low-power dual modulus prescaler (DMP) topology is proposed. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4/5 divider, it has a higher speed by eliminating the NAND-gate introduced critical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFF's) required. Based on this topology, a divide-by-15/16 DMP is implemented in the 0.6 mum standard CMOS process. Simulation result shows that a maximum operating frequency of 2.15 GHz is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circuit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltage with 570 MHz input frequency.

  • 99. Tang, Y. W.
    et al.
    Ismail, Mohammed
    A methodology for fast SPICE simulation of frequency synthesizers2000In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 16, no 4, p. 10-15Article in journal (Refereed)
  • 100.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Manolopoulos, Vasileios
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hybrid Vehicle Positioning and Tracking Using Mobile Phones2011In: 2011 11th International Conference on ITS Telecommunications, ITST 2011, 2011, p. 315-320Conference paper (Refereed)
    Abstract [en]

    Due to the pervasive deployments of mobile communication technologies, vehicle positioning and tracking by locating the driver's mobile phones has become feasible. However, no single positioning method can provide decent tradeoff between accuracy and coverage. To address this issue, we propose a Kalman filter-based hybrid method which can track the mobile phones traveling on-board vehicles. The proposed method combines coordinates collected by assisted global positioning system (A-GPS) mobile phones and location estimates calculated from observed time difference of arrival (OTDOA) measurements. Numerical results demonstrate the effectiveness of this hybrid scheme in a simulated vehicular scenario.

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