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  • 501. Sanden, Martin
    et al.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Östling, Mikel
    Marinov, O.
    Deen, M. Jamal
    Up-Conversion of Device 1/f Noise to Phase Noise in Voltage Controlled Oscillators2001In: Proc 16th International Conference on Noise in Physical Systems and1/f Fluctuations, ICNF, 2001, p. 449-502Conference paper (Refereed)
  • 502.
    Sander, Ingo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Attarzadeh Niaki, Seyed Hosein
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Towards a Formal Software Synthesis Methodology for Embedded Multiprocessor Systems2011In: Proceedings of First International Software Technology Exchange Workshop 2011, 2011Conference paper (Refereed)
    Abstract [en]

    This paper addresses the increasing complexity of software design for multiprocessor embedded systems by proposing a designmethodology that combines a formal foundation based on the theory of models of computation (MoCs) and the industrial systemdesign language SystemC. The ForSyDe methodology provides thedesigner with SystemC class libraries that lead to executable system models, from which abstract analyzable models can be extracted. Using these abstract models, the design exploration andsynthesis process can make use of existing MoC theory by for instance incorporating efficient scheduling and buffer optimizationtechniques. The choice of SystemC as modeling language allowsfor an efficient implementation, since system model functions canbe directly compiled to target processors.

  • 503.
    Sarif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An architectural countermeasure against power analysis attacks for FSR-based stream ciphers2012In: Lect. Notes Comput. Sci., 2012, p. 54-68Conference paper (Refereed)
    Abstract [en]

    Feedback Shift Register (FSR) based stream ciphers are known to be vulnerable to power analysis attacks due to their simple hardware structure. In this paper, we propose a countermeasure against non-invasive power analysis attacks based on switching activity masking. Our solution has a 50% smaller power overhead on average compared to the previous standard cell-based countermeasures. Its resistance against different types of attacks is evaluated on the example of Grain-80 stream cipher.

  • 504.
    Sarmiento M., David
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Pang, Zhibo
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, H.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mobile wireless sensor system for tracking and environmental supervision2010In: IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE 2010), IEEE conference proceedings, 2010, p. 470-477Conference paper (Refereed)
    Abstract [en]

    In this paper a system level analysis andimplementation of two-layer mobile wireless sensor networkarchitecture is proposed for tracking and environmentalsupervision applications. It uses a mobile Master Sensor Node(MSN) that collects information inside a Sensor Area Network(SAN) where many semi-passive Slave Sensor Nodes (SSN) aredeployed. The collected information is sent through a WirelessWide Area Network (WWAN) infrastructure to a central server viaTCP/UDP. The communication interface between the user and theMSN is established through out mobile communication services orinternet mail services. The communication between the MSN andthe SSN is through asymmetric-link Radio FrequencyIdentification (RFID) based architecture. An MSN prototype hasbeen implemented and tested under real conditions forenvironmental supervision during the perishable goodstransportation.

  • 505.
    Sarmiento M., David
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, H.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Baghaei-Nejad, Majid
    Sabzevar Tarbiat Moallem University, Sabzevar, Iran .
    A 9.2pJ/pulse UWB-IR transmitter with tunable amplitude for wireless sensor tags in 0.18um CMOS2010Conference paper (Refereed)
    Abstract [en]

    This paper presents a transmitter design for Ultra Wideband Impulse Radio (UWB-IR) communications. The design is targeted towards the implementation of passive Wireless Sensor Tags (WST) where micro-power consumption is required. The transmitter has been implemented in UMC 0.18μm CMOS and placed inside a QFN lead-less package. It complies with the FCC regulations for Pulse Rate Frequencies (PRF) up to 10MHz using OOK modulation. It is capable of adjusting the Power Spectral Emissions (PSE) modifying the transmitted pulse amplitude to always achieve the best BER/Power performance depending on the application demands. The power emission tunability has been validated implementing a complete communication link using a low sensitivity non-coherent energy receiver. Measurements show a maximum power consumption of 92uW@10MHz PRF having a maximum energy/pulse of 9.2 pJ.

  • 506.
    Sarmiento M., David
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhou, Qin
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Wang, Peng
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Analog front-end RX design for UWB impulse radio in 90nm CMOS2011In: 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, 2011, p. 1552-1555Conference paper (Refereed)
    Abstract [en]

    In this paper a reconfigurable differential Ultra Wideband-Impulse Radio (UWB-IR) energy receiver architecture has been simulated and implemented in UMC 90nm. The signal is amplified, rectified and integrated. By using an integration windowed scheme the SNR requirements are relaxed increasing the sensitivity. The design has been optimized for large bandwidths, low implementation area and configurability. The RX can be adapted to work at different data rates, processing gains, and channel environments. It works between the 3.1-4.8 GHz bands with OOK or PPM modulation with a tunable data rate up to 33Mb/s. In order to relax the ADC sampling time an interleave mode of operation has been implemented. It has a maximum power consumption of 22m W with a power supply of 1V. The complete RX occupies an area of 1.11mm2.

  • 507.
    Schamberger, Pierre
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Creation and validation of flows with IEEE1500 test wrapper for core-based test methodology2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    System-on-Chips are getting more complex every day, making manufacturing test constantly more challenging. As chip size is increasing, a divide and conquer approach is tackled, through a core-based methodology, using Synopsys Design-for-Test (DfT) state of the art features. This document deals with flows implementing such architectures. A wrapping core flow is proposed, limiting ports impact, thanks to compression feature. A full automated flow is proposed, as well as one offering more test possibilities, implementing wrapper bypass paths for full custom tests.

    Then a top-down flow is presented to tackle an actual complex ST-Ericsson project, using most of Synopsys features, showing first how to use the tool and which workarounds are to be implemented to achieve the expected architecture.

    As a parallel study, clock management under test, which is one of the most challenging parts in DfT flows, was examined. Clocks are handled with On-Chip-Clocking (OCC) controller, setting dynamically clock behavior through clock chains. It was shown that all clock chains should be handled in a single scan chain through compression modules. As a consequence, and to avoid a longer clock chain than regular chains, an update of the current Synopsys OCC controller was proposed, improving test time in coming projects.

  • 508.
    Schamberger, Pierre
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jiang, X.
    Qiu, M.
    Modeling and power evaluation of on-chip router components in spintronics2012In: Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012, IEEE , 2012, p. 51-58Conference paper (Refereed)
    Abstract [en]

    On-chip routers are power hungry components. Besides exploiting current CMOS-based power-saving techniques, it is also desirable to investigate the power saving potential enabled by new technologies and devices. This paper investigates the potential of exploiting the emerging spin-electronics based MTJ (Magnetic Tunnel Junction) devices with application to on-chip router modules, in particular, buffers and crossbars. To this end, we build MTJ models, design circuits based on mixed MTJ-CMOS devices, and evaluate their switching power consumption, using their pure CMOS counterparts as the baseline. Our study shows that the new technology can significantly improve power efficiency for buffers but the gain for crossbars is less clear.

  • 509. Schaumont, Patrick
    et al.
    Sheeran, Mary
    Singh, Satnam
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Object Oriented Approach versus Functional Approach in System Design2000In: Proceedings of the Forum on Design Languages, 2000Conference paper (Refereed)
  • 510. Seceleanu, Tiberiu
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Modeling Communication with Synchronized Environments2008In: Fundamenta Informaticae, ISSN 0169-2968, E-ISSN 1875-8681, Vol. 86, no 3, p. 343-369Article in journal (Refereed)
    Abstract [en]

    A deterministic behavior of systems composed of several modules is a desirable design goal. Assembling a complex system from components requires also a high degree of re-usability. The compatibility of the selected components may become a problem even at abstract design levels, due to possible different degrees of model determinacy, possible different execution models, etc. In this cases, an overall deterministic system behavior is difficult to achieve. The development of communication mechanisms between such components will have then to accommodate the differences, so that both correct processing and information exchange (data and control, appropriate choices and relative timing or sequencing) are achieved. For instance, human-machine interaction offers a good example of cooperation between deterministic models (machines) communicating with highly non-deterministic counterparts (the human models, if not restricted). We analyze here such communication mechanisms by "confronting" synchronized and un-synchronized models of execution, in the framework of action systems, a state based formalism. We "force" the two models to coexist within the same context and explore the possibilities of building trustworthy communication channels between them. We base our approach on a combined polling - interrupt scheme, which allows us to mitigate communication issues that may otherwise compromise the correct input-output system behavior. More robust system models are obtained by applying specific correctness rules of refinement. We illustrate our methods on an audio system example, implementable as either a software or a hardware device.

  • 511.
    Shami, Muhammad Ali
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dynamically Reconfigurable Resource Array2012Doctoral thesis, monograph (Other academic)
    Abstract [en]

    The goals set by the International Technology Roadmap for Semiconductors (ITRS) for the consumer portable category, to be realized by 2020, are 1000X improvement in performance with only 40\% increase in power budget and no increase in design team size. To meet these goals, the challenges facing the VLSI community are gaps in architecture efficacy, design productivity and battery capacity.As the causes of the gaps in architecture efficacy and battery capacity, this thesis identifies: a) instruction granularity mismatch, b) bit-width granularity mismatch, c) silicon granularity mismatch and d) parallelism mismatch. Field Programmable Gate Array(FPGA) technology can address instruction/bit-width granularity and parallelism mismatch but suffers from silicon granularity mismatch due to high reconfiguration overheads. The ultimate design goal of a system-on-chip is to achieve an ASIC-like performance and FPGA-like flexibility, design time and cost. Coarse Grain Reconfigurable Architectures (CGRAs) are a compromise between ASIC and FPGA since they provide better computational efficiency compared to FPGAs and better engineering efficiency compared to ASIC. However, the current generation of CGRAs lack many architectural properties that would enable them to replace ASIC and/or FPGA by mainstream industry.To objectively discuss these properties, in the first part of the thesis a classification scheme has been proposed that classifies parallel computing machines into 47 classes and propose how they can be graded in terms of flexibility. We apply this classification scheme on academic and industrial reconfigurable architectures to compare them for their similarities and differences. We identify an instruction flow spatial computing class to be used for a CGRA fabric called Dynamically Reconfigurable Resource Array (DRRA) presented in the second part of this thesis. The DRRA fabric is a Parallel Distributed Digital Signal Processing (PDDSP) fabric with distributed arithmetic, logic, interconnect and control resources. Problems associated with the distributed control model of DRRA are identified and architectural solutions that can be exploited by the compiler tools are presented.After logical and physical synthesis, DRRA shows a peak performance of 21 GOPS and peak silicon efficiency of 16.03 GOPS/mm\textsuperscript{2}. We further performed a three-level validation of the DRRA fabric. At first level, we mapped a number of signal and compute intensive algorithms to demonstrate the flexibility of the DRRA fabric. At second level, we measured the gap between ASIC, DRRA and FPGA. On average DRRA shows 22.87x area, 10.75x power consumption, 852x configuration bits, 959x configuration cycles, 63,94x silicon efficiency, 4.78x computational efficiency, and 6.15E+10x better energy-delay product improvements compared to FPGA. Finally, at third level we present the use of DRRA for a real world example of implementing a 128-, 256-, 512-, 1024-, 2048-point configurable FFT processor. For 1024 point FFT, in terms of computational efficiency, DRRA outperforms all CGRAs by at least 2x and is worse than ASIC by 3.45x. As regards silicon efficiency, although dedicated processors perform 1.6x better, DRRA is better than all other CGRAs.

  • 512.
    Shami, Muhammad Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Address generation scheme for a coarse grain reconfigurable architecture2011In: Proc. IEEE Int Application-Specific Systems, Architectures and Processors (ASAP) Conf, 2011, p. 17-24Conference paper (Refereed)
    Abstract [en]

    In this paper, we describe a versatile address generation scheme for distributed storage resources of a coarse grain Parallel Distributed Digital Signal Processing (PDDSP) reconfigurable architecture under development in our group. This scheme proposes the distributed address generation units (AGUs) to decouple the address generation logic with compute logic to exploit parallelism (ILP and TLP). To achieve this, the proposed distributed address generation scheme with standard DSP address generation modes like linear vectorized, circular buffer and bit-reverse addressing, all with parameterizable address range and increment/decrement offsets is further enhanced with temporal flexibility by introducing three dynamically programmable delays: initial delay before the stream starts, middle delay after every address generation for the stream and end delay after the stream is complete. The dynamic programmability of these delays makes streams elastic that can be chained with an interrupt mechanism to create chained-elastic streams. Our approach is compared with the traditional approach of using VLIW and Scalar. Our approach shows 21times;(Scalar), 10×(VLIW) reduction in instructions and 2×(Scalar) reduction in cycles for a single thread FIR filter. When compared for Synchronous and Asynchronous scenarios of two parallel treads T1 and T2, our approach shows 4.6×(Scalar), 5.6×(VLIW) reduction in instructions, 1.76 reduction in cycles for Synchronous and 4.6×(Scalar), 15×(VLIW) eduction in instructions, 1.76×(Scalar) reduction in cycles for Asynchronous threads.

  • 513.
    Shami, Muhammad Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An improved self-reconfigurable interconnection scheme for a Coarse Grain Reconfigurable Architecture2010In: NORCHIP 2010: 28th Norchip Conference, 2010Conference paper (Refereed)
    Abstract [en]

    An improved Dynamic, Partial and self reconfigurable interconnection network (Hybrid-2 Network) is presented for Dynamically Reprogrammable Resource Array (DRRA), which is a Coarse Grain Reconfiguration Architecture (CGRA). To justify the design decision, Hybrid-2 network implementation is compared against the possible implementations using Multiplexer, NoC, Crossbar and already published Hybrid-1 interconnection network. Results shows that newly presented Hybrid-2 Interconnection network take (1.08x, 0.104x, 0.212x and 0.681x) the area, (1x, 0.037x, 0.026x and 0.107x) the configuration bits of Multiplexer, NoC, Crossbar and Hybrid-1 Implementation respectively. Hybrid-2 network is also 2.87x and 5.86x faster than Multiplexer and Hybrid-1 networks.

  • 514.
    Shami, Muhammad Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Classification of Massively Parallel Computer Architectures2012In: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012, IEEE , 2012, p. 344-351Conference paper (Refereed)
    Abstract [en]

    Faced with slowing performance and energy benefits of technology scaling, VLSI/Computer architectures have turned from parallel to massively parallel machines for personal and embedded applications in the form of multi and many core architectures. Additionally, in the pursuit of finding the sweet spot between engineering and computational efficiency, massively parallel Coarse Grain Reconfigurable Architectures(CRGAs) have been researched. While these articles have been surveyed, they have not been rigorously classified to enable objective differentiation and comparison for performance, area and flexibility. In this paper, we extend the well known Skillicorn taxonomy to create new classes, present a scoring system to rate these classes on flexibility, and present equations for early estimation of area and configuration overheads. Furthermore, we use this extended classification scheme to classify and compare 25 different massively parallel architectures that covers most of the reported CGRAs and other well known multi and many core architectures.

  • 515.
    Shami, Muhammad Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Control Scheme for a CGRA2010In: Proc. 22nd Int Computer Architecture and High Performance Computing (SBAC-PAD) Symp, 2010, p. 17-24Conference paper (Refereed)
    Abstract [en]

    Ability to instantiate low cost and agile FSMs that can implement an arbitrary parallelism and combine such FSMs in a chain and in a hierarchy is one of the key differentiating factors between the ASICs and MPSOCs. CGRAs that have been reported in literature, like MPSOCs, also lack this ASIC like ability. The downside of ASICs is their lack of reuse and high engineering cost. We present a CGRA architecture that retains the programmability of CGRA and yet has the ASIC like ability to construct a) arbitrarily parallel data-path/FSM combine, b) chain an arbitrary number of such FSMs and c) create a hierarchy of such chains. We present in detail the architecture of such a control scheme and illustrate its use for an example composed of FFT and FIRs. We quantify the benefits of our approach by benchmarking for energy-delay product against a) ASICs (4.8X worse), b) a state-of-the-art CGRA (4.58X better) and FPGAs (63.95X better).

  • 516.
    Shami, Muhammad Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Morphable DPU: Smart and Efficient Data Path for Signal Processing Applications2009In: SIPS: 2009 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, 2009, p. 167-172Conference paper (Refereed)
    Abstract [en]

    A coarse grained morphable Datapath Unit (mDPU) has been proposed. This mDPU implements multiplier in a smart way that enables the component adders to be reused when we do not need the multiplier. A pipelined design further enhances the design by creating a balanced datapath in temporal sense. These two features results in a design that optimally uses silicon and time. A judicious set of Coarse Granular instructions are enabled by the mDPU that we show can implement typical signal processing functions. A radix-2 64 point FFT has been implemented in 90 nm technology using the proposed mDPUs and performance and energy results from physical design phase are reported and compared to a state-of-the-art comparable design from the research community. 4X improvement in performance and 2.5X improvement in power-performance product are reported.

  • 517.
    Shami, Muhammad Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Partially Reconfigurable Interconnection Network for Dynamically Reprogrammable Resource Array2009In: 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS / [ed] Tang TA; Zeng XY; Chen Y; Yu HH, NEW YORK: IEEE , 2009, p. 122-125Conference paper (Refereed)
    Abstract [en]

    This paper describes an innovative regular non-blocking, point-to-point, point-to-multipoint, low latency interconnection network scheme with sliding window connectivity, which allows arbitrary parallelism among large sub-systems. The area overhead of interconnect is only 30% of the chip area which is much smaller as compared to 80% in case of FPGA. The interconnection scheme is partially and dynamically reconfigurable. The configware is reduced 5.6 times by using binary encoding which allows energy efficient dynamic reconfiguration(1).

  • 518.
    Shao, Botao
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Fully Printed Chipless RFID Tags towards Item-Level Tracking Applications2014Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    An ID generating circuit is unquestionably the core of a chipless RFID tag. For convenience of printing process and cost consideration, the circuit should be kept as simple as possible. Based on the cognition, an 8-bit time-domain based ID generating circuit that merely consists of a ML and eight capacitors was offered, and implemented on photo-paper substrates via inkjet printing process. In addition to the experimental measurements, the circuit was also input into circuit simulators for cross-validation. The good agreement between simulations and measurements is observed, exhibiting the tag technical feasibility. Besides of low cost, the tag has wide compatibility with current licensed RFID spectrum, which will facilitate the future deployment in real applications.

    Compared   to  time-domain   based  chipless   tags,  frequency   signatures   based chipless RFID tags are expected to offer a larger coding capacity. As a response, we presented a 10-bit frequency-domain based chipless RFID tag. The tag composed of ten configurable LC resonators was implemented on flexible polyimide substrate by using  fast  toner-transferring  process.  Field  measurements  revealed  not  only  the practicability  of  the  tag,  but  also  the  high  signal  to  noise  ratio  (SNR).  Another frequency domain tag consists of a configurable coplanar LC resonator. With the use of all printing process, the tag was for the first time realized on common packaging papers.  The tag feasibility was confirmed by subsequent measurements. Owing to the ultra-low cost potential and large SNR, The tag may find wide applications in typical RFID solutions such as management of paper tickets for social events and governing of smart documents.

    Ultra wide band (UWB) technology possesses a number of inherent merits such as high speed communication and large capacity, multi-path immunity, accurate ranging and positioning, penetration through obstacles, as well as extremely low-cost and low- power transmitters. Thus, passive UWB RFIDs are expected to play an important pole in  the future identification applications for IoT. We explained the feature difference between  UWB  chipless  tags  and  chip  based  tags,  and  forecasted  the  applications respectively  based on the comparison  between the two technologies.  It is expected that the two technologies will coexist and compensate each other in the applications of IoT.

    Lastly, the thesis ends up with brief summary of the author’s contributions, and technical prospect for the future development of printable chipless RFID tags.

     

  • 519.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Liu, Ran
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Directly Printed Packaging-Paper-Based Chipless RFID Tag With Coplanar LC Resonator2013In: IEEE Antennas and Wireless Propagation Letters, ISSN 1536-1225, E-ISSN 1548-5757, Vol. 12, p. 325-328Article in journal (Refereed)
    Abstract [en]

    This letter presents the design, simulation, fabrication, and characterization of an LC-resonator-based chipless RFID tag. The ID-generating circuit is designed based on a reconfigurable LC resonance circuit. Phase position modulation (PPM) coding is used for the enhancement of the coding capacity. The tag has been realized on packaging paper using all printing technique. In fabrication, overprinting process has been investigated as an effective pathway for the improvement of the conductivities. The tag with 4.25-bit coding capacity has been examined using a sweeping frequency signal transmitted from a vector network analyzer, and experimental results confirm the feasibility of the proposed chipless tag. With further optimizations, the tag can be used in the item-level tracking and identification applications, especially for the management of paper tickets and banknotes.

  • 520.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Liu, Ran
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chipless RFID tags fabricated by fully printing of metallic inks2013In: Annales des télécommunications, ISSN 0003-4347, E-ISSN 1958-9395, Vol. 68, no 7-8, p. 401-413Article in journal (Refereed)
    Abstract [en]

    This paper reviews recent advances in fully printed chipless radio frequency identification (RFID) technology with special concern on the discussion of coding theories, ID generating circuits, and tag antennas. Two types of chipless tags, one based on time-domain reflections and the other based on frequency domain signatures, are introduced. To enable a fully printed encoding circuit, linearly tapering technique is adopted in the first type of tags to cope with parasitic resistances of printed conductors. Both simulation and measurement efforts are made to verify the feasibility of the eight-bit fully printed paper-based tag. In the second type of tags, a group of LC tanks are exploited for encoding data in frequency domain with their resonances. The field measurements of the proof-of-concept of the tag produced by toner-transferring process and flexible printed circuit boards are provided to validate the practicability of the reconfigurable ten-bit chipless RFID tag. Furthermore, a novel RFID tag antenna design adopting linearly tapering technique is introduced. It shows 40 % save of conductive ink materials while keeping the same performance for conventional half-wave dipole antennas and meander line antennas. Finally, the paper discusses the future trends of chipless RFID tags in terms of fabrication cost, coding capacity, size, and reconfigurability. We see that, coupled with revolutionary design of low-cost tag antennas, fabrication/reconfiguration by printing techniques, moving to higher frequencies to shrink tag sizes and reduce manufacturing cost, as well as innovation in ID generating circuits to increase coding capacities, will be important research topics towards item-level tracking applications of chipless RFID tags.

  • 521.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sarmiento Mendoza, David
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Liu, Ran
    Fudan University.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An ultra-low-cost RFID tag with 1.67 Gbps data rate by ink-jet printing on paper substrate2010In: 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, 2010, p. 109-112Conference paper (Other academic)
    Abstract [en]

    A fully metallic ink-jet printed passive chipless RFID tag on paper substrate is presented. The tag consists of an ultra-wide-band antenna, a microstrip transmission line with distributed shunt capacitors as information coding element which is reconfigurable by ink-jet printing process. Tapered microstrip line is employed to overcome the limitations of low conductivity and thin film thickness of ink-jet printed metal tracks. Measurement results show that the tag features a robust readability over 80 cm reading distance and a high data rate of 1.67 Gb/s.

  • 522.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Liu, Ran
    Fudan University.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A reconfigurable chipless RFID tag based on sympathetic oscillation for liquid-bearing applications2011In: 2011 5th IEEE International Conference on RFID, RFID 2011, 2011, p. 170-175Conference paper (Other academic)
    Abstract [en]

    This paper reports on the development of a 10-bit chipless RFID tag on flexible plastic substrate. This tag is based on sympathetic oscillations of a group of LC circuits with different resonant frequencies. Sophisticated designs including the placement of capacitors involved in each LC circuit, and various LC combinations are examined for the trade-off of the readability and the tag sizes. Moreover, the antennas for detecting the proposed tags are presented. The measurement results show that the proposed tag possesses remarkable readability for a read range up to 21 cm and more importantly, it is suited for tagging liquid-bearing containers, which are widely used in food and medical industries. In addition, this tag is reconfigurable on circuit level, enabling a potential pathway towards the realization of low cost RFID tags for HF/VHF band applications.

  • 523.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Liu, Ran
    Fudan University.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    CONFIGURABLE INK-JET-PRINTED RFID TAG ON PAPER SUBSTRATE FOR LOW COST AND GREEN APPLICATIONS2011In: Microwave and optical technology letters (Print), ISSN 0895-2477, E-ISSN 1098-2760, Vol. 53, no 12, p. 2781-2786Article in journal (Refereed)
    Abstract [en]

    The letter presents the design, fabrication, and measurement of a configurable radio frequency identification (RFID) tag based on time-domain reflections. The tag circuit contains a microstrip line (ML) that propagates radio frequency (RF) signals, and a group of capacitors that introduce impedance discontinuities to encode binary codes. The configurability of the tag circuit is allowed by connecting the nearby-placed capacitors with the ML. Ink-jet printing technology is employed to implement the layout of the proposed tag on paper substrate. To overcome the limitations of printed metallic tracks, a linearly tapering technique is proposed. With this technique, a four-bit configurable passive chipless RFID tag is realized. Both time-domain reflectometry (TDR) measurements and ultrawideband (UWB) characterizations were conducted for the proposed tag, and the results are in good consistence with the simulation ones from the circuit simulator advanced design system (ADS). Owing to its low cost fabrication and environmentally friendly nature, the proposed tag has great potential to be widely employed in low-end RFID applications. (C) 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53: 2781-2786, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26412

  • 524.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Liu, Ran
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Design of fully printable and configurable chipless RFID tag on flexible substrate2012In: Microwave and optical technology letters (Print), ISSN 0895-2477, E-ISSN 1098-2760, Vol. 54, no 1, p. 226-230Article in journal (Refereed)
    Abstract [en]

    This article presents the design and implementation of a chipless radio frequency identification (RFID) tag on flexible substrate.The tag is designed based on the sympathetic oscillations of multiple LC (inductor–capacitor) circuits that possess distinct resonant frequencies. Information is encoded by controlling placement of these resonant frequencies. To trade off the readability and size of the tag, the optimizations including capacitor placements and different LC combinations are studied. The tag is then realized onto flexible polyimide substrate using toner-transferring process. The detection system is also constructed and used to measure the proposed tag. The measurement results show that the tag can provide an excellent readability more than 20 cm reading range. In addition, this tag is fully printable and configurable, hence making it more feasible and considerably cheaper to be used. This tag can provide a meaningful approach toward the realization of ultralow-cost RFID tags attached onto low-value items.

  • 525.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Liu, Ran
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Linearly-tapered RFID tag antenna with 40% material reduction for ultra-low-cost applications2011In: 2011 IEEE International Conference on RFID, 2011, p. 45-49Conference paper (Other academic)
    Abstract [en]

    The development of RFID technology are requiring high performance and low cost tag antennas than ever before. To meet these demands, linear tapering technique is firstly proposed in the design of planar tag antennas. With this strategy, the current distribution along antenna arms is effectively assigned by varying the antenna line width. Compared with conventional ones, the tapered antennas can reduce the material cost by over 40% not only for PCB (Printed Circuit Board) processed, but also for ink-jet printing produced dipole and meander line antennas, while they still maintain comparable performance. With an identical volume of conducting material, the tapered antennas can achieve better radiation performance than non-tapered ones on antenna gains and radiation efficiencies. The method has been successfully verified by applying it onto 869 MHz and 2.45 GHz antennas. The influence of the tapering technique on antenna bandwidth is also investigated.

  • 526.
    Sharif Mansouri, Shohreh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Design and Implementation of Efficient and Secure Lightweight Cryptosystems2014Doctoral thesis, monograph (Other academic)
    Abstract [en]

    In recent years there has been a wide-spread deployment of battery-powered and passive devices such as RFID tags, systems with very strong limitations on area, cost and power budgets. Deploying cryptographic solutions for these systems is both important, because it could unlock several security-critical applications, and challenging, due to the stringent budgets: the overheads of even the smallest block ciphers are often one or more orders of magnitude too high. Because of this reason there is a growing interest in lightweight cryptography, a discipline that tries to develop cryptographic solutions for systems with very tight cost, area and power constraints. The importance of lightweight cryptography is forecasted to continue growing in the future, with lightweight systems becoming more ubiquitous and more common in sensitive applications.In this work we analyse and solve several problems related to light weight cryptography. We first study efficient implementations of feedback shift registers (FSR)-based cryptosystems, such as stream ciphers and hash functions, that are especically designed for highly-constrained environments. The core of our solution is to apply a Fibonacci-to-Galois transformation that changes the structure of an FSR to minimise its critical path. Along with this transformation we apply several hardware optimization techniques, such as pipelining and double-frequency clock generators, that are necessary to obtain through-put benefits. Our results show impressive throughput improvements (100% for some cryptographic systems) without any area and power penalties. In a second part, we show how to protect FSR-based stream ciphers from power analysis attacks, a type of attack that exploits the information content in the power trace of a system. It is well known that, due to their very simple hardware structure, FSR-based stream ciphers are very vulnerable to this type of attacks. We introduce two different countermeasures against power analysis attacks: one at the architectural level (masking the switching activity of the FSRs) and the other one at the physical level ( flattening the power curve to one among two power levels). Both solutions exploit the properties of FSR-based stream ciphers with the specic goal to minimise their area and power overheads. We demonstrate them on the FSR-based stream cipher Grain by performing Differential Power Analysis (DPA) and Mutual Information Analysis (MIA) attacks at SPICE level. However, the techniques we introduce are general and can potentially be applied to any FSR-based stream ciphers. In a third part, we focus on Ring Oscillator Physical Unclonable Functions (RO-PUFs), a type of digital fingerprint used for chip identication that is well-suited for lightweight cryptography. We suggest solutions to two well-known problems related to this type of PUF: how to generate a secure and large challenge-response database and how to increase PUF reliability in presence of temperature variations. We validate our solutions at SPICE level by modelling the random variations introduced during manufacturing.

  • 527.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A countermeasure against power analysis attacks for FSR-based stream ciphers2011In: Proc. ACM Great Lakes Symp. VLSI GLSVLSI, 2011, p. 235-240Conference paper (Refereed)
    Abstract [en]

    In this paper we analyze the power characteristics of Feedback Shift Registers (FSRs) and their e ect on FSR-based stream ciphers. We introduce a technique to isolate the switching activity of a stream cipher by equalizing the current drawn from the cipher with lower power overhead compared to previously introduced countermeasures. By re-implementing the Grain-80 and the Grain-128 ciphers with the presented approach, we lower their power consumption respectively by 20% and 25% compared to previously proposed countermeasures.

  • 528.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An improved hardware implementation of the Grain stream cipher2010In: Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010, 2010, p. 433-440Conference paper (Refereed)
    Abstract [en]

    A common approach to protect confidential information is to use a stream cipher which combines plain text bits with a pseudo-random bit sequence. Among the existing stream ciphers, Non-Linear Feedback Shift Register (NLFSR)-based ones provide the best trade-off between cryptographic security and hardware efficiency. In this paper, we show how to further improve the hardware efficiency of the Grain stream cipher. By transforming the NLFSR of Grain from its original Fibonacci configuration to the Galois configuration and by introducing new hardware solutions, we double the throughput of the 80 and 128-bit key 1 bit/cycle architectures of Grain with no area and power penalty.

  • 529.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An Improved Hardware Implementation of the Grain-128a Stream Cipher2012In: Lecture Notes in Computer Science / [ed] Springer-Verlag, 2012, p. 278-292Conference paper (Refereed)
    Abstract [en]

    We study efficient high-throughput hardware implementations of the Grain-128a family of stream ciphers. To increase the throughput compared to the standard design, we apply five different techniques in combination: isolation of the authentication section, Fibonacci-to-Galois transformation of the feedback shift registers, multi-frequency implementation, simplification of the pre-outputs functions and internal pipelining. The combined effect of all these techniques enables an average 56% higher keystream generation throughput among all the ciphers, at the expense of an average 8% area penalty, an average 4% power overhead and a 21% slower keystream initialization phase. An alternative combination of techniques allows an average 23% throughput improvement in all phases.

  • 530.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Double-edge transformation for optimized power analysis suppression countermeasures2013In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, IEEE , 2013, p. 353-359Conference paper (Refereed)
    Abstract [en]

    We introduce a power optimization technique for suppression countermeasures against Power Analysis attacks that can potentially be applied to any type of crypto-system implemented as a synchronous digital system. Since the power consumption of systems protected by suppression countermeasures is proportional to current peaks, we propose a simple transformation to move some of the switching activity of the crypto-system from the rising edge to the falling edge of the clock, so that current peaks are reduced. The transformation is easy to apply, requires only standard cell logic gates, has a low area overhead but can reduce the maximal working frequency of a system by at most a factor 2. We prove our method on an ASIC implementation of the Grain-80 stream cipher using SPICE-level simulation, obtaining 50% power savings compared to the non-optimized suppression countermeasure.

  • 531.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Power-security trade-off in multi-level power analysis countermeasures for FSR-based stream ciphers2012In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2012), IEEE , 2012, p. 81-84Conference paper (Refereed)
    Abstract [en]

    Feedback Shift Register (FSR) based stream ciphers are one of the most promising new groups of cryptographic algorithms, which target applications characterized by strong power, area and cost constraints. Due to high sensibility against power analysis attacks, there is a strong need for countermeasures which increase the immunity of this class of ciphers without introducing large power and area overheads. In this paper we study analog multi-level countermeasures which can protect FSR-based stream ciphers against Differential Power Analysis (DPA) attacks, with lower power overhead compared to alternative solutions that can be found in literature. We highlight a trade-off between power consumption and security, and propose an approach which ensures at the same time low power overhead and high security against power analysis attacks.

  • 532.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Pulse Latch Based FSRs for Low-Overhead Hardware Implementation of Cryptographic Algorithms2010In: 2010 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2010, p. 253-259Conference paper (Refereed)
    Abstract [en]

    In this paper, we address the problem of low-overhead implementation of Feedback Shift Registers (FSRs). We present a dynamic pulse latch which is based on transistors with two different channel lengths. The channel lengths are selected to make the latch suitable for replacing flip-flops in FSRs. The presented latch is 1.92 times smaller and 3.94 times less power consuming compared to the smallest standard flip-flop in the same technology. By re-implementing FSRs of Grain-80 stream cipher with the presented latch, we achieve 32.24% reduction in area, 36.77% reduction in total power, and 10.81% increase in the maximum clock frequency compared to the original, flip-flop based version of Grain-80. If, in addition, the static time borrowing technique is applied, we achieve an additional 25.5% increase in the maximum clock frequency at the expense of 4.68% smaller gain in area and 2.67% smaller gain in total power.

  • 533.
    Sharif Mansouri, Shohreh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ring oscillator physical unclonable function with multi level supply voltages2012In: Computer Design (ICCD), 2012 IEEE 30th International Conference on, IEEE Computer Society, 2012, p. 520-521Conference paper (Refereed)
    Abstract [en]

    In this paper we introduce a new type of Ring Oscillator PUF (RO-PUF) in which the inverters composing the ring oscillators can be supplied by independent voltages. This new RO-PUF can improve the reliability of the PUF in case of temperature variations.

  • 534.
    She, Huimin
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Performance Analysis and Deployment Techniques forWireless Sensor Networks2012Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Recently, wireless sensor network (WSN) has become a promising technology with a wide range of applications such as supply chain monitoring and environment surveillance. It is typically composed of multiple tiny devices equipped with limited sensing, computing and wireless communication capabilities. Design of such networks presents several technique challenges while dealing with various requirements and diverse constraints. Performance analysis and deployment techniquesare required to provide insight on design parameters and system behaviors.

    Based on network calculus, a deterministic analysis method is presented for evaluating the worst-case delay and buffer cost of sensor networks. To this end,traffic splitting and multiplexing models are proposed and their delay and buffer bounds are derived. These models can be used in combination to characterize complex traffic flowing scenarios. Furthermore, the method integrates a variable duty cycle to allow the sensor nodes to operate at low rates thus saving power. In an attempt to balance traffic load and improve resource utilization and performance,traffic splitting mechanisms are introduced for sensor networks with general topologies. To provide reliable data delivery in sensor networks, retransmission has been one of the most popular schemes. We propose an analytical method to evaluate the maximum data transmission delay and energy consumption of two types of retransmission schemes: hop-by-hop retransmission and end-to-end retransmission.In order to validate the tightness of the bounds obtained by the analysis method, the simulation results and analytical results are compared with various input traffic loads. The results show that the analytic bounds are correct and tight.

    Stochastic network calculus has been developed as a useful tool for Qualityof Service (QoS) analysis of wireless networks. We propose a stochastic servicecurve model for the Rayleigh fading channel and then provide formulas to derive the probabilistic delay and backlog bounds in the cases of deterministic and stochastic arrival curves. The simulation results verify that the tightness of the bounds are good. Moreover, a detailed mechanism for bandwidth estimation of random wireless channels is developed. The bandwidth is derived from the measurement of statistical backlogs based on probe packet trains. It is expressed by statistical service curves that are allowed to violate a service guarantee with a certain probability. The theoretic foundation and the detailed step-by-step procedure of the estimation method are presented.

    One fundamental application of WSNs is event detection in a Field of Interest(FoI), where a set of sensors are deployed to monitor any ongoing events. To satisfy a certain level of detection quality in such applications, it is desirable that events in the region can be detected by a required number of sensors. Hence, an important problem is how to conduct sensor deployment for achieving certain coverage requirements. In this thesis, a probabilistic event coverage analysis methodis proposed for evaluating the coverage performance of heterogeneous sensor networks with randomly deployed sensors and stochastic event occurrences. Moreover,we present a framework for analyzing node deployment schemes in terms of three performance metrics: coverage, lifetime, and cost. The method can be used to evaluate the benefits and trade-offs of different deployment schemes and thus provide guidelines for network designers.

  • 535.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    System-level evaluation of sensor networks deployment strategies: Coverage, lifetime and cost2012In: 2012 8th International Wireless Communications And Mobile Computing Conference (IWCMC), IEEE , 2012, p. 549-554Conference paper (Refereed)
    Abstract [en]

    In wireless sensor networks, sensor nodes can be organized either randomly or deterministically according to regular deployment patterns. Due to the trade-offs between performance and cost, evaluating the advantages and disadvantages of node deployment strategies are fundamental issues to be solved. In this paper, we present a framework for analyzing node deployment schemes in terms of three performance metrics: coverage, lifetime, and cost. Based on the proposed coverage analysis model, energy model and cost model, we compare the performance of two node deployment schemes: rectangle mesh and uniformly random. The results show that the rectangle mesh scheme is generally better than the uniformly random scheme in terms of coverage and network lifetime. Our method can be used to evaluate the benefits of different deployment schemes and thus provide guidelines for network designers.

  • 536.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhou, Dian
    Department of Microelectronics, Fudan Universiy.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Modeling and Analysis of Rayleigh Fading Channels using Stochastic Network Calculus2011Conference paper (Refereed)
    Abstract [en]

    Deterministic network calculus (DNC) is not suitable for deriving performance guarantees for wireless networks due to their inherently random behaviors. In this paper, we develop a method for Quality of Service (QoS) analysis of wireless channels subject to Rayleigh fading based on stochastic network calculus. We provide closed-form stochastic service curve for the Rayleigh fading channel. With this service curve, we derive stochastic delay and backlog bounds. Simulation results verify that the bounds are reasonably tight. Moreover, through numerical experiments, we show the method is not only capable of deriving stochastic performance bounds, but also can provide guidelines for designing transmission strategies in wireless networks.

  • 537.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhou, Dian
    Department of Microelectronics, Fudan Universiy.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks2012In: International Journal of Distributed Sensor Networks, ISSN 1550-1329, p. 232937-Article in journal (Refereed)
    Abstract [en]

    Performance analysis is crucial for designing predictable and cost-efficient sensor networks. Based on the network calculus theory, we propose a flow-based traffic splitting strategy and its analytical method for worst-case performance analysis on cluster-mesh sensor networks. The traffic splitting strategy can be used to alleviate the problem of uneven network traffic load. The analytical method is able to derive close-form formulas for the worst-case performance in terms of the end-to-end least upper delay bounds for individual flows, the least upper backlog bounds, and power consumptions for individual nodes. Numerical results and simulations are conducted to show benefits of the splitting strategy as well as validate the analytical method. The numerical results show that the splitting strategy enables much better balance on network traffic load and power consumption. Moreover, the simulation results verify that the theoretic bounds are fairly tight.

  • 538.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zhou, Dian
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Stochastic Coverage in Event-Driven Sensor Networks2011In: 2011 IEEE 22nd International Symposium On Personal Indoor And Mobile Radio Communications (PIMRC), New York: IEEE , 2011, p. 915-919Conference paper (Refereed)
    Abstract [en]

    One of the primary tasks of sensor networks is to detect events in a field of interest (FoI). To quantify how well events are detected in such networks, coverage of events is a fundamental problem to be studied. However, traditional studies mostly focus on analyzing the coverage of the FoI, which is usually called are a coverage. In this paper, we propose an analytic method to evaluate the performance of event coverage in sensor networks with randomly deployed sensor nodes and stochastic event occurrences. We provide formulas to calculate the probabilities of event coverage and event missing. The numerical results show how these two probabilities change with the sensor and event densities. Moreover, simulations are conducted to validate the analytic method. This method can provide guidelines for determining the amount of sensor nodes to achieve a certain level of coverage in event-driven sensor networks.

  • 539.
    Shen, Jue
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Xie, Li
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A Passive UHF-RFID Tag with Inkjet-Printed Electrochromic Paper Display2013In: Proceedings of the IEEE International Conference on RFID (RFID), 2013, IEEE conference proceedings, 2013, p. 118-123Conference paper (Refereed)
    Abstract [en]

    In this paper, an inkjet-printed electrochromic(EC) paper display integrated with passive UHF-RFID tag is introduced as a solution for passive electronic shelf labels (ESL). To address the system challenges of the limited power budget of passive UHF-RFID tags and the material aging of EC display, a feedback comparator integrated digital displaydriver is proposed based on the study of electrochromic, bi-stable and aging features of the EC display. Modularized baseband with different enableconditions and clock domains is implemented in the system design level. Moreover, to maintain the system functions when the input power is lower than the display refresh power, a duty-cycled power management unit (PMU) is activated to reduce the load current during energy scavenging and drive the display in short intervals, enabling the fast charging of the voltage rectifier and the correct output of the regulated supply for the core circuit. The design is fabricated in a 0.18-um CMOS process with an area of 2.25 mm2. Fed with EPC C1G2 protocol write command, experiments demonstrate correct refresh of EC display with 4 cm2 effective area. System sensitivity at the antenna reference point is basically immune to the display load. Further improvements can be achieved after careful chip-to-antenna impedance matching and PMU efficiency optimization.

  • 540. Simon, T. M.
    et al.
    Thomas, B. H.
    Smith, R. T.
    Smith, Mark
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Adding input controls and sensors to RFID tags to support dynamic tangible user interfaces2014In: TEI '14 Proceedings of the 8th International Conference on Tangible, Embedded and Embodied Interaction, Association for Computing Machinery (ACM), 2014, p. 165-172Conference paper (Refereed)
    Abstract [en]

    Providing high resolution tangible user interface components without batteries such as dials and sliders that support dynamic user interface arrangement is challenging. Previous work uses RFID to support limited resolution custom-built components. We demonstrate improved techniques using commercial off the shelf input controls incorporated into passive RFID tags using an on-off key subcarrier to encode state information into the RFID signal. Our method supports high resolution components that do not require power cables or batteries. We provide exemplars demonstrating how the technique supports a range of user interface components including buttons, dials, sliders, flex and light sensors. Compared to previous work, we obtain a higher resolution, only limited by sample time, for all components and demonstrate 115 discrete dial positions. Our technique allows the TUI components to be freely placed and rearranged without hardwiring or batteries.

  • 541. Sinn, T.
    et al.
    Brown, R.
    McRobb, M.
    Wujek, Adam
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lowe, C.
    Weppler, J.
    Parry, T.
    Yarnoz, D. G.
    Brownlie, F.
    Skogby, Jerker
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dolan, I.
    De Franca Queiroz, T.
    Rogberg, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Donaldson, N.
    Clark, R.
    Tibert, Gunnar
    KTH, School of Engineering Sciences (SCI), Mechanics, Structural Mechanics.
    Lessons learned from three university experiments onboard the REXUS/BEXUS sounding rockets and stratospheric balloons2013In: 64th International Astronautical Congress 2013, International Astronautical Federation, 2013, p. 7965-7976Conference paper (Refereed)
    Abstract [en]

    Over the last three years the authors have been involved in three experiments that were or will be launched on sounding rockets and high altitude balloons with the REXUS/BEXUS program (Rocket-borne / Balloon-borne Experiments for University Students). The first experiment, called Suaineadh was launched from Esrange (Kiruna, Sweden) onboard REXUS 12 in March 2012. Suaineadh had the purpose of deploying a web in space by using centrifugal forces. The payload was lost during re-entry but was recovered 18 month later in early September 2013. StrathSat-R is the second experiment, which had the purpose of deploying two cube satellites with inflatable structures from the REXUS 13 sounding rocket, was launched first in May 2013 and will be launched a second time in spring 2014. The last experiment is the iSEDE experiment which has the goal of deploying an inflatable structure with disaggregated electronics from the high altitude balloon BEXUS15/16 in October 2013. All these experiments have been designed, built and flown in a timeframe of one and a half to two years. This paper will present the lessons learned in project management, outreach, experiment design, fabrication and manufacturing, software design and implementation, testing and validation as well as launch, flight and post-flight. Furthermore, the lessons learned during the recovery mission of Suaineadh will be discussed as well. All these experiments were designed, built and tested by a large group of university students of various disciplines and different nationalities. StrathSat-R and iSEDE were built completely at Strathclyde but the Suaineadh experiment was a joint project between Glasgow and Stockholm which was especially tricky during integration while approaching the experiment delivery deadline. This paper should help students and professionals across various disciplines to build and organise these kinds of projects more efficiently without making the same, sometimes expensive, mistakes all over again.

  • 542. Sinn, T.
    et al.
    McRobb, M.
    Wujek, Adam
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Skogby, Jerker
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Rogberg, Fredrik
    KTH, School of Electrical Engineering (EES).
    Wang, Junyi
    KTH, School of Electrical Engineering (EES).
    Vasile, M.
    Tibert, Gunnar
    KTH, School of Engineering Sciences (SCI), Mechanics, Structural Mechanics.
    Results of rexus12's suaineadh experiment: Deployment of a spinning space web in micro gravity conditions2012In: Proceedings of the International Astronautical Congress, IAC: Volume 2, 2012, International Astronautical Federation, 2012, p. 803-810Conference paper (Refereed)
    Abstract [en]

    On the 19th of March 2012, the Suaineadh experiment was launched onboard the sounding rocket REXUS12 (Rocket Experiments for University Students) from the Swedish launch base ESRANGE in Kiruna. The Suaineadh experiment served as a technology demonstrator for a space web deployed by a spinning assembly. The deployment of this web is a stepping stone for the development of ever larger structures in space. Such a structure could serve as a substructure for solar arrays, transmitters and/or antennas. The team was comprised of students from the University of Strathclyde (Glasgow, UK), the University of Glasgow (Glasgow, UK) and the Royal Institute of Technology (Stockholm, Sweden), designing, manufacturing and testing the experiment over the past 24 months. Following launch, the experiment was ejected from the ejection barrel located within the nosecone of the rocket. Centrifugal forces acting upon the space webs spinning assembly were used to stabilise the experiment's platform. A specifically designed spinning reaction wheel, with an active control method, was used. Once the experiment's motion was controlled, a 2 m by 2 m space web is released. Four daughter sections situated in the corners of the square web served as masses to stabilise the web due to the centrifugal forces acting on them. The four daughter sections contained inertial measurement units (IMUs). Each IMU provided acceleration and velocity measurements in all three directions. Through this, the positions of the four corners could be found through integration with respect to known time of the accelerations and rotations. Furthermore, four cameras mounted on the central hub section captured high resolution imagery of the deployment process. After the launch of REXUS12, the recovery helicopter was unable to locate the ejected experiment, but 22 pictures were received over the wireless connection between the experiment and the rocket. The last received picture was taken at the commencement of web deployment. Inspection of these pictures allowed the assumption that the experiment was fully functional after ejection, but perhaps through tumbling of either the experiment or the rocket, the wireless connection was interrupted. A recovery mission in the middle of August was only able to find the REXUS12 motor and the payload impact location.

  • 543.
    Sinn, Thomas
    et al.
    University of Strathclyde.
    McRobb, Malcolm
    University of Strathclyde.
    Wujek, Adam
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Skogby, Jerker
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Rogberg, Fredrik
    KTH, School of Electrical Engineering (EES).
    Wang, Junyi
    KTH, School of Electrical Engineering (EES).
    Vasile, Massimiliano
    University of Strathclyde.
    Tibert, Gunnar
    KTH, School of Engineering Sciences (SCI), Mechanics, Structural Mechanics.
    Lessons learned from REXUS12'S suaineadh experiment: Spinning deployment of a space Web in milli gravity2013In: 21st ESA Symposium: European Rocket & Balloon Programmes and Related Research / [ed] L. Ouwehand, ESA Communications , 2013, p. 329-338Conference paper (Refereed)
    Abstract [en]

    On the 19th of March 2012, the Suaineadh experiment was launched onboard the sounding rocket REXUS 12 (Rocket Experiments for University Students) from the Swedish launch base ESRANGE in Kiruna. The Suaineadh experiment served as a technology demonstrator for a space web deployed by a spinning assembly. Following launch, the experiment was ejected from the ejection barrel located within the nosecone of the rocket. Centrifugal forces acting upon the space web spinning assembly were used to stabilise the experiment's platform. A specifically designed spinning reaction wheel, with an active control method, was used. Once the experiment's motion was controlled, a 2 m by 2 m space web is released. Four daughter sections situated in the corners of the square web served as masses to stabilise the web due to the centrifugal forces acting on them. The four daughter sections contained inertial measurement units (IMUs). After the launch of REXUS 12, the recovery helicopter was unable to locate the ejected experiment, but 22 pictures were received over the wireless connection between the experiment and the rocket. The last received picture was taken at the commencement of web deployment. Inspection of these pictures allowed the assumption that the experiment was fully functional after ejection, but probably through tumbling of either the experiment or the rocket, the wireless connection was interrupted. A recovery mission in the middle of August was only able to find the REXUS 12 motor and the payload impact location.

  • 544.
    Sinn, Thomas
    et al.
    University of Strathclyde.
    McRobb, Malcolm
    University of Glasgow.
    Wujek, Adam
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Skogby, Jerker
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, Mengqi
    KTH, School of Engineering Sciences (SCI), Mechanics.
    Vasile, Massimiliano
    University of Strathclyde.
    Tibert, Gunnar
    KTH, School of Engineering Sciences (SCI), Mechanics, Structural Mechanics.
    Weppler, Johannes
    University of Stuttgart.
    Feeney, Andrew
    University of Glasgow.
    Russell, John
    University of Glasgow.
    Rogberg, Fredrik
    KTH, School of Electrical Engineering (EES).
    Wang, Junyi
    KTH, School of Electrical Engineering (EES).
    REXUS 12 Suaineadh experiment: deployment of a web in microgravity conditions using centrifugal forces2011In: IAC 2011: Proceedings of the 62nd International Astronautical Congress, 2011, p. IAC-11-A2.3.7-Conference paper (Refereed)
  • 545.
    Solsona Belenguer, Jordi
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Topics in engineering methods for IT: Moving towards an interdisciplinary design space2014Licentiate thesis, comprehensive summary (Other academic)
  • 546. Soudris, D.
    et al.
    Jantsch, AxelKTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Scalable multi-core architectures: Design methodologies and tools2012Collection (editor) (Other academic)
    Abstract [en]

    As Moore's law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallelization of the computation and 3D integration technologies lead to distributed memory architectures. This book describes recent research that addresses urgent challenges in many-core architectures and application mapping. It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies.

  • 547. Su, Hai
    et al.
    Qiu, Meikang
    Chen, Huimin
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Qin, Xiao
    Jamming-Resilient Multi-Radio Multi-Channel Multihop Wireless Network for Smart Grid2011In: In Proceedings of the 7th ACM Annual Cyber Security and Information Intelligence Research Workshop (CSIIR’11), 2011Conference paper (Refereed)
  • 548. Sun, X.
    et al.
    Dai, W.
    Yan, W.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Gao, H.
    Analytical electro-thermal model for RF-LDMOSFET2010In: Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics, ISSN 1000-3819, Vol. 30, no 3, p. 370-376+424Article in journal (Refereed)
    Abstract [en]

    This paper presents the model development of Agere eletro-thermal transistor, an electro-thermal large signal nonlinear RF-LDMOSFET model used in radio frequency (RF) power amplifiers (PAs). We first describe our model schematics, then the iso-thermal and pulsed device characterization systems used in the parametrization of the model are described. The extracted model is implemented in Agilent's Advanced Design System (ADS) for the development of several PAs. Finally, the model accuracy is measured by comparing several experimental verifications of physical chips against those of EDA designs.

  • 549. Sun, Yi-Ran
    et al.
    Kumar, Shashi
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Simulation and Evaluation of a Network on Chip Architecture Using Ns-22002In: Proceedings of the IEEE NorChip Conference, 2002Conference paper (Refereed)
  • 550.
    Tajammul, Muhammad Adeel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jafri, Syed Mohammad Asad Hassan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Private configuration environments (PCE) for efficient reconfiguration, in CGRAs2013In: Proceedings Of The 2013 IEEE 24th International Conference On Application-Specific Systems, Architectures And Processors (ASAP 13), IEEE Computer Society, 2013, p. 227-236Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a polymorphic configuration architecture, that can be tailored to efficiently support reconfiguration needs of the applications at runtime. Today, CGRAs host multiple applications, running simultaneously on a single platform. Novel CGRAs allow each application to exploit late binding and time sharing for enhancing the power and area efficiency. These features require frequent reconfigurations, making reconfiguration time a bottleneck for time critical applications. Existing solutions to this problem either employ powerful configuration architectures or hide configuration latency (using configuration caching). However, both these methods incur significant costs when designed for worst-case reconfiguration needs. As an alternative to worst-case dedicated configuration mechanism, we exploit reconfiguration to provide each application its private configuration environment (PCE). PCE relies on a morphable configuration infrastructure, a distributed memory sub-system, and a set of PCE controllers. The PCE controllers customize the morphable configuration infrastructure and reserve portion of the a distributed memory sub-system, to act as a context memory for each application, separately. Thereby, each application enjoys its own configuration environment which is optimal in terms of configuration speed, memory requirements and energy. Simulation results using representative applications (WLAN and Matrix Multiplication) showed that PCE offers up to 58 % reduction in memory requirements, compared to dedicated, worst case configuration architecture. Synthesis results show that the morphable reconfiguration architecture incurs negligible overheads (3 % area and 4 % power compared of a single processing element).

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