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• 451.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Mobile and Wide Area Deployable Sensor System for Networked Services2009In: 2009 IEEE SENSORS: VOLS 1-3, NEW YORK: IEEE , 2009, p. 1329-1332Conference paper (Refereed)

A mobile and wide area deployable wireless sensor system, including hardware and software, is developed to enhance the mobility, deployment and capability of wireless sensors for networked services. Due to the dual-layer dual-directional wireless communication capability of a novel WAN-SAN coherent architecture and the removal of fix-installed gateway, all sensor nodes are remotely controllable and seamlessly integrated to internet services. Hardware modules are optimized for ultra low power and compact size. Abstract and extendable application interface is developed, based on SMS and TCP/UDP protocol, to be integrated easily into existing service systems. Hierarchical CPS-LPS Adaptive Localization, is supported based on CPS, wireless cellular ID, RFID, IR-UWB and inertial prediction. Specific data compression technique is adopted for high density data source. Finally, Fresh Food Tracking service is presented as an application example, including some field test data.

• 452.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Global Fresh Food Tracking Service Enabled by Wide Area Wireless Sensor Network2010In: 2010 IEEE Sensors Applications Symposium, SAS 2010, IEEE Sensors Council, 2010, p. 6-9Conference paper (Refereed)

A global fresh food tracking service is presented, in which a set of primary environmental conditions for transport of fresh fruits and vegetables, including global position, temperature, relative humidity, concentrations of CO2, O2 and ethylene gases and 3-axis acceleration, is collected through mobile and remotely controllable wireless sensor nodes. Real time monitoring, tracking, alarming, close-loop controlling and information sharing could therefore be provided as WEB services with service oriented architecture. Fully functioned hardware modules, protocols and system software have been developed. A 50-day field test has been successfully carried out, proving the system concept and the robustness of hardware and software designed. Due to its worldwide deploy-ability and added-values to fresh food supply chain, it is feasible to establish a practical fresh food tracking service business.

• 453.
ABB Corporate Research.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Ecosystem analysis in the design of open platform-based in-home healthcare terminals towards the internet-of-things2013In: International Conference on Advanced Communication Technology, ICACT, ISSN 1738-9445, p. 529-534Article in journal (Refereed)

In-home healthcare services based on the Internet-of-Things (IoT) have big potential in business. To exploit this opportunity, an ecosystem should be established first. Technical solutions should aim for a cooperative ecosystem by addressing the interoperability, security, and system integration. In this paper, we propose an ecosystem-driven design strategy and apply it in the design of an open-platform based solution. In particular, a cooperative ecosystem is formulated by merging the traditional healthcare and mobile internet ecosystems. Utilizing the existing standardization efforts, the interfaces between actors can be simplified. To balance the control and avoid monopoly, ecosystem-driven security schemes are proposed including the public-based authentication, repository-based credential management, SE-based cryptography, and non-invasive message handover. In order to achieve the economy of scale, an open platform-based in-home healthcare station is proposed. The proposed methodology and solution are demonstrated in implemented prototype system and field trials.

• 454.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
A Global Fresh Food Tracking Service Based on Novel Wireless Sensor and RFID Technologies2009Conference paper (Refereed)

A global fresh food tracking service is presented, in which a set of real-time primary environmental conditions for transport of fresh fruits and vegetables, including global position, temperature, relative humidity, concentrations of CO2, O2 and ethylene gases and 3-axis acceleration, is collected through mobile and remotely controllable wireless sensor nodes. Real time monitoring, tracking, alarming, close-loop controlling and information sharing could therefore be provided as WEB services with service oriental architecture. Fully functioned hardware modules, protocols and system software have been developed. A 50-day field test has been successfully carried out, proving the system concept and the robustness of hardware and software designed. Due to its worldwide deploy-ability and added-values to fresh food supply chain, it is now feasible to establish a practical fresh food tracking service business.

• 455.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A Pervasive and Preventive Healthcare Solution for Medication Noncompliance and Daily Monitoring2009In: 2009 2ND INTERNATIONAL SYMPOSIUM ON APPLIED SCIENCES IN BIOMEDICAL AND COMMUNICATION TECHNOLOGIES (ISABEL 2009), NEW YORK: IEEE , 2009, p. 315-320Conference paper (Refereed)

Pervasive healthcare solution for medication noncompliance problem would help to save \$177 billion annually in the United States. And the rapidly increasing demanding of daily monitoring with onsite diagnosis and prognosis is driving homecare solutions to integrate more and more sensing and data processing capacities. So a powerful system is needed not only to address the medication noncompliance but also to be used as a Pervasive Healthcare Station in home. In this paper, a pervasive and preventive healthcare solution for medication noncompliance and daily monitoring is proposed using an intelligent package sealed by Controlled Delamination Material (CDM) and controlled by Radio Frequency Identification (RFID). Onsite diagnosis and prognosis capacities for kinds of health parameters are supported due to scalable and intensive computing capacitance of the 2D-Mesh-NoC based multi-core architecture. Additionally, friendly human-machine interface is emphasized to make it usable for the elderly, disabled and patients due to enhanced multimedia performance. Experimental results of an implemented prototype confirmed the necessity of the multi-core architecture and approved the feasibility of the proposed intelligent package.

• 456.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Content-extraction-based compression of acceleration data for mobile wireless sensors2012In: Sensors, 2012 IEEE, IEEE , 2012, p. 1244-1247Conference paper (Refereed)

A content-extraction based acceleration data compression algorithm is proposed for real-time transport quality monitoring in critical logistics applications. It splits the original data into three components, Tilt, Shock and Vibration, and compresses them separately by making use of the specific characteristics. Outstanding performances as well as low complexity and good scalability are achieved, which are essential for resource-constrained mobile wireless sensors. The algorithm has been proven by 46-day field test data. The compression ratio is up to 3.75 in loss-less mode, and up to 142 in lossy mode with 28.9dB SNR.

• 457.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Scenario-based Design of Wireless Sensor System for Food Chain Visibility and Safety2011In: 2011 International Conference on Computer, Communication, Control and Automation, 3CA 2011, Springer Publishing Company, 2011, p. 541-548Conference paper (Refereed)

Food chain visibility and safety problems have caused huge loss of money and threat to public food safety. The blooming Wireless Sensor Network (WSN) technology has been highlighted as a promising solution to resolve these problems. Because nowadays food chains has become highly distributed, heterogeneous, cooperative, and globalized, a comprehensive system-picture is needed in design practices to meet the extremely diverse requirements. In this paper, a universal WSN platform is designed for food chain monitoring applications based on a scenario-based method. It classifies the complicated real food chains into five typical scenarios (Produce, Store, Transport, Sell, and Consume). All scenarios are supported by convergence of all the necessary technical requirements. And corresponding operation models, networking protocols, hardware, and software are implemented. Comparing to existing researches, this paper provides a more comprehensive system-picture and its technical feasibility is approved by practical implementation as well as field experiments.

• 458.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
An in-home medication management solution based on intelligent packaging and ubiquitous sensing2013In: Int. Conf. Adv. Commun. Technol. ICACT, 2013, p. 545-550Conference paper (Refereed)

A healthcare solution for medication noncompliance problem would help to save 177 billion annually in the United States. In addition, an in-home healthcare station (IHHS) is needed to meet the rapidly increasing demands for daily monitoring with on-site diagnosis and prognosis. In this paper, an intelligent medication management system is proposed based on intelligent package and ubiquitous sensing technologies. Preventive medication management is enabled by an intelligent package sealed by Controlled Delamination Material (CDM) and controlled by RFID link. Various vital parameters are collected by wearable biomedical sensors through the short range wireless link. Onsite diagnosis and prognosis based on these health parameters are supported by the scalable architecture. Additionally, friendly human-machine interface is emphasized to make it convenient for the elderly or disabled patients. A prototype system including the hardware, embedded software, user interface, database and some intelligent packages is implemented to verify the concepts.

• 459.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Corporate Research, ABB AB.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan University. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. School of Information Science and Technology, Fudan University, No. 220.
Value-Centric Design of the Internet-of-Things Solution for Food Supply Chain: Value Creation, Sensor Portfolio and Information Fusion2013In: Information Systems Frontiers, ISSN 1387-3326, E-ISSN 1572-9419, Vol. 17, no 2, p. 289-319Article in journal (Refereed)

The revolution of Internet-of-Things (IoT) is reshaping the modern food supply chains with promising business prospects. To be successful in practice, the IoT solutions should create “income-centric” values beyond the conventional “traceability-centric” values. To accomplish what we promised to users, sensor portfolios and information fusion must correspond to the new requirements introduced by this income-centric value creation. In this paper, we propose a value-centric business-technology joint design framework. Based on it the income-centric added-values including shelf life prediction, sales premium, precision agriculture, and reduction of assurance cost are identified and assessed. Then corresponding sensor portfolios are developed and implemented. Three-tier information fusion architecture is proposed as well as examples about acceleration data processing, self-learning shelf life prediction and real-time supply chain re-planning. The feasibilities of the proposed design framework and solution have been confirmed by the field trials and an implemented prototype system.

• 460.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
An RTOS-based Architecture for Industrial Wireless Sensor Network Stacks with Multi-Processor Support2013In: Proceedings ICIT 2013 - 2013 IEEE International Conference on Industrial Technology (ICIT), 2013, p. 1216-1221Conference paper (Refereed)

The design of industrial wireless sensor network (IWSN) stacks requires the adoption of real time operation system (RTOS). Challenges exist especially in timing integrity and multi-processor support. As a solution, we propose an RTOS-based architecture for IWSN stacks with multi-processor support. It offers benefits in terms of platform independency, product life cycle, safety and security, system integration complexity, and performance scalability. An implemented WirelessHART stack has proven the feasibility of the proposed architecture in practical product design. And future challenges as well as suggestions to standard improvement are discussed.

• 461.
ABB Corporate Research, Sweden.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Design of a terminal solution for integration of in-home health care devices and services towards the Internet-of-Things2015In: Enterprise Information Systems, ISSN 1751-7575, E-ISSN 1751-7583, Vol. 9, no 1, p. 86-116Article in journal (Refereed)

In-home health care services based on the Internet-of-Things are promising to resolve the challenges caused by the ageing of population. But the existing research is rather scattered and shows lack of interoperability. In this article, a business-technology co-design methodology is proposed for cross-boundary integration of in-home health care devices and services. In this framework, three key elements of a solution (business model, device and service integration architecture and information system integration architecture) are organically integrated and aligned. In particular, a cooperative Health-IoT ecosystem is formulated, and information systems of all stakeholders are integrated in a cooperative health cloud as well as extended to patients' home through the in-home health care station (IHHS). Design principles of the IHHS includes the reuse of 3C platform, certification of the Health Extension, interoperability and extendibility, convenient and trusted software distribution, standardised and secured electrical health care record handling, effective service composition and efficient data fusion. These principles are applied to the design of an IHHS solution called iMedBox. Detailed device and service integration architecture and hardware and software architecture are presented and verified by an implemented prototype. The quantitative performance analysis and field trials have confirmed the feasibility of the proposed design methodology and solution.

• 462.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A System-Level Framework for Energy and Performance Estimation in System-on-Chip Architectures2011Doctoral thesis, monograph (Other academic)

Shifting the design entry point up to the system level is the most important countermeasure adopted to manage the increasing complexity of SoCs. The reason is that decisions taken at this level, early in the design cycle, have the greatest impact on the final design in terms of performance, energy efficiency and silicon area occupation. However, taking decisions at this level is very difficult, since the design space is extremely wide, and it has so far been mostly a manual activity. Efficient system-level estimation tools are therefore necessary to enable proper design-space exploration and the development of system-level synthesis tools.

Proposing an efficient approach to system-level estimation is the main contribution of this thesis.

The approach consists of three layers. The bottom layer relies on building a library of IP energy and performance models, where each IP functionality is pre-characterized. Characterization is done only once at the gate level, which gives high accuracy to the approach. The implementation of an energy and performance model for a Leon3 processor is reported as an example. The impact that the IP-to-IP communication infrastructure has over individual IP properties is also taken into account, for bus-based and NoC-based architectures.

The intermediate layer is where the actual estimation takes place. At this level, applications are run and profiled on a development host (a common PC). This allows us to create a trace of the executed source code, which is then mapped to the assembly code of the target architecture. This operation allows a trace of target instructions to be indirectly built and confers high speed on the whole methodology. Once the target trace is inferred, energy and performance figures can be extracted by using the IP models from the bottom layer. To make the whole process possible, changes are made to the GNU GCC compiler. Estimation is shown for a few common image/video codec applications.

The top layer is a refinement layer that accounts for the presence of caches and for the fact that multiple applications normally run concurrently, share the same resources and are controlled by an operating system. Statistical models are built to account for the impact of each of these components. An MPSoC hosting up to 15 processors and using both fixed-priority and round robin bus arbitration is used for modeling bus contention. The RTEMS operating system is taken as a reference to model the OS impact.

Validation for each layer is also carried out. The results show that the approach is within 15% of gate-level accuracy and exhibits an average speed-up of $\sim$30X compared to transaction-level modeling (TLM).

• 463.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A Step Beyond TLM: Inferring Architectural Transactions at Functional Untimed Level2008In: IFIP/IEEE VLSI-SoC 2008 International Conference: 16th International Conference on Very Large Scale Integration, 2008, p. 505-509Conference paper (Other academic)
• 464.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A layered approach to estimating power consumption2006In: 24th Norchip Conference, Proceedings / [ed] Johansson, T, IEEE , 2006, p. 93-98Conference paper (Refereed)

A layered approach to estimating power consumption at the highest level of abstraction is presented. This approach is sufficiently accurate and fast enough to be used as guide for exploring the algorithmic and architectural space. The layers span from use-case level down to gate level. Speed and accuracy come from our ability to relate parameterized transactions at architectural level to switching activity at gate level and to perform architecturally-aware application-level simulation for specific or sweeps of use-cases. That enables us to recreate accurately architectural-level transactions. Additionally, we use preliminary floorplan to factor physical design aspects to improve the accuracy of our estimates. We base our work on the industry standard SPIRIT for specifying IPs and Platforms. Early results of work are also presented.

• 465.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Modelling Embedded Systems at Functional Untimed Application Level2007In: IP Conference (IP’07), 2007, p. 107-112Conference paper (Other academic)
• 466.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A general approach to high-level energy and performance estimation in system-on-chip architectures2009In: Journal of Low Power Electronics, ISSN 1546-1998, Vol. 5, no 3, p. 373-384Article in journal (Refereed)

We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs. Differently from the most common approaches, which rely on Transaction-Level Modeling (TLM), we infer energy and performance figures directly from the Functional Untimed Level, by running the algorithmic specification natively on a common host machine. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 17% of gate-level accuracy and in average 28x faster than TLM-PV, for the benchmark applications selected.

• 467.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Inferring energy and performance cost of RTOS in priority-driven scheduling2010In: 5th International Symposium on Industrial Embedded Systems, SIES 2010, 2010, p. 1-8Conference paper (Other academic)
• 468.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Predicting bus contention effects on energy and performance in multi-processor SoCs2011In: 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, 2011, p. 1196-1199Conference paper (Other academic)
• 469.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Predicting energy and performance overhead of Real-Time Operating Systems2010In: Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, 2010, p. 15-20Conference paper (Other academic)
• 470. Phong, N. D. B.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland . KTH, School of Information and Communication Technology (ICT), Electronic Systems. University of Turku, Finland .
Silicon synapse designs for VLSI neuromorphic platform2014In: NORCHIP 2014 - 32nd NORCHIP Conference: The Nordic Microelectronics Event, IEEE , 2014, p. 7004745-Conference paper (Refereed)

Analog silicon neurons were proven to be a promising solution for VLSI neuromorphic platform to implement massively scalable computing systems. They possess the advantages of consuming less power and silicon area than digitally designed neurons. This paper compares the differences in power and area consumption between two methods of synapse design for analog neuron models: time-based modulation and current-based modulation. The obtained results demonstrate that under the same technology process (ST CMOS 65nm), the neuron that uses time-based modulation consumes less power (almost six times) and silicon area (about thirty times) but higher energy (twelve times) than that of the current-based modulation.

• 471. Postolache, O.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
IEEE 1451.4 embedded smart sensors architecture for wheelchair user monitoring2012In: MeMeA 2012 - 2012 IEEE Symposium on Medical Measurements and Applications, Proceedings, IEEE , 2012, p. 15-19Conference paper (Refereed)

The design and implementation of a microcontroller based platform compatible with IEEE 1451.4 standard for high performance unobtrusive accurate cardio-respiratory and motor activity estimation of wheelchair users are presented in this paper. The platform is a multi-sensor architecture that includes sensors with plug-and-play and auto-identification capabilities, a RFID reader that is used to identify the wheelchair user, and RFID tags mounted in critical regions of the indoor habitat. The acquired data from the smart sensor channels are delivered through Bluetooth communication or wired serial communication to a host computer that includes a server application associated with IEEE 1451.4 TEDS management and display of the measured data. Elements of human-machine-interface (HMI) implementation and several experimental results are included in the paper.

• 472. Qian, Yue
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
QoS Scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin2010In: 2010 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2010, p. 52-59Conference paper (Refereed)

Strict Priority Queueing (SPQ) and Weighted Round Robin (WRR) are two common scheduling techniques to achieve Quality-of-Service (QoS) while using shared resources. Based on network calculus, we build analytical models for traffic flows under SPQ and WRR scheduling in on-chip wormhole networks. With these models, we can derive per-flow end-to-end delay bound. We compare the service behavior and show that WRR is not only more fair but also more flexible for QoS provision. To exhibit the potential and flexibility enabled by WRR, we develop a weight allocation algorithm to automatically assign proper weights for individual flows to satisfy their delay constraints. In particular, the weights are assigned in a way not more than necessary, in other words, to approach flows' delay constraints in order to leave room for other flows. Our experimental results validate our analysis technique and algorithms.

• 473. Qian, Yue
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks2010In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 29, no 5, p. 802-815Article in journal (Refereed)

In network-on-chip (NoC), computing worst-case delay bounds for packet delivery is crucial for designing predictable systems but yet an intractable problem. This paper presents an analysis technique to derive per-flow communication delay bound. Based on a network contention model, this technique, which is topology independent, employs network calculus to first compute the equivalent service curve for an individual flow and then calculate its packet delay bound. To exemplify this method, this paper also presents the derivation of a closed-form formula to compute a flow's delay bound under all-to-one gather communication. Experimental results demonstrate that the theoretical bounds are correct and tight.

• 474. Qiu, Meikang
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors2012In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 58, no 10, p. 439-445Article in journal (Refereed)

Energy consumption has been one of the most critical issues in the Chip Multiprocessor (CMP). Using the Dynamic Voltage and Frequency Scaling (DVFS), a CMP system can achieve a balance between the performance and the energy-efficiency. In this paper, we propose a three-phase discrete DVFS algorithm for a CMP system dedicated to applications where the period of the applications' task graph is smaller than the deadline of tasks. In these applications, multiple task graphs are unrolled and then concatenated together to form a new task graph. The proposed DVFS algorithm is applied to the newly formed task graph to stretch tasks' execution time, lower operating frequencies of processors and achieve the system power efficiency. Experimental results show that the proposed algorithm reduces the energy dissipation by 25% on average, compared to previous DVFS approaches.

• 475. Radetzki, Martin
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Methods for Fault Tolerance in Networks-on-Chip2013In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341, Vol. 46, no 1, p. 8-Article in journal (Refereed)

Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.

• 476. Radetzki, Martin
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Special issue on languages, models and model based design for embedded systems Introduction2014In: Design automation for embedded systems, ISSN 0929-5585, E-ISSN 1572-8080, Vol. 18, no 1-2, p. 61-62Article in journal (Other academic)
• 477.
MICAS-ESAT, Katholieke Univ. Leuven.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. MICAS-ESAT, Katholieke Univ. Leuven. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. MICAS-ESAT, Katholieke Univ. Leuven.
Far-field RF powering system for RFID and implantable devices with monolithically integrated on-chip antenna2010In: 2010 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS RFIC SYMPOSIUM, 2010, p. 113-116Conference paper (Refereed)

A fully integrated far-field powering system for RFID and implantable devices with monolithically fully integrated on-chip antenna in 0.18ÎŒm CMOS is presented. The chip receives power, clock and data wirelessly through RF signal at all the three ISM bands of 915 MHz, 2.45 GHz and 5.8 GHz. Measurements show a minimum input power of -19.41 dBm at 900MHz for chip operation, corresponding to 15.7 meter of operation range with an off-chip 0dB gain antenna. On the other hand, with its on-chip antenna at 5.8 GHz, the chip can be powered-up up to 7.5 cm distance. This is a huge improvement in terms of operation distance compared with other reported similar works with on-chip antenna as well as the off-chip antennas.

• 478. Radiom, Soheil
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-mu m Standard CMOS2010In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 45, no 9, p. 1746-1758Article in journal (Refereed)

• 479. Radiom, Soheil
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Miniaturization of UWB Antennas and its Influence on Antenna-Transceiver Performance in Impulse-UWB Communication2013In: Wireless personal communications, ISSN 0929-6212, E-ISSN 1572-834X, Vol. 71, no 4, p. 2913-2935Article in journal (Refereed)

In this paper, a co-design methodology and the effect of antenna miniaturization in an impulse UWB system/transceiver is presented. Modified small-size printed tapered monopole antennas (PTMA) are designed in different scaling sizes. In order to evaluate the performance and functionality of these antennas, the effect of each antenna is studied in a given impulse UWB system. The UWB system includes an impulse UWB transmitter and two kinds of UWB receivers are considered, one based on correlation detection and one on energy detection schemes. A tunable low-power Impulse UWB transmitter is designed and the benefit of co-designing it with the PTMA antenna is investigated for the 3.1-10.6 GHz band. A comparison is given between a 50 design and a co-designed version. Our antenna/transceiver co-design methodology shows improvement in both transmitter efficiency and whole system performance. The simulation results show that the PTMA antenna and its miniaturized geometries are suitable for UWB applications.

• 480. Radiom, Soheil
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Antenna Miniaturization Influence on the Performance of Impulse Radio UWB system2008In: Proceedings of the 1st European Wireless Technology Conference, EuWiT 2008, NEW YORK: IEEE , 2008, p. 362-365Conference paper (Other academic)

In this paper the effect of antenna miniaturization in a UWB system is presented. Modified small-size printed tapered monopole antennas are designed in different scaling sizes. In order to evaluate the antennas performance and their functionality, the performance of three kinds of UWB systems, Correlation Detection, Energy Detection and Transmitted Reference UWB, is studied in the presence of each antenna in the AWGN channel. The simulation results show that our designed antenna and its miniaturized geometries are suitable for UWB applications.

• 481. Rahmani, A. M.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Power-Aware Architecture for 3D Networks-on-Chip2011In: Work in Progress Session of the Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (WiP-PDP’11) / [ed] Grosspietsch, Erwin and Kloeckner, Konrad, 2011, p. 15-16Conference paper (Refereed)
• 482.
Turku Centre for Computer Science (TUCS).
Turku Centre for Computer Science (TUCS). Turku Centre for Computer Science (TUCS). Turku Centre for Computer Science (TUCS). Turku Centre for Computer Science (TUCS). KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Low-Cost Monitoring Platform for 3D Networks-on-Chip2012In: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (WiP-PDP'12), 2012, p. 19-20Conference paper (Refereed)
• 483.
Turku Centre for Computer Science (TUCS).
Turku Centre for Computer Science (TUCS). Turku Centre for Computer Science (TUCS). KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
High-Performance, Power-Aware and Reliable 3D NoC Architectures2012In: Ph.D. Forum Booklet of IEEE/ACM International Asia and South Pacific Design Automation Conference (ASP-DAC’12), 2012, p. 23-24Conference paper (Refereed)
• 484. Rahmani, Amir-Mohammad
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Special section on advances in methods for adaptive multicore systems2014In: Journal of Supercomputing, ISSN 0920-8542, E-ISSN 1573-0484, Vol. 68, no 3, p. 1023-1026Article in journal (Refereed)
• 485. Rahmati, Dara
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Power-efficient deterministic and adaptive routing in torus networks-on-chip2012In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 36, no 7, p. 571-585Article in journal (Refereed)

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual channels is important since it has a direct effect on the power consumption of NoCs. In this paper, we propose a novel systematic approach for designing deadlock-free routing algorithms for torus NoCs. Using this method a new deterministic routing algorithm (called TRANC) is proposed that uses only one virtual channel per physical channel in torus NoCs. We also propose an algorithmic mapping that enables extracting TRANC-based routing algorithms from existing routing algorithms, which can be both deterministic and adaptive. The simulation results show power consumption and performance improvements when using the proposed algorithms.

• 486. Rashed, M.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Power characteristics of Asynchronous Networks-on-Chip2011In: Int. Syst. Chip Conf., 2011, p. 160-165Conference paper (Refereed)

Power characteristics of different Asynchronous Network on Chip (NoC) architectures are developed. Among different NoC architectures, the Butterfly Fat Tree (BFT) dissipates the minimum power. With increasing the number of IP blocks, the relative power consumption of the interconnects and the associate repeaters of the Asynchronous NoC architecture decreases as compared to the power consumption of the network switches. The power dissipation of the Asynchronous architecture is decreased by up to 57% as compared to the power dissipation of the conventional Synchronous architecture. The BFT is more efficient with increasing the number of IP blocks.

• 487.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Measurement of mass of single inkjet drops with a quartz crystal microbalance QCM2012In: Int. Conf. Digit. Print. Technol., The Society for Imaging Science and Technology, 2012, p. 312-314Conference paper (Refereed)

Monitoring inkjet performance requires control of parameters such as drop velocity, direction and drop volume. Present methods to determine drop volume utilize optical vision systems or calculation of an average drop mass from large numbers of drops on a precision balance. An alternative technique based on QCM (Quartz Crystal Microbalance) was assessed to measure the mass of single drops. Low-cost plano-convex 6 MHz AT-cut quartz resonators were used to measure single inkjet drops. Since the footprint of these ink drops is of the order 100 μm the QCM detector was used in a 'localized spot' measurement mode in contrast to the typical large area detection mode. The sensitivity of an inner 0.5 mm circle was determined to be 5.46 x 10-10 g/Hz for solid silver films. Single drops of an oil-based ink of 50 pL nominal volume were jetted using a Xaar126 piezo inkjet printhead onto the QCM target area and produced signals with a SNR better than 70:1. This paper presents the technical challenges relating to liquid droplet volume measurements using higher frequency oscillators.

• 488.
KTH. XaarJet AB, Sweden .
XaarJet AB, Sweden . KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics. XaarJet AB, Sweden . KTH, School of Information and Communication Technology (ICT), Electronic Systems. XaarJet AB, Sweden .
Electrical through-hole and planar interconnect generation in roll-to-roll LED lighting manufacturing using industrial inkjet printheads2011In: Mater Res Soc Symp Proc, 2011, p. 1-6Conference paper (Refereed)

Despite the availability of many high-volume and low-cost manufacturing processes for LED-based lighting applications, relying mainly on fixed patterns such as LED-backlights and RGB-pixelated displays, novel applications, such as "mood lighting" or interior wall displays call for more complicated and shaped LED arrangements. The presented work is based of a novel roll-to-roll (R2R) process to adaptively and cost-efficiently generate LED arrangements on RMPD® substrates. Inkjet printing of planar and though-hole electrical interconnections is of high importance to the process, as it provides a fully digital way of interconnecting devices electrically, accounting for the actual position of the component and spatially provide different ink film thicknesses. Xaar's industrial inkjet printheads are used to dispense defined volumes of 50 pL of a silver nanoparticle ink in order to provide high reliability and good positioning accuracy while maintaining low satellite drop densities. Specific printing strategies are investigated at a print speed of 0.1 m/s to allow for a reliable electrical connection in case of up to 50 μm deep via connections to the buried component. Due to the low glass-transition nature of the underlying substrates, low sintering temperatures are required to preserve the mechanical properties of the substrate. Low temperature oven sintering yielding sufficient conductivity to drive a current of 40 mA will be discussed.

• 489.
KTH. XaarJet AB, Sweden.
KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics. XaarJet AB, Sweden. KTH, School of Information and Communication Technology (ICT), Electronic Systems. XaarJet AB, Sweden.
Inkjet printing of electrical vias2011In: EMPC - Eur. Microelectron. Packag. Conf., Proc., 2011Conference paper (Refereed)

Inkjet printing of planar and via (through-hole) electrical interconnections is developed to be incorporated into a roll-to-roll manufacturing line. The specific roll-to-roll machine uses rotary RMPD® technology, self-alignment of bare LED dies, and inkjet printing of the electrical connections to the LEDs dies. The key problem to be solved is the inkjet printing of electrical connections through via holes with vertical walls Xaar126-50pL industrial inkjet printheads were used to print silver nano particle ink at 0.1 m/s to connect through LED vias of 90 μm diameter and up to 50 μm depth. While high throughput sintering techniques are desirable for the specific roll-to-roll machine standard convection oven sintering was applied for the proof of principle described here. Sintering at temperatures as low as 135 °C for 30 min prevented damage to the substrate and LED dies and yielded electrical connections that allowed to drive LEDs with 20 mA at 3V under emission of bright green light.

• 490.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Novel developments in photonic sintering of inkjet printed functional inks2013In: NIP29: Digital fabrication 2013, 29th international conference on digital printing technologies, September 29-October 3, 2013, Seattle, Washington : technical program and proceedings, The Society for Imaging Science and Technology, 2013, p. 476-478Conference paper (Refereed)

Inkjet printing of electrical tracks in roll-to-roll applications was hampered for a long time since nano-particle inks required thermal sintering at temperatures greater than 120 °C for several minutes. Among a large number of potential R2R compatible techniques, photonic sintering of inkjet-printed metal-based inks was shown to enable very fast sintering times and providing high quality of structural integrity and low electrical resistance [1]. While the above investigations were carried out with a low dutylow frequency irradiation source, novel developments allow for pulse shaping on the timescale of several microseconds and, therefore, the combination of drying and sintering pulses into a single piece of equipment. In this contribution the photonic sintering process was investigated numerically and experimentally for the case of inkjetprinted aqueous copper oxide ink and a Pulse Forge®3200 X2 tool, both implemented onto a NovaCentrix roll-to-roll machine. Our finding support the assumption, that pulse shaping and, therefore, energy tailoring as a function of time, is essential for efficient conversion of wet copper oxide deposits into conductive copper with no impact on the underlying substrate. The paper presents and discusses the resulting electrical resistances of features processed with a conventional hybrid solution using IRradiation for pre-drying as well as a single step drying and sintering using a single radiation source.

• 491. Rezaei, A.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku (UTU), Finland . KTH, School of Information and Communication Technology (ICT), Electronic Systems.
HiWA: A hierarchical Wireless Network-on-Chip architecture2014In: Proceedings of the 2014 International Conference on High Performance Computing and Simulation, HPCS 2014, 2014, p. 499-505Conference paper (Refereed)

Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged. Employing wireless communication links between cores, the new technology has reasonably increased the performance of NoC. However, wireless transceivers along with associated antenna impose considerable area and power overheads in WNoCs. Thus, in this paper, we introduce a hierarchical WNoC called Hierarchical Wireless-based Architecture (HiWA) to use the wireless resources optimally. In the proposed approach the network is divided into subnets where intra-subnet nodes communicate through wire links while inter-subnet communications are almost handled by single-hop wireless links. On top of that, we have also defined performance evaluation parameters. Simulation results show that the proposed architecture reduces average packet latency 16% and power consumption 14% in comparison with its conventional counterparts.

• 492.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA2014Licentiate thesis, comprehensive summary (Other academic)

Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA.

• 493.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
From Simulink to NoC-based MPSoC on FPGA2014In: Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, IEEE , 2014Conference paper (Refereed)

Network-on-chip (NoC) based multi-processor systems are promising candidates for future embedded system platforms. However, because of their complexity, new high level modeling techniques are needed to design, simulate and synthesize embedded systems targeting NoC-based MPSoC. Simulink is a popular modeling environment suitable to model at system level. However, there is no clear standard to synthesize Simulink models into SW and HW towards a NoC-based MPSoC implementation. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In this paper we present a novel design flow to synthesize Simulink models onto a NoC-based MPSoC running on low-cost FPGAs. Our design flow constrains the MPSoC and the Simulink model to share a common semantics domain. This permits to reduce the need of resource consuming SW components, reducing the memory requirements on the platform. At the same time, performances (throughput) of dataflow applications can increase when the number of processors of the target platform is increased. This is shown through a case study on FPGA.

• 494.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA2013In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, IEEE , 2013, p. 6581536-Conference paper (Refereed)

Future embedded systems will make use of many hundred, configurable or re-configurable, processing elements communicating through a network on chip (NoC), but there is lack of rapid automated design flows bridging the abstraction gap between the models of such systems and their implementation.

• 495.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
All Digital Polar Transmitter Design for Software Defined Radio: Architecture and Low Power Circuit Implementation2012Doctoral thesis, comprehensive summary (Other academic)

The evolving wireless communication technology is aiming highdata rate, high mobility, long distance and at the meantime, co-existwith various different standards. This developing trend requires ahighly linear transceiver system and it causes the problem of lowefficiency due to the large crest factor of signals. On the other hand,with process scaling, digital blocks are occupying more functions andchip area than before, to fully utilize the digital process low poweradvantage and save design cost, hardware reuse is preferable. Theconcept of Software Defined Radio (SDR) is raised to make thesystem more adaptable to multiple communication standards withminimal hardware resources.

In this doctoral dissertation work, the software defined radioarchitecture especially the all-digital polar transmitter architecture isexplored. System level comparison on different transmitter topologiesis carried out in the first place. Direct conversion, out-phasing andpolar transmitter topologies are compared. Based on the system levelevaluation, a Lowpass Sigma Delta Modulation (LPSDM) digitalpolar transmitter is designed under 90nm CMOS process andpackaged in QFN32. 19.3% peak efficiency and 11.4dBm outputpower is measured under single 1.0V supply. The constellationmeasurement achieved 5.08% for 3pi/8PSK modulation and 7.01%for QAM16 modulation output. The measurement on the packagedtransmitter AM/AM and AM/PM also demonstrated the linearity andpower efficiency performance under low voltage environment. This verified the possibility for a fully SDR solution in the future.

As a specific application and genuine creation, the UHF RFIDstandard is mapped into digital polar transmitter architecture. System level simulation is performed and transient signal parameters areextracted. To prove the SDR possibility, the system is fully designedby VHDL language and downloaded into FPGA hardware with highspeed serial port. The measured results confirm the possibility of thedigital polar transmitter architecture potential in SDR systemrealization.

Based on the design and verification of two different systems, themethodology for digital implementation of linear transmitter systemis developed and the skill to carry out optimization and measurementis also possessed. In conclusion, the academic publication andverification proved the feasibility of digital polar transmitterapplication in linear system and point out the direction for a fullySDR realization.

• 496.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A 11.4dBm 90nm CMOS H-Bridge Resonating Polar Amplifier using RF Sigma Delta Modulation2011In: Proceedings of the ESSCIRC (ESSCIRC), 2011, IEEE , 2011, p. 307-310Conference paper (Refereed)

Using RF Sigma Delta Modulation (RFSDM), aclass-D polar amplifier in H-Bridge configuration can work in resonatingmode and minimize the switching loss for high efficiencypolar transmitters. The high oversampling ratio envelop bitstream created by the low pass RFSDM is phase modulated anddigitally mixed with quantized RF carrier to give a modulatedRF digital signal. By taking the advantage of high speed andaccurate digital CMOS process, this ’information combination’architecture can achieve high efficiency and reduce the need forexternal filter components. A polar power amplifier based on thisconcept is implemented in 90nm CMOS process and achieved apeak output power of 11.4dBm with 19.3% efficiency at 1.0Vpower supply. The total area is 0.72mm2 including an on-chipfilter matching network designed for 2.4GHz to 2.7GHz band.

• 497.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A Switch Mode Resonating H-Bridge Polar Transmitter using RF Sigma Delta Modulation2010In: IEEE INT SYMP CIRC SYST PROC, 2010, p. 1911-1914Conference paper (Refereed)

Using saturated power amplifier (PA) as the last stage, polar transmitter has the potential to be the most power efficient architecture to transmit large Peak-to-Average Ratio (PAR) signals. In this work, a polar transmitter using H-Bridge configured Class-D amplifiers is proposed. To fully exploit low voltage resource, maintain linearity and meet the spectrum mask requirements, RF Sigma-Delta Modulation (SDM) is used. An on-chip transformer based filter network is designed to filter out SDM noise and provide load matching. The system verification is carried out by using Matlab passband simulation on a 13dB PAR mobile WiMAX signal. Evaluation of noise shaping and spectral regrowth shows the proposed architecture can achieve -45dBc/10kHz ACPR in a 140MHz bandwidth range. This provides a solid ground for the circuit design work.

• 498.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A polar transmitter architecture with digital switching amplifier for UHF RFID applications2011In: 5th Annual IEEE International Conference on RFID, IEEE , 2011, p. 1-6Conference paper (Refereed)

With amplitude shift keying (ASK) modulation and signal envelope rising falling edge slope requirements, the efficiency of UHF RFID system can be improved by using polar transmitter architecture than using linear power amplifiers. In this work, to ensure maximum integration and meet EPC Class-1 Generation-2 specification, an all digital polar transmitter is proposed and verified by transient signal analysis and random pattern simulation. The timing and signal quality constraints of the digital polar transmitter circuits are extracted. Due to the use of RF frequency low pass sigma delta modulation, the system can be designed in pure digital process without on-chip inductive components. Compared to the 31% theoretical efficiency by using class-A linear power amplifier, a minimum 77% theoretical efficiency can be achieved in this proposed digital RFID system.

• 499.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
A constraint-based design space exploration framework for real-time applications on MPSoCs2014In: Proceedings -Design, Automation and Test in Europe, DATE 2014, IEEE Computer Society, 2014, p. 1-6Conference paper (Refereed)

Design space exploration (DSE) is a critical step in the design process of real-time multiprocessor systems. Combining a formal base in form of SDF graphs with predictable platforms providing guaranteed QoS, the paper proposes a flexible and extendable DSE framework that can provide performance guarantees for multiple applications implemented on a shared platform. The DSE framework is formulated in a declarative style as interprocess communication-aware constraint programming (CP) model. Apart from mapping and scheduling of application graphs, the model supports design constraints on several cost and performance metrics, as e.g. memory consumption and achievable throughput. Using constraints with different compliance level, the framework introduces support for mixed criticality in the CP model. The potential of the approach is demonstrated by means of experiments using a Sobel filter, a SUSAN filter, a RASTA-PLP application and a JPEG encoder.

• 500. Sack, H.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions2000In: Proceedings of 30th IEEE International Symposium on Multiple-Valued Logic, 2000, p. 233-239Conference paper (Refereed)
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