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  • 251.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Bekka - A System Specification and Design Framework1997Report (Other academic)
  • 252.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Design Space Exploration with Design Style Description and Estimation Functions1992Other (Other academic)
  • 253.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Formal System Specification Models for Verification and Refinement1999In: EDA-Traff’99, 1999Conference paper (Refereed)
  • 254.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hades: An Environment for Design Space Exploration1993In: Proceedings of GME Fachtagung Mikroelektronik, 1993Conference paper (Refereed)
  • 255.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Integrated Electronic Systems Program - A National Research Program1999In: EDA-Traff’99, 1999Conference paper (Refereed)
  • 256.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Limitations of Interactive Design1997In: Workshop on Electronic Design Processes, 1997Conference paper (Refereed)
  • 257.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Modeling Embedded Systems and SoCs - Concurrency and Time in Models of Computation2003Book (Other academic)
  • 258.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Models of Computation for Networks on Chip2006In: Proceedings - International Conference on Application of Concurrency to System Design, ACSD 2006, 2006Conference paper (Refereed)
    Abstract [en]

    Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making the implementation of these services entirely irrelevant for system design, an effective separation of system design from component design can be achieved. We discuss the principles to formulate network-on-chip services to establish an abstract computational model that exposes all relevant properties of the platform's functionality, performance and power consumption while hiding all irrelevant implementation details. As in many other successful abstractions, these principles are based on separating functionality from time and power aspects to allow for reasoning about these properties at the system level. As a concrete example we formulate a MoC for the Nostrum NoC. It is based on guaranteed bandwidth (GB) and best effort (BE) traffic. The MoC characterizes both GB and BE traffic in terms of closed formulas and allows for efficient composition of traffic.

  • 259.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Models of Embedded Computation2005In: Embedded Systems Handbook / [ed] Richard Zurawski, CRC Press, 2005Chapter in book (Refereed)
  • 260.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Network on Chip2002In: Proceedings of the Conference Radio vetenskap och Kommunication, 2002Conference paper (Refereed)
  • 261.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    NoCs: A new Contract between Hardware and Software2003In: Proceedings of the Euromicro Symposium on Digital System Design, 2003Conference paper (Refereed)
  • 262.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Nocsim: A NoC Simulator2006Other (Other academic)
  • 263.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Bjuréus, Per
    Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors2000In: Proceedings of the Design and Test Europe Conference (DATE), 2000Conference paper (Refereed)
  • 264.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Xiaowen
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Naeem, Abdul
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, Yuang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Penolazzi, Sandro
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Memory Architecture and Management in an NoC Platform2011In: Scalable Multi-core Architectures: Design Methodologies and Tools / [ed] Axel Jantsch and Dimitrios Soudris, Springer, 2011, 1, p. 3-28Chapter in book (Refereed)
    Abstract [en]

    The memory organization and the management of the memory space is a critical part of every NoC based platform design. We propose a Data Management Engine (DME), that is a block of programmable hardware and part of every processing element. It off-loads the processing element (CPU, DSP, etc.) by managing the memory space, memory access and the communication over the on-chip network. The DME’s main functions are virtual address translation, private and shared memory management, cache coherence protocol, support for memory consistency models, synchronization and protection mechanisms for shared memory communication. The DME is fully programmable and configurable thus allowing for customized support for high level data management functions such as dynamic memory allocation and abstract data types. This chapter describes the main concepts, design and functionality of the DME and presents case studies illustrating its usage and performance.

  • 265.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Grange, Matthew
    Pamunuwa, Dinesh
    The Promises and Limitations of 3-D Integration2011In: 3D Integration for NoC-based SoC Architectures, Springer Publishing Company, 2011, p. 27-44Chapter in book (Other academic)
    Abstract [en]

    The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use ECE and ECD to study the limits of performance under different memory distribution constraints of various 2-D and 3-D topologies, in current and future technology nodes. Among other results, our model shows that in a 35 nm technology a 16 stack 3-D system can, as a theoretical upper limit, obtain 3.4 times the performance of a 2-D system (8.8 Tera OPS vs 2.6 TOPS) at 70% reduced frequency (2.1 vs 3.7 GHz) on 1/8 the total area (50 vs 400 mm2).

  • 266.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Isoaho, Jouni
    A Versatile Design Validation Environment by Means of Software Execution, Hardware Simulation, and Emulation1994In: Proc. of the 36th SIMS Simulation Conference, 1994, p. 322-325Conference paper (Refereed)
  • 267.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Isoaho, Jouni
    Öberg, Johnny
    Hardware-Software Codesign for Multirate DSP System Development1994In: Poster session of Third International Workshop on Hardware-Software Codesign, 1994Conference paper (Refereed)
  • 268.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Shashi
    Hemani, Ahmed
    The Pyramid Model: A General Framework for Study of Modelling, Analysis and Synthesis concepts of Electronic Systems1997Report (Other academic)
  • 269.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Shashi
    KTH, School of Information and Communication Technology (ICT).
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    The Rugby Model: a conceptual frame for the study of modelling, analysis and synthesis concepts of electronic systems1999In: Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings, 1999, p. 256-262Conference paper (Refereed)
    Abstract [en]

    We propose a conceptual framework, called the Rugby Model, in which designs, design processes and design tools can be studied. It is an extension of the Y chart and adds two dimensions for design representation, namely Data and Tune. The behavioural domain of Y chart is replaced by a more restricted domain called Computation. The structural and physical domains of Y chart are merged into a more general domain called Communication. A fifth dimension deals with design manipulations and transformations at three abstraction levels. The model shall establish a common understanding of modelling and design process concepts for communication and education in the community. In a case study we illustrate how a design can be characterized with the concepts the Rugby model

  • 270.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Shashi
    Hemani, Ahmed
    The Rugby Model: A Framework for the Study of Modelling, Analysis, and Synthesis Concepts in Electronic Systems1999In: Proceedings of Design Automation and Test in Europe (DATE), 1999Conference paper (Refereed)
  • 271.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Notbauer, Johann
    Albrecht, Thomas
    Functional Validation for Large Telecom Systems2000In: Design Automation of Embedded Systems, Kluwer, Vol. 5Article in journal (Refereed)
  • 272.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Notbauer, Johann
    Albrecht, Thomas
    Testcase Development for Large Telecom Systems1997In: Proceedings of the International High-level Design Validation and test Workshop, 1997Conference paper (Refereed)
  • 273.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Soininen, Juha-Pekka
    Forsell, Martti
    Zheng, Li-Rong
    Kumar, Shashi
    Millberg, Mikael
    Öberg, Johnny
    Networks on Chip2001In: Workshop at the European Solid State Circuits Conference, 2001Conference paper (Refereed)
  • 274.
    Jantsch, Axel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Johnny
    Hemani, Ahmed
    Is there a Niche for a General Protocol Processor ?1998In: Proceeedings of 16th NORCHIP Conference, 1998Conference paper (Refereed)
  • 275.
    Jerraya, Ahmed
    et al.
    TIMA.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Wolf, Wayne
    Princeton University.
    Multiprocessor systems-on-chips2005In: Computer, ISSN 0018-9162, E-ISSN 1558-0814, Vol. 38, p. 36-40Article in journal (Refereed)
    Abstract [en]

    Single processors may be sufficient for low-performance applications that are typical of early microcontrollers, but an increasing number of applications require multiprocessors to meet their performance goals.

  • 276. Jiang, X.
    et al.
    Li, D.
    Xiao, P.
    Liu, S.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lessons of IOT effects on backbone networks learnt from traffic characteristics2012In: Int. Conf. Wirel. Commun., Networking Mob. Comput., WiCOM, 2012Conference paper (Refereed)
    Abstract [en]

    Emerging and blooming internet of things (IOT)technology greatly affects backbone network development. The effects are not accurately tested or predicted yet. As a trial, some traffic characteristics profiling cases are investigated based on a gateway in IOT (IOTGW), a classical device, for data communication between IOT and backbone networks. From this investigation, some lessons of IOT effects on backbone networks are learnt by taking application, network size, data volume, etc. into account. To our knowledge, this study is the first trial to investigate the IOT effects on backbone networks from the traffic perspective.

  • 277. Jiang, X.
    et al.
    Nie, S.
    Luo, J.
    Li, D.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An enhanced iot gateway in a broadcast system2012In: Proceedings - IEEE 9th International Conference on Ubiquitous Intelligence and Computing and IEEE 9th International Conference on Autonomic and Trusted Computing, UIC-ATC 2012, IEEE , 2012, p. 746-751Conference paper (Refereed)
    Abstract [en]

    Internet of things (IOT) technology increasingly affects backbone network development. Aiming to reduce or weaken such effects on backbone networks from a traffic perspective and attain no discount on functions in a CobraNet based digital broadcast system, an enhanced IOT gateway and its evaluation system are presented. Based on the prototype evaluation system, experiments demonstrate the IOT gateway not only inherits the conventional functions previously often carried out by a PC platform or a server, but also develops additional abilities to cut down traffic under some cases and provides portable management for the system at the same time. According to the experimental results, it is possible from a traffic perspective to design an enhanced IOT gateway to provide value added service such as file transfer, message function, etc. in addition to high quality audio service by taking advantage of the verified sub-linear information addition mechanism. Such enhanced gateway can be properly adapted to other kinds of applications according to the nondemanding system requirements of the prototype evaluation system and proposed IOTGW design.

  • 278.
    Jue, Shen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li-Rong, Zheng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jun, Yu
    Non-linear Quantization Effects and Impacts on Phase Noise of Integer-N ALL Digital Phase Locked-Loop2011In: China Journal, ISSN 1324-9347, E-ISSN 1835-8535Article in journal (Refereed)
  • 279.
    Kamrani, Farzad
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Garcia Lozano, Marianela
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ayani, Rassul
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Path planning for UAVs using symbiotic simulation2006In: Modelling and Simulation 2006 / [ed] Nketsa, A; Paludetto, M; Bertelle, C, 2006, p. 207-213Conference paper (Refereed)
    Abstract [en]

    The problem of efficient path planning for Unmanned Aerial Vehicles (UAV) with a surveillance mission in a dynamic environment can in some cases be solved using Symbiotic Simulation (S2), i.e. an on-line simulation that interacts in real-time with the UAV and chooses its path. Sequential Monte Carlo Simulation, known also as Particle Filtering (PF) is an instance of such a simulation. In this paper we describe a methodology and an algorithm to use PF for efficient path planning of a UAV which searches a road network for a target. To verify whether this method is feasible and to supply a tool to compare different methods a simulator is developed. This simulator and its features are presented in this paper as well.

  • 280. Kanth, R. K.
    et al.
    Ahmad, Waqar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Liljeberg, P.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Analysis, design and development of novel, low profile 2.487 GHz microstrip antenna2010In: 2010 14th International Symposium on Antenna Technology and Applied Electromagnetics and the American Electromagnetics Conference, ANTEM/AMEREM 2010, 2010, p. 1-4Conference paper (Refereed)
    Abstract [en]

    International Telecommunication Union Radio Communication Sector ( ITU-R) has assigned 1.176 GHz and 2.487 GHz respectively in L and S band to Regional Navigational Satellite System (RNSS) for satellite navigation purpose. In this paper attempt has been made to design a novel, low profile compact microstrip antenna which achieves required specification such as gain of -4dBi up to ±50° and bandwidth of 30 MHz. The design of S band antenna was carried out using Ansoft Designer software, was fabricated and the required performance of antenna was measured in terms of its return loss, VSWR and gain radiation pattern. The return loss of the developed antenna was measured with the vector network analyzer and its gain radiation pattern in anechoic chamber and the performance of its measurements were compared with the analyzed results.

  • 281.
    Kanth, R. K.
    et al.
    Turku Centre for Computer Science (TUCS).
    Kumar, H.
    Liljeberg, P.
    Turku Centre for Computer Science (TUCS).
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Exploring course development for green ICT in engineering education: A preliminary study2012In: AICERA 2012 - Annual International Conference on Emerging Research Areas: Innovative Practices and Future Trends, IEEE , 2012, p. 6306685-Conference paper (Refereed)
    Abstract [en]

    This paper aims to give an insight into the importance of green ICT course in the curriculum of Master and PhD level studies. An attempt has been made to demonstrate its necessity, implementation issues and strategic plans to execute this course. General structural plans along with details of the course content are discussed in this paper. The course aims to provide a unified view of sustainable embedded system technologies, practices of using efficiently computers and telecommunication equipments, environmental assessment strategies and life cycle management of electronic components as well as end-products. The objective of this new course is to give knowledge and foresight toward assessment of environmental impacts. This course will also be capable of imparting knowledge of sustainable design approach in life cycle of the materials, manufacturing processes, use/reuse and recycling of the electronic equipments and components. The course has been proposed of 5 ECTS credit units inclusive of extensive theoretical lectures and lab exercises using suitable environmental assessment software tools.

  • 282.
    Kanth, R. K.
    et al.
    Turku Centre for Computer Science (TUCS).
    Liljeberg, P.
    Turku Centre for Computer Science (TUCS).
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Comparative End-of-Life Study of Polymer and Paper Based Radio Frequency Devices2012In: International Journal of Environmental Protection, ISSN 2224-7777, Vol. 2, p. 23-27Article in journal (Refereed)
    Abstract [en]

    In this work end-of-life (EOL) analysis of polymer and paper based radio frequency devices have been carried out. Polymer and paper based RFID antenna has been chosen as a radio frequency device. An attempt has been made to investigate and evaluate the environmental emissions at end-of-life-cycle stage and to explore type and quantity of emissions at their disposal. The Gabi’s balance calculation methodology has been employed to determine amount of environmental emissions at the end-of-life cycle stage. Each significant component of the antenna and their corresponding emissions has been investigated in this paper. We have also compared the corresponding emissions to air and fresh water in both the technologies i.e. incineration and land-filling at EOL stage.

  • 283. Kanth, R. K.
    et al.
    Liljeberg, P.
    Tenhunen, H.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ahmad, Waqar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shakya, S.
    Zheng, Li Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Autonomous use of fractal structure in low cost, multiband and compact navigational antenna2010In: Proc. Mediterranean Microwave Symp. (MMS), 2010, p. 135-138Conference paper (Refereed)
    Abstract [en]

    Different fractal structures and their relevance in navigational antennas have been studied. Based on multiband characteristics and performance of sierpinski gasket fractal structures, a dual band, low profile antenna is devised in this paper. Classical fractal structures have been generated with extensive use of MATL AB, dimensions of the parasitic layers are determined viaseveral optimizations in Math CAD and finally design analysis is carried out using Ansoft Designer. The performance of this antenna is theoretically measured in terms of its return loss, gain radiation pattern and axial ratio. The multi layered physical antenna has been fabricated using glass epoxy substrate material contributing acceptable bandwidth in bothbands. The measured performance of the fabricated antenna has been analyzed and evaluated with the theoretical outcomes.

  • 284. Kanth, R. K.
    et al.
    Liljeberg, P.
    Tenhunen, H.
    Wan, Qiansu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ahmad, Waqar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, H.
    Insight into the requirements of self-aware, adaptive and reliable embedded sub-systems of satellite spacecraft2011In: PECCS - Proc. Int. Conf. Pervasive Embedded Comput. Commun. Syst., 2011, p. 603-608Conference paper (Refereed)
    Abstract [en]

    This position paper gives an insight for self-aware and adaptivity requirements of the sub-systems embedded in a satellite spacecraft. The most significant and considerable issues of self-aware and adaptive systems that are necessary in present and future on-board satellite spacecraft are illustrated in this paper. An attempt has been made to discuss several embedded sub-systems and space environment scenarios of the spacecraft. As a case study, an adaptive sierpinski based dual band antenna has been devised. The adaptive nature of this antenna provides a foundation of longer and more reliable mission life of a spacecraft. Through this paper it will be shown that adaptive, reconfigurable and reliability issues are the most prominent and potential area of research for outer space communication technology.

  • 285. Kanth, R. K.
    et al.
    Liljeberg, P.
    Tenhunen, Hannu
    Turku Centre for Computer Science, University of Turku, Finland.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Janstch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, H.
    Design of sierpinski grid patch antenna for multiband application2013In: Progress In Electromagnetics Research Symposium Proceedings, Stockholm, Sweden, Aug. 12-15, 2013, 2013, p. 577-582Conference paper (Refereed)
    Abstract [en]

    The purpose of this paper is two-fold. Firstly, we have attempted to design a planar Sierpinski fractal antenna with stacked configuration for multiband applications. The stacked configuration of Sierpinski fractal patch and Sierpinski grid are employed to improve the multiband characteristics. The operating frequencies obtained are at 3.3 GHz, 5GHz, 5.74 GHz and 5.9 GHz which covers the bands useful for HIPERLAN2 frequencies and for implementation in futuristic WiFi enabled devices and PCI Cards for mobile internet. The Simulated results show that the operating frequencies obtained are spread over a wide range of frequency band compared to the simple Sierpinski fractal patch antenna. Secondly this paper aims at evaluating the sustainability and life cycle management of proposed antenna.

  • 286.
    Kanth, R. K.
    et al.
    Turku Centre for Computer Science (TUCS).
    Liljeberg, P.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Kumar, H.
    Quantifying the environmental footprint of rigid substrate printed antenna2012In: Proceedings of the 2012 IEEE Conference on Technology and Society in Asia, T and SA 2012, IEEE , 2012, p. 6397973-Conference paper (Refereed)
    Abstract [en]

    Quantifying environmental footprint is an important task for the embedded system researcher as this study keep them aware of environmental impacts' threat toward green and healthy living of human beings. In this work we have presented a study on analysis of sustainability and environmental impacts assessment in manufacturing process of rigid substrate printed antennas. Life cycle assessment approach has been employed to quantify and asses the environmental footprint. A case study has been carried out for epoxy resin substrate based tip truncated equilateral triangle microstrip antenna. The subtractive printing methodology have been conducted to trace the required antenna pattern. The output parameters have been analyzed in terms of global warming potential, ozone layer depletion potential, human toxicity and acidification potential. Gabi's balance approach has been utilized to analyze the environmental emissions to the air, fresh water, sea water, agricultural and industrial soils. The consumption of resources has also been shortly described in this paper.

  • 287.
    Kanth, R. K.
    et al.
    Turku Centre for Computer Science (TUCS).
    Liljeberg, P.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Janstch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Kumar, H.
    Varshney, L.
    Turku Centre for Computer Science (TUCS).
    Design of Sierpinski Grid Patch Antenna for Multiband Application and Sustainability Analysis in its Manufacturing Process2012In: IEEE International Conference on Industrial Technology, 2012, p. 1-5Conference paper (Refereed)
    Abstract [en]

    The purpose of this paper is two-fold. Firstly, we have attempted to design a planar Sierpinski fractal antenna in stacked configuration for multiband application. The stacked configuration of Sierpinski fractal patch and Sierpinski grid are employed to improve the multiband characteristics. The operating frequencies obtained are at 3.3 GHz, 5 GHz, 5.74 GHz and 5.9 GHz which covers the bands useful for HIPERLAN2 frequencies and for implementation in futuristic WiFi enabled devices and PCI Cards for mobile internet. The Simulated results show that the operating frequencies obtained are spread over a wide range of frequency band compared to the simple Sierpinski fractal patch antenna. Secondly this paper aims at evaluating the sustainability and life cycle management of proposed antenna.

  • 288. Kanth, R. K.
    et al.
    Liljeberg, P.
    Tenhunen, Hannu
    University of Turku, Finland.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Harish
    KTH, School of Information and Communication Technology (ICT).
    Comparative toxic emission analysis in production process of polymer and paper Based RFID tags2012In: 2012 11th International Conference on Environment and Electrical Engineering, EEEIC 2012 - Conference Proceedings, IEEE , 2012, p. 184-187Conference paper (Refereed)
    Abstract [en]

    A balance optimization method has been employed to determine the quantity of toxic emissions particularly in emissions to air, fresh water, sea water and industrial soil, in production process of polymer and paper based RFID tags. We have developed a low profile antenna design for passive UHF RFID tags using both polymer and paper substrate with copper and aluminum for the antenna trace. Comparative analysis of toxic emissions during production process of polymer and paper based RFID antennas have been discussed in this paper. Our results show that paper based RFID antennas yield lower organic emissions to the environment while considerably higher inorganic emissions to the air. The results also depict that air is highly affected with the toxic emissions compared to fresh water, sea water and industrial soil.

  • 289. Kanth, R. K.
    et al.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Wan, Qiansu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Insight into quantitative environmental emission analysis of printed circuit board2011In: 2011 10th International Conference on Environment and Electrical Engineering, EEEIC.EU 2011 - Conference Proceedings, 2011, p. 1-4Conference paper (Refereed)
    Abstract [en]

    This paper presents quantitative analysis of environmental emissions in different life cycle stages such as raw material preparation (RMP) and production processing (PP) of printed circuit board. A general emission model for printed circuit board (PCB) has been developed to analyze the emissions to air, fresh water, sea water and industrial soil. This work also demonstrates the quantities of renewable and non-renewable resources that are required to manufacture PCBs. Based on these generic models, the environmental assessment has been carried out in a production of one million PCBs. We also make an attempt to give an analytic description for evaluating the amount of emissions in each life cycle stages of the printed circuit board.

  • 290. Kanth, R. K.
    et al.
    Wan, Qiansu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, H.
    Liljeberg, P.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, LiRong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    University of Turku.
    Evaluating sustainability, environment assessment and toxic emissions in life cycle stages of printed antenna2012In: International Conference On Communication Technology And System Design 2011, Elsevier, 2012, Vol. 30, p. 508-513Conference paper (Refereed)
    Abstract [en]

    In this work cradle to grave life cycle assessment of printed electronics resources have been presented. An attempt has been made to investigate and evaluate the life cycle assessment and environmental impacts of printed electronics resources such as polymer substrate-printed RFID antenna. Life cycle inventory analysis for these resources has been carried out to quantify total systems' inputs and outputs that are relevant to the environmental impacts especially emissions to air, fresh water, industrial soil and sea water. The results show that printed electronics materials are considerably more environment friendly than materials needed for PCB electronics. We have obtained the mass of emissions in each life cycle stages which verify that technology wise printed antenna causes less harmful and hazardous impacts to the environment.

  • 291. Kanth, R. K.
    et al.
    Wan, Qiansu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, H.
    Liljeberg, P.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Life cycle assessment of printed antenna: Comparative analysis and environmental impacts evaluation2011In: Proceedings of the 2011 IEEE International Symposium on Sustainable Systems and Technology, ISSST 2011, New York: IEEE , 2011, p. 5936899-Conference paper (Refereed)
    Abstract [en]

    THIS paper presents cradle to grave life cycle assessment of printed electronics resources. In this work, an attempt has been made to investigate and evaluate the life cycle assessment and environmental impacts of printed electronics resources such as polymer substrate-printed RFID antenna. Life cycle inventory analysis for these resources has been carried out to quantify total systems' inputs and outputs that are relevant to the environmental impacts especially emissions to air, fresh water, industrial soil and sea water.

  • 292. Kanth, Rajeev Kumar
    et al.
    Liljeberg, Pasi
    Tenhunen, Hannu
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Harish
    Study on Glass-Epoxy-Based Low-Cost and Compact Tip-Truncated Triangular Printed Antenna2012In: International Journal of Antennas and Propagation, ISSN 1687-5869, E-ISSN 1687-5877, p. 184537-Article in journal (Refereed)
    Abstract [en]

    Printed antennas based on glass epoxy substrate have been developed. On the basis of required specifications and assigned frequencies, tip-truncated triangular printed antennas have been designed, analyzed, and fabricated. The performances of the antennas have been measured in terms of return loss, frequency of operation, bandwidth, and radiation pattern. Triangular microstrip antenna (TMSA) configuration consisting of copper as active radiating patch and glass epoxy as dielectric substrate has been screened out to achieve the essential characteristics and satisfying recommended low-cost antenna. The Method of Moment (MOM) analyzing techniques have been employed to realize the required specific properties, whereas optimized tip truncation technique and varying feed point location give rise to suitable LHCP or RHCP configuration of the printed antenna. The coaxial probe signal feed arrangement have been considered for this work. The proposed printed antennas are suitable for communication links between ships or buoys and satellites specially for navigation purpose.

  • 293.
    Kanth, Rajeev Kumar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Liljeberg, Pasi
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Wan, Qiansu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shao, Botao
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Kumar, Harish
    Evaluating Sustainability, Environmental Assessment and Toxic Emissions during Manufacturing Process of RFID Based Systems2011In: Dependable, Autonomic and Secure Computing (DASC), 2011 IEEE Ninth International Conference on, 2011, p. 1066-1071Conference paper (Refereed)
    Abstract [en]

    The present state of the art research in the direction of embedded systems demonstrate that analysis of life-cycle, sustainability and environmental assessment have not been a core focus for researchers. To maximize a researcher's contribution in formulating environmentally friendly products, devising green manufacturing processes and services, there is a strong need to enhance life-cycle awareness and sustainability understandings among embedded systems researchers, so that the next generation of engineers will be able to realize the goal of a sustainable life-cycle. In this work an attempt has been made to investigate and evaluate the life-cycle management and environmental assessment in fabricating processes of the RFID based systems. We have chosen a general life cycle assessment approach which involves the collection and evaluation of quantitative data on the inputs and outputs of materials and energy associated with the RFID based systems. Based on the developed generic models, we have obtained the results in terms of environmental emissions for a production of paper substrate printed RFID antennas. We also make an attempt to raise several sustainability issues and quantify the toxic emissions during the manufacturing process.

  • 294. Kazerouni, I. A.
    et al.
    Dehrizi, H. G.
    Isfahani, S. M. M.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Baghaei-Nejad, Majid
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A 77 nW bioamplifier with a tunable bandwidth for neural recording systems2010In: IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 2010, p. 36-39Conference paper (Refereed)
    Abstract [en]

    In this paper a low-power low-noise amplifier for neural recording and biomedical applications is presented. The frequency band of the amplifier is tunable. It has a gain of 28.3 dB. The low and the high cut-off frequency can be adjusted from 24 mHz to 30.6 Hz and 4.5 kHz to 7.47 kHz, respectively. The circuit is designed in 0.18μm CMOS process, and it consumes only 77.8 nW at 1.8V supply voltage. The simulation results show a 14.3μV input-referred noise corresponding to 1.32 efficiency factor (NEF). It is a great improvement compared with recent presented works in terms on power consumption and NEF which is vital in neural recording applications.

  • 295. Khatib, Iyad Al
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Saleh, Mohammad
    Simulation of Real Home Healthcare Sensor Networks Utilizing IEEE 802.11g Biomedical Network-on-Chip2005In: Proceedings of REALWAN, 2005Conference paper (Other academic)
  • 296.
    Khatib, Iyad Al
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Poletti, Francesco
    Bertozzi, Davide
    Benini, Luca
    Bechara, Mohamed
    Khalifeh, Hasan
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Nabiev, Rustam
    A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration2008In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 13, no 2, p. 31-Article in journal (Refereed)
    Abstract [en]

    In this article we focus on multiprocessor system-on-chip (MPSoC) architectures for human heart electrocardiogram (ECG) real time analysis as a hardware/software (HW/SW) platform offering an advance relative to state-of-the-art solutions. This is a relevant biomedical application with good potential market, since heart diseases are responsible for the largest number of yearly deaths. Hence, it is a good target for an application-specific system-on-chip (SoC) and HW/SW codesign. We investigate a symmetric multiprocessor architecture based on STMicroelectronics VLIW DSPs that process in real time 12-lead ECG signals. This architecture improves upon state-of-the-art SoC designs for ECG analysis in its ability to analyze the full 12 leads in real time, even with high sampling frequencies, and its ability to detect heart malfunction for the whole ECG signal interval. We explore the design space by considering a number of hardware and software architectural options. Comparing our design with present-day solutions from an SoC and application point-of-view shows that our platform can be used in real time and without failures.

  • 297. Kianpour, I.
    et al.
    Baghaei-Nejad, Majid
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zeinolabedin, S. M. A.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A subthreshold ultra low power 22fJ/conversion flash ADC for RFID sensing applications2011In: 2011 19th Iranian Conference on Electrical Engineering (ICEE), 2011, p. 1-4Conference paper (Other academic)
    Abstract [en]

    In this paper an ultra low power Flash ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power Track-and-Latch comparator with no static current, large resisters in the resister string, an optimum encoder with only 2 stages using subthreshold design with the aid of low supply voltage of 0.7v for resister string and 0.5v for all logic blocks. In this ADC by absolute approximation the occupied area is equal with area of 16 resisters in the string. The circuit designed in 0.18μm CMOS technology and simulations show that the 4-bit ADC consumes almost 14.5μW at 40MS/s and 93.8nW at 0.1MS/s; however, it minimally dissipates only 22fJ per each conversion step. The results show that the proposed ADC could seriously compete with other low power ADCs in RFID sensing applications such as SAR ADCs.

  • 298. Kianpour, I.
    et al.
    Baghaei-Nejad, Majid
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    78 nW ultra-low-power 17 kS/s two-step-successive approximation register analogue-to-digital converter for RFID and sensing applications2012In: IET CIRC DEVICE SYST, ISSN 1751-858X, Vol. 6, no 6, p. 397-405Article in journal (Refereed)
    Abstract [en]

    In this study an ultra-low-power successive approximation register (SAR) analogue-to-digital converter (ADC) for radio frequency identification (RFID) applications is presented. Several techniques are used to further reduce power consumption and relatively elevate the speed of the conventional SAR ADC. These techniques include a low-power comparator with no static current, a dual-stage (resistor-string/capacitive dividing) architecture as digital-to-analogue converter (DAC), and utilising low-power design with the aid of low supply voltages: 0.7 V for DAC, and 0.5 V for SAR block and pulse generator circuitry (PGC). In the DAC architecture fine search will be performed by only two C and 15C capacitors which reduce the silicon area significantly. The circuit designed in 0.18 mu m complementary metal-oxide-semiconductor (CMOS), technology and post-layout simulations show that the 8-bit core ADC consumes almost 78.4 nW at 17.8 kS/s speed whereas the PGC block consumes 84.1 nW. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison to its charge redistribution counterparts.

  • 299. Kianpour, I.
    et al.
    Baghaei-Nejad, Majid
    Sabzevar Tarbiat Moallem University, Sabzevar, Iran.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    A subthreshold 8-bit 78.4nw 17.8 kS/s 0.18um SAR ADC for RFID sensing applications2011In: 2011 19th Iranian Conference on Electrical Engineering, ICEE 2011, 2011, p. 1-5Conference paper (Refereed)
    Abstract [en]

    In this paper an ultra low power SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power comparator with no static current, a dual-stage (Resistor-string / capacitive dividing) architecture as digital-to-analog converter (DAC) and using subthreshold design with the aid of low supply voltage of 0.7v for DAC and 0.5v for SAR block and Pulse Generator Circuit (PGC). In this DAC architecture fine search will be performed by only two C and 15C capacitors which reduce the silicon area significantly. A new FOM is also proposed for better verification of ADCs with power in W and nW range. The circuit designed in 0.18um CMOS technology and post layout simulations show that the 8-bit core ADC, consumes almost 78.4nW at 17.8kS/s speed and the PGC block which is designed in subthreshold region consumes 84.1nW. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison with its charge redistribution counterparts.

  • 300. Kianpour, I.
    et al.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Baghaei-Nejad, Majid
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    An 8-bit 166nw 11.25 kS/s 0.18um two-step-SAR ADC for RFID applications using novel DAC architecture2010In: 28th Norchip Conference, NORCHIP 2010, 2010, p. 1-4Conference paper (Refereed)
    Abstract [en]

    SAR ADCs have been mostly used for moderate-speed, moderate-resolution applications that power consumption is one of the major concerns (e. g. RFID). Furthermore two-step ADCs are classified as high-speed, low to moderate-accuracy ADC. In this paper an ultra low power two-step-SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power comparator with no static current and a dual-stage (Resistor-string / capacitive dividing) architecture as digital-to-analog converter (DAC). In this DAC architecture fine search will be performed by only two C and 15C capacitors which reduced the silicon area significantly. The circuit designed in 0.18um CMOS technology and simulations show that the 8-bit ADC, consumes almost 166nW at 11.25kS/s. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison with its charge redistribution counterpart.

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