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  • 251.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodríguez de Llera González, Delia
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    The design of a low-distortion sigma-delta ADC for WLAN standards2005In: ISSCS 2005: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, Proceedings, 2005, p. 151-154Conference paper (Refereed)
    Abstract [en]

    A low-distortion sigma-delta analog-to-digital converter (ADC) for Wireless Local Area Network (WLAN) standards is presented. The proposed sigma-delta modulator architecture employs the 4-bit 2(nd) order sigma-delta modulator with swing suppression in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). The modulator is designed in 0.18um CMOS process and operates at 1.8V supply voltage. It achieves a dynamic range of 69.1dB and a spurious free dynamic range (SFDR) of 82.2dB for a 10MHz signal bandwidth, and an oversampling ratio of 8.

  • 252.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Roslind Jose, Babita
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Linearity enhancement in a configurable sigma-delta modulator2005In: IEEE-NEWCAS Conference, 2005. The 3rd International / [ed] IEEE, IEEE conference proceedings, 2005, p. 59-62Conference paper (Refereed)
    Abstract [en]

    A highly linear sigma-delta modulator for dual-standard receivers is presented. The modulator makes use of low-distortion sigma-delta modulator architecture to attain high linearity over a wide bandwidth. The dual-band modulator employs a 2nd order single-bit sigma-delta modulator with feedforward path for GSM mode and a 4th order modified cascaded modulator with single-bit in the first stage and 4-bit in the second for WCDMA mode. The modulator is designed in TSMC 0.18μm CMOS technology and operates at 1.8 supply voltage. It achieves in GSM/WCDMA mode a peak SNDR of 83/75dB, a 96/84dB SFDR and an IMD3 of -93/-82dB for an OSR of 160/16.

  • 253.
    Sander, Ingo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Acosta, Alfonso
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hardware Design and Synthesis in ForSyDe2009In: Proceedings of Hardware Design and Functional Languages, 2009Conference paper (Refereed)
  • 254.
    Sander, Ingo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Modelling Adaptive Systems in ForSyDe2008In: Electronical Notes in Theoretical Computer Science, ISSN 1571-0661, E-ISSN 1571-0661, Vol. 200, no 2, p. 39-54Article in journal (Refereed)
    Abstract [en]

    Emerging architectures such as partially reconfigurable FPGAs provide a huge potential for adaptivity in the area of embedded systems. Since many system functions are only executed at particular points of time they can share an adaptive component with other system functions, which can significantly reduce the design costs. However, adaptivity adds another dimension of complexity into system design since the system behaviour changes during the course of adaptation. This imposes additional requirements on the design process, in particular system verification. In this paper we illustrate how adaptivity is treated as first-class citizen inside the ForSyDe design framework. ForSyDe is a transformational system design methodology, where an initial abstract system model is refined by the application of semantic-preserving and non-semantic preserving design transformations into a detailed model that can be mapped to an implementation. Since ForSyDe is based on the functional paradigm we can model adaptivity by using functions as signal values, which we use as the base for our concept of adaptive processes. Depending on the level of adaptivity we categorise four classes of adaptive process, spanning from parameter adaptive to interface adaptive process. We illustrate our concepts by two typical examples for adaptivity, where we also show the application of design transformations.

  • 255.
    Sander, Ingo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhu, Jun
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Herrholz, Andreas
    Hartmann, Philipp A.
    Nebel, Wolfgang
    High-Level Estimation and Trade-Off Analysis for Adaptive Real-Time Systems2009In: 2009 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, 2009, p. 2985-2988Conference paper (Refereed)
    Abstract [en]

    We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accurate design cost estimates at an early design stage. Given the size and computation time of a set of configurations, which can be derived through logic synthesis, our method gives estimates for configuration parameters, such as bitstream sizes, computation mid reconfiguration times. To fulfil the system's throughput requirements, the required FIFO buffer sizes are then calculated using a hybrid analysis approach based on integer linear programming and simulation. Finally, we are able to calculate the total design cost as the sum of the costs for the FPGA area, the required configuration memory and the FIFO buffers. We demonstrate our method by analysing non-obvious trade-offs for a static and dynamic implementation of adaptivity.

  • 256.
    Sarmiento, David M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Nejad, Majid Baghaei
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Low power tunable CMOS I-UWB transmitter design2007In: 2007 Norchip, 2007, p. 116-119Conference paper (Refereed)
    Abstract [en]

    In this paper an on-chip tunable Impulse-Ultra Wide Band Transmitter is presented. It is capable of modifjing the power emission to comply with the FCC regulations at different pulse rates up to 300 NMz using two external controls. The maximum power consumption is 1.2 mW and 142 mu W at 300 NMz and 10 AM PRF respectively with a leakage current of 100 nA. The prototype has been designed in 0.18 UMC technology and placed in a QFN lead-less package.

  • 257.
    Schulte, Christian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Carlsson, Mats
    Finite Domain Constraint Programming Systems2006In: Handbook of Constraint Programming / [ed] Francesca Rossi, Peter van Beek, Toby Walsh, Elsevier, 2006, p. 495-526Chapter in book (Other academic)
  • 258.
    Schulte, Christian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Stuckey, Peter J.
    Dynamic Variable Elimination During Propagation Solving2008In: PPDP 2008: Proceedings of the 10th International ACM SIGPLAN Symposium on Principles and Practice of Declarative Programming, ACM Press, 2008, p. 247-257Conference paper (Refereed)
    Abstract [en]

    Constraint propagation solvers interleave propagation (removing impossible values from variables domains) with search. Propagation is performed by executing propagators (removing values) implementing constraints (defining impossible values). In order to specify constraint problems with a propagation solver often many new intermediate variables need to be introduced. Each variable plays a role in calculating the value of some expression. But as search proceeds not all of these expressions will be of interest any longer, but the propagators implementing them will remain active. In this paper we show how we can analyse the propagation graph of the solver in linear time to determine intermediate variables that can be removed without effecting the result. Experiments show that applying this analysis can reduce the space and time requirements for constraint propagation on example problems.

  • 259.
    Schulte, Christian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tack, Guido
    Perfect Derived Propagators2008In: PRINCIPLES AND PRACTICE OF CONSTRAINT PROGRAMMING / [ed] Stuckey, PJ, 2008, Vol. 5202, p. 571-575Conference paper (Refereed)
    Abstract [en]

    When implementing a propagator for a constraint, one must decide about variants: When implementing min , should one also implement max ? Should one implement linear equations both with and without coefficients? Constraint variants are ubiquitous: implementing them requires considerable effort, but yields better performance. This paper shows how to use variable views to derive perfect propagator variants: derived propagators inherit essential properties such as correctness and domain and bounds completeness.

  • 260.
    Schulte, Christian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tack, Guido
    Views and Iterators for Generic Constraint Implementations2006In: Recent Advances in Constraints, Springer Berlin/Heidelberg, 2006, Vol. 3978, p. 118-132Chapter in book (Refereed)
  • 261. Seceleanu, T.
    et al.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jerraya, A.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Kuzmanov, G.
    Goosens, K.
    Collette, T.
    Candaele, B.
    Gide, L.
    Madsen, J.
    Multicore Processing and ARTEMIS2006In: Turku UniverstiyArticle in journal (Refereed)
  • 262. Seceleanu, Tiberiu
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Communicating with Synchronized Environments2006In: Proceedings of the Sixth International Conference on Application of Concurrency to System Design, 2006, p. 15-24Conference paper (Refereed)
    Abstract [en]

    In the modern design environments, different modules, available in existent libraries, may obey different architectural styles and execution models. Reaching a well-behaved composition of such modules is a very important task of the system designer. In the framework of the action systems formalism, we analyze the co-existence of two models of execution, one synchronized, the other, interleaved. We devise a communication scheme, similar to the classical paradigm of polling, which allows us to model synchronized components that correctly exchange information, within the borders of a global system, with their non-synchronized partners. Derivations of such mechanisms follow specific correctness rules for refinement. We illustrate our methods on an audio system example, implementable as either a software or a hardware device.

  • 263. Seceleanu, Tiberiu
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. TUCS, Finland .
    On-Chip Distributed Architectures2006In: 2006 IEEE International Systems-on-Chip Conference, SOC / [ed] Secareanu, R; Krishnamurthy, R; Kim, S; Tran, T, IEEE , 2006, p. 329-330Conference paper (Refereed)
  • 264.
    Shaber, Mezbah Uddin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Signell, Svante
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Pipelined DAC architecture using gray coding2005In: Norchip 2005, Proceedings, 2005, p. 141-144Conference paper (Refereed)
    Abstract [en]

    This work describes a new architecture suitable for wideband Digital to Analog converter for System-on-Chip. The architecture use switched capacitor pipelined D/A converter design with Selection Inversion based on gray coded bits. A 95dB DC-gain fully differential folded cascode gain-boosted OTA has been designed to be used in each pipelined stage. High linearity up to 61db (SFDR) is achieved for a 5MHz input sign wave at a 50MHz Update frequency. This work describes a new architecture suitable for wideband Digital to Analog converter for System-on-Chip. The architecture use switched capacitor pipelined D/A converter design with Selection Inversion based on gray coded bits. A 95dB DC-gain fully differential folded cascode gain-boosted OTA has been designed to be used in each pipelined stage. High linearity up to 61db (SFDR) is achieved for a 5MHz input sign wave at a 50MHz Update frequency.

  • 265.
    Shafaat, Tallat M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Baden, Scott B.
    A method of adaptive coarsening for compressing scientific datasets2007In: Applied Parallel Computing: State Of The Art In Scientific Computing / [ed] Kagstrom, B; Elmroth, E; Dongarra, J; Wasniewski, J, 2007, Vol. 4699, p. 774-780Conference paper (Refereed)
    Abstract [en]

    We present adaptive coarsening, a multi-resolution lossy compression algorithm for scientific datasets. The algorithm provides guaranteed error bounds according to the user's requirements for subsequent post-processing. We demonstrate compression factors of up to an order of magnitude with datasets coming from solutions to time-dependent partial differential equations in one and two dimensions.

  • 266.
    Shafaat, Tallat M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ghodsi, Ali
    Haridi, Seif
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS.
    A Practical Approach to Network Size Estimation for Structured Overlays2008In: SELF-ORGANIZING SYSTEMS, PROCEEDINGS / [ed] Hummel KA; Sterbenz JPG, Berlin: SPRINGER-VERLAG , 2008, Vol. 5343, p. 71-83Conference paper (Refereed)
    Abstract [en]

    Structured overlay networks have recently received much attention due to their self-* properties under dynamic and decentralized settings. The number of nodes in all overlay fluctuates all the time due to churn. Since knowledge of the size of the. overlay is a core requirement for many systems, estimating the size in a decentralized manner is a challenge taken up by recent research activities. Gossip-based Aggregation has been shown to give accurate estimates for the network size, but previous work done is highly sensitive to node failures. In this paper, we present a gossip-based aggregation-style network size estimation algorithm. We discuss shortcomings of existing aggregation-based size estimation algorithms, and give a solution that is highly robust to node failures and is adaptive to network delays. We examine our solution in various scenarios to demonstrate. its effectiveness.

  • 267.
    Shafaat, Tallat M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ghodsi, Ali
    Haridi, Seif
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS.
    Dealing with network partitions in structured overlay networks2009In: Peer-to-Peer Networking and Applications, ISSN 1936-6442, Vol. 2, no 4, p. 334-347Article in journal (Refereed)
    Abstract [en]

    Structured overlay networks form a major class of peer-to-peer systems, which are touted for their abilities to scale, tolerate failures, and self-manage. Any long-lived Internet-scale distributed system is destined to face network partitions. Although the problem of network partitions and mergers is highly related to fault-tolerance and self-management in large-scale systems, it has hardly been studied in the context of structured peer-to-peer systems. These systems have mainly been studied under churn (frequent joins/failures), which as a side effect solves the problem of network partitions, as it is similar to massive node failures. Yet, the crucial aspect of network mergers has been ignored. In fact, it has been claimed that ring-based structured overlay networks, which constitute the majority of the structured overlays, are intrinsically ill-suited for merging rings. In this paper, we present an algorithm for merging multiple similar ring-based overlays when the underlying network merges. We examine the solution in dynamic conditions, showing how our solution is resilient to churn during the merger, something widely believed to be difficult or impossible. We evaluate the algorithm for various scenarios and show that even when falsely detecting a merger, the algorithm quickly terminates and does not clutter the network with many messages. The algorithm is flexible as the tradeoff between message complexity and time complexity can be adjusted by a parameter.

  • 268.
    Shafaat, Tallat M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ghodsi, Ali
    Haridi, Seif
    KTH, School of Information and Communication Technology (ICT), Communication Systems, CoS.
    Handling network partitions and mergers in structured overlay networks2007In: P2P: Seventh International Conference On Peer-To-Peer Computing, Proceedings / [ed] Hauswirth, M; Montresor, A; Shahmehri, N; Wehrle, K; Wierzbicki, A, 2007, p. 132-139Conference paper (Refereed)
    Abstract [en]

    Structured overlay networks form a major class of peer-to-peer systems, which are touted for their abilities to scale, tolerate failures, and self-manage. Any long-lived Internet-scale. distributed system is destined to face network partitions. Although the problem of network partitions and mergers is highly related to fault-tolerance and self-management in large-scale systems, it has hardly been studied in the context of structured peer-to-peer systems. These systems have mainly been studied under chum (frequent joins/failures), which as a side effect solves the problem of network partitions, as it is similar to massive node failures. Yet, the crucial aspect of network mergers has been ignored. In fact, it has been claimed that ring-based structured overlay networks, which constitute the majority of the structured overlays, are intrinsically ill-suited for merging rings. In this paper we present an algorithm for merging multiple similar ring-based overlays when the underlying network merges. We examine the solution in dynamic conditions, showing how our solution is resilient to churn during the merger something widely believed to be difficult or impossible. We evaluate the algorithm for various scenarios and show that even when falsely detecting a merger the algorithm quickly terminates and does not clutter the network with many messages. The algorithm is flexible as the tradeoff between message complexity and time complexity can be adjusted by a parameter.

  • 269.
    Shafaat, Tallat M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Moser, Monika
    Ghodsi, Ali
    Schuett, Thorsten
    Haridi, Seif
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS.
    Reinefeld, Alexander
    On consistency of data in structured overlay networks2008In: GRID COMPUTING: ACHIEVEMENTS AND PROSPECTS / [ed] Gorlatch, S; Fragopoulou, P; Priol, T, NEW YORK: SPRINGER , 2008, p. 249-260Conference paper (Refereed)
    Abstract [en]

    Data consistency can be violated in Distributed Hash Tables (DHTs) due to inconsistent lookups. In this paper, we identify the events leading to inconsistent lookups and inconsistent responsibilities for a key. We find the inaccuracy of failure detectors as the main reason for inconsistencies. By simulations with inaccurate failure detectors, we study the probability of reaching a system configuration which may lead to inconsistent data. We analyze majority-based algorithms for operations on replicated data. To ensure that concurrent operations do not violate consistency, they have to use non-disjoint sets of replicas. We analytically derive the probability of concurrent operations including disjoint replica sets. By combining the simulation and analytical results, we show that the probability for a violation of data consistency is negligibly low for majority-based algorithms in DHTs.

  • 270.
    Shafaat, Tallat M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Schütt, Thomas
    Moser, Monika
    Haridi, Seif
    KTH, School of Information and Communication Technology (ICT), Communication: Services and Infrastucture, Software and Computer Systems, SCS.
    Ghodsi, Ali
    Reinefeld, Alexander
    Key-based consistency and availability in structured Overlay Networks2008In: Proceedings of the 17th International Symposium on High Performance Distributed Computing 2008, HPDC'08, 2008, p. 235-236Conference paper (Refereed)
    Abstract [en]

    Structured Overlay Networks (SONs) provide a promising platform for high performance applications since they are scalable, fault-tolerant and self-managing. SONs provide lookup services that map keys to nodes that can be used as processing or storage resources. In SONs, lookups for a key may return inconsistent results. Consequently, it is difficult to provide consistent data services on top of SONs that build on key-based search. In this paper, we study the frequency of occurrence of inconsistent lookups. We show that the affect of lookup inconsistencies can be reduced by using node responsibilities. We present our results as a trade-off between consistency and availability of keys.

  • 271.
    Shafaat, Tallat Mahmood
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Dealing with Network Partitions and Mergers in Structured Overlay Networks2009Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Structured overlay networks form a major classof peer-to-peer systems, which are touted for their abilitiesto scale, tolerate failures, and self-manage. Any long livedInternet-scale distributed system is destined to facenetwork partitions. Although the problem of network partitionsand mergers is highly related to fault-tolerance andself-management in large-scale systems, it has hardly beenstudied in the context of structured peer-to-peer systems.These systems have mainly been studied under churn (frequentjoins/failures), which as a side effect solves the problemof network partitions, as it is similar to massive nodefailures. Yet, the crucial aspect of network mergers has beenignored. In fact, it has been claimed that ring-based structuredoverlay networks, which constitute the majority of thestructured overlays, are intrinsically ill-suited for mergingrings. In this thesis, we present a number of research papers representing our work on handling network partitions and mergers in structured overlay networks. The contribution of this thesis is threefold. First, we provide a solution for merging ring-based structured overlays. Our solution is tuneable, by a {\em fanout} parameter, to achieve a trade-off between message and time complexity. Second, we provide a network size estimation algorithm for ring-based structured overlays. We believe that an estimate of the current network size can be used for tuning overlay parameters that change according to the network size, for instance the fanout parameter in our merger solution.Third, we extend our work from fixing routing anomalies to achieving data consistency. We argue that decreasing lookup inconsistencies on the routing level aids in achieving data consistency in applications built on top of overlays. We study the frequency of occurence of lookup inconsistencies and discuss solutions to decrease the affect of lookup inconsistencies.

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  • 272.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Liu, Ran
    Fudan University.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Process-dependence of inkjet printed folded dipole antenna for 2.45 GHZ RFID tags2009In: 2009 3RD EUROPEAN CONFERENCE ON ANTENNAS AND PROPAGATION, VOLS 1-6, NEW YORK: IEEE , 2009, p. 2336-2339Conference paper (Refereed)
    Abstract [en]

    This paper focuses on the process dependence of an inkjet printed folded dipole antenna based on practical parameters in a typical inkjet printing process. We present the effect of width variations and number of overprinting times on the antenna properties such as gain, radiation efficiency and input impedance. Furthermore we investigate the read range degradation of the tag on which the antenna is attached, due to width or thickness variations. In addition, an comparison between an inkjet printed antenna on a regular paper substrate and a copper antenna on Printed Circuit Board (PCB) was made, manifesting the strong competitiveness of the printed silver antenna as a low cost solution.

  • 273.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Weerasekera, Roshan
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Woldegiorgis, Abraham Tareke
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Liu, Ran
    Zapka, Werner
    High Frequency Characterization and Modelling of Inkjet Printed Interconnects On Flexible Substrate for Low-Cost RFID Applications2008In: ESTC 2008: 2ND ELECTRONICS SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, NEW YORK: IEEE , 2008, p. 695-699Conference paper (Refereed)
    Abstract [en]

    This paper presents the characterization and modeling of inkjet printed interconnects on flexible polyimide substrate using nano-paticle silver ink for low-cost RFID applications. Then TDR/TDT and S-parameter measurements are performed at high frequency from 30 kHz to 6 GHz. A Jumped equivalent circuit and distributed parameter model of the printed interconnects have been developed for the realization of the full printed RFID tags. Additionally the related electrical properties of the printed interconnects are extracted.

  • 274.
    Shao, Botao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Weerasekera, Roshan
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Liu, Ran
    Zapka, Werrier
    Lindberg, Peter
    High frequency characterization of inkjet printed coplanar waveguides2008In: 2008 IEEE Workshop On Signal Propagation On Interconnects, 2008, p. 170-173Conference paper (Refereed)
    Abstract [en]

    This work is focused on frequency domain electrical characterization of ink-jet printed coplanar waveguides (CPWs). The waveguides were designed and printed using conductive nano-silver ink at room temperature and sintered at 300 degrees C. Distributed models, dependent on frequency, have been developed and some relevent parameters such as impedance, attenuation, are derived over frequency band from 30 kHz to 6 GHz. Two different widths of ground planes are investigated to examine the effects on CPW high frequency behaviors. In addition to these the obtained parameters have been compared and validated by theoretical calculations and momentum simulations.

  • 275.
    She, Huimin
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Network-Calculus-based Performance Analysis for Wireless Sensor Networks2009Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Recently, wireless sensor network (WSN) has become a promising technologywith a wide range of applications such as supply chain monitoringand environment surveillance. It is typically composed of multiple tiny devicesequipped with limited sensing, computing and wireless communicationcapabilities. Design of such networks presents several technique challengeswhile dealing with various requirements and diverse constraints. Performanceanalysis techniques are required to provide insight on design parametersand system behaviors.

    Based on network calculus, we present a deterministic analysis methodfor evaluating the worst-case delay and buffer cost of sensor networks. Tothis end, three general traffic flow operators are proposed and their delayand buffer bounds are derived. These operators can be used in combinationto model any complex traffic flowing scenarios. Furthermore, the methodintegrates a variable duty cycle to allow the sensor nodes to operate at lowrates thus saving power. In an attempt to balance traffic load and improveresource utilization and performance, traffic splitting mechanisms areintroduced for mesh sensor networks. Based on network calculus, the delayand buffer bounds are derived in non-splitting and splitting scenarios.In addition, analysis of traffic splitting mechanisms are extended to sensornetworks with general topologies. To provide reliable data delivery in sensornetworks, retransmission has been adopted as one of the most popularschemes. We propose an analytical method to evaluate the maximum datatransmission delay and energy consumption of two types of retransmissionschemes: hop-by-hop retransmission and end-to-end retransmission.

    We perform a case study of using sensor networks for a fresh food trackingsystem. Several experiments are carried out in the Omnet++ simulationenvironment. In order to validate the tightness of the two bounds obtainedby the analysis method, the simulation results and analytical results arecompared in the chain and mesh scenarios with various input traffic loads.From the results, we show that the analytic bounds are correct and tight.Therefore, network calculus is useful and accurate for performance analysisof wireless sensor network.

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  • 276.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, D.
    Deterministic Worst-case Performance Analysis for Wireless Sensor Networks2008In: Proceedings of the International Wireless Communications and Mobile Computing Conference, 2008, p. 1081-1086Conference paper (Refereed)
    Abstract [en]

    Dimensioning wireless sensor networks requires formal methods to guarantee network performance and cost in any conditions. Based on network calculus, this paper presents a deterministic analysis method for evaluating the worst-case performance and buffer cost of sensor networks. To this end, we introduce three general traffic flow operators and derive their delay and buffer bounds. These operators are general because they can be used in combination to model any complex traffic flowing scenarios in sensor networks. Furthermore, our method integrates variable duty cycle to allow the sensor nodes to operate at lower rates thus saving power. Moreover, it incorporates traffic splitting mechanisms in order to balance network workload and nodes' buffers. To show how our method applies to real applications, we conduct a case study on a fresh food tracking application, which monitors the food freshness in realtime. The experimental results demonstrate that our method can be either used to perform network planning before deployment, or to conduct network reconfiguration after deployment.

  • 277.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    A Network-based System Architecture for Remote Medical Applications2007In: Proceedings of the Asia-Pacific Advanced Network Meeting, 2007Conference paper (Refereed)
    Abstract [en]

    Nowadays, the evolution of wireless communication and networktechnologies enables remote medical services to be availableeverywhere in the world. In this paper, a network-based systemarchitecture adopting wireless personal area network (WPAN)protocol IEEE 802.15.4/Zigbee standard and 3G communicationnetworks for remote medical applications is proposed. In theproposed system, the number and type of medical sensors arescalable depending on individual needs. This feature allows thesystem to be flexibly applied in several medical applications.Furthermore, a differentiated service using priority scheduling anddata compression is introduced. This scheme can not only reducetransmission delay for critical physiological signals and enhancebandwidth utilization at the same time, but also decrease powerconsumption of the hand-held personal server which uses batteryas the energy source.

  • 278.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    Analysis of Traffic Splitting Mechanisms for 2D Mesh Sensor Networks2008In: International Journal of Software Engineering and Its Applications, ISSN 1738-9984, Vol. 2, no 3Article in journal (Refereed)
    Abstract [en]

    For many applications of sensor networks, it is essential to ensure that messages aretransmitted to their destinations within delay bounds and the buffer size of each sensor nodeis as small as possible. In this paper, we firstly introduce the system model of a mesh sensornetwork. Based on this system model, the expressions for deriving the delay bound and bufferrequirement bound are presented using network calculus theory. In order to balance trafficload and improve resource utilization, three traffic splitting mechanisms are proposed. Andthe two bounds are derived in these traffic splitting mechanisms. To show how our methodapplies to real applications, we conduct a case study on a fresh food tracking application,which monitors the food freshness status in real-time during transportation. The numericalresults show that the delay bound and buffer requirement bound are reduced while applyingtraffic splitting mechanisms. Thus the performance of the whole sensor network is improvedwith less cost.

  • 279.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    Traffic splitting with network calculus for mesh sensor networks2007In: Proceedings of Future Generation Communication and Networking, FGCN 2007, IEEE Computer Society, 2007, p. 371-376Conference paper (Refereed)
    Abstract [en]

    In many applications of sensor networks, it is essential to ensure that messages are transmitted to their destinations as early as possible and the buffer size of each sensor node is as small as possible. In this paper, we firstly propose a mesh sensor network system model. Based on this system model, the expressions for deriving the delay bound and buffer requirement bound are presented using network calculus. In order to balance traffic load and improve resource utilization, three traffic splitting mechanisms are proposed The numerical results show that the delay bound and buffer requirement bound are lowered while applying those traffic splitting mechanisms. And thus the performance of the whole sensor network is improved.

  • 280.
    She, Huimin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhou, Dian
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks2009In: 2009 IEEE VEHICULAR TECHNOLOGY CONFERENCE, 2009, p. 38-42Conference paper (Refereed)
    Abstract [en]

    Retransmission has been adopted as one of the most popular schemes for improving transmission reliability in wireless sensor networks. Many previous works have been done on reliable transmission issues in experimental ways, however, there still lack of analytical techniques to evaluate these solutions. Based on the traffic model, service model and energy model, we propose an analytical method to analyze the delay and energy metrics of two categories of retransmission schemes: hop-by-hop retransmission (HBH) and end-to-end retransmission (ETE). With the experiment results, the maximum packet transfer delay and energy efficiency of these two scheme are compared in several scenarios. Moreover, the analytical results of transfer delay are validated through simulations. Our experiments demonstrate that HBH has less energy consumption at the cost of lager transfer delay compared with ETE. With the same target success probability, ETE is superior on the delay metric for low bit-error-rate (BER) cases, while HBH is superior for high BER cases.

  • 281.
    Shen, Meigen
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Concurrent chip and package design for radio and mixed-signal systems2005Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to explore the new design space and opportunities for System-on-Package (SoP), with special attention on radio and mixed-signal system applications. Global level system partitioning for SoC and SoP with cost-performance trade-off, concurrent chip and design for high-speed off-chip signaling, global clock distribution, and ultra wideband (UWB) radio module are two fields in this research.

    Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first addressed in this thesis. We develop a modeling technique to pre-estimate the cost and performance. The performance model evaluates various noise isolation technologies, such as using guard rings, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints.

    System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in this part. First we explore the interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitics are set up and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of package. After that, bandwidth and noise of the signal channel are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. We also analyzed the global clock distribution using co-design method.

    We developed a low cost, low power consumption, and low complexity UWB radio module using co-design method and SoP technologies. The module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensors networks (WSN). Liquid-crystal-polymer (LCP) based SoP technologies were used to implement the module.

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  • 282.
    Shen, Meigen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Koivisto, Tero
    Peltonen, Teemu
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tjukanoff, Esa
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    UWB radio module design for wireless intelligent systems-form specification to implementation2005Conference paper (Refereed)
    Abstract [en]

    In this paper, we designed an impulse-based ultra wideband (UWB) radio module (low band) for wireless intelligent system applications such as radio frequency identification (RFID) and wireless sensor networks (WSN). The UWB radio module includes transceiver block, baseband process unit and power management block. The transceiver circuits include Gaussian pulse generator, wideband low noise amplifier (LNA), multiplier, integrator and timing circuits, which use 0.18mum, 1P6M CMOS technology. The wideband LNA has a power gain of 10dB and minimum noise figure of 2.7dB. For UWB transceiver, the power consumption of transmitter is lower than 1mW while the receiver is about 23mW. The liquid-crystal-polymer (LCP)-based system-on-package (SoP) technology is used to implement the UWB radio module for low power, low cost and small size

  • 283.
    Shen, Meigen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Koivisto, Tero
    Peltonen, Teemu
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tjukanoff, Esa
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    UWB radio module design for wireless sensor networks2005In: Norchip 2005, Proceedings, 2005, p. 184-187Conference paper (Refereed)
    Abstract [en]

    In this paper, we have designed an impulse-based ultra wideband (UWB) radio module for wireless sensor networks (WSN) applications. The UWB radio module includes transceiver block, baseband process unit and power management block. The transceiver block includes Gaussian pulse generator, wideband low noise amplifier (LNA), multiplier, integrator and timing circuits, which use 0.18um, 1P6M CMOS technology. The wideband LNA has a power gain of 10dB and minimum noise figure of 2.7dB. For transceiver block, the power consumption of transmitter is lower than 1mW while the receiver is about 23mW. The liquid-crystal-polymer (LCP)-based System-on-Package (SoP) technology will be used to implement the UWB radio module for low power, low cost and small size.

  • 284.
    Shen, Meigen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Liu, Jian
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tjukanoff, Esa
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Robustness enhancement through chip-package co-design for high-speed electronics2005In: Microelectronics Journal, ISSN 0959-8324, Vol. 36, no 9, p. 846-855Article in journal (Refereed)
    Abstract [en]

    The low interaction between chip and package design has an increasingly limiting effect on the system performance. In this paper, the chip-package co-design flow is presented. We address robustness enhancement under the package and interconnection constraints as well as process, voltage, and temperature (PVT) variations by using impedance control, optimal pins assignment and transmitter equalization. From the simulation results we find that without on-chip digital compensation circuit, the variation of the driver's output impedance is 37% under different PVT conditions. However, it is only 5% when digital compensation circuit is used. Through optimal pins assignment the effective inductance of the pins is reduced. When power and ground pins are used as shielding pins, crosstalk is also decreased by 10 dB. Transmitter equalization effectively decreases inter-symbol interference caused by interconnection attenuation and dispersion. In our design example we find that without equalization the eye-diagram is almost closed at the receiver end. On the other hand with one-tap pre-emphasis equalization the eye-diagram is open and has a height of 90 mV and a width of 140 ps. It is also found that there is a clear optimal window for high data rate in this design. Without a chip-package co-design such an optimal window will not be found.

  • 285.
    Shen, Meigen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tjukanoff, E.
    Isoaho, J.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Concurrent chip package design for global clock distribution network using standing wave approach2005Conference paper (Refereed)
    Abstract [en]

    As a result of the continuous downscaling of CMOS technology, on chip frequency for high performance microprocessors will soon reach 10 GHz, according to the international technology roadmap for semiconductors (ITRS). A 10 GHz global clock distribution network using a standing wave approach is analyzed on the chip and package levels. On the chip level, a 10 GHz standing wave oscillator (SWO) for a global clock distribution network, using 0.18 /spl mu/m IP6M CMOS technology, is designed and analyzed. Simulation results show that skew is well controlled (about 1 ps), while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On the package level, we assume that the chip size is 20/spl times/20 mm/sup 2/ and flip-chip bonding technology is used. Simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of /spl tau//sub clk/ when the attenuation is about 1.5 dB. For attenuation from 1.5 dB to 6.7 dB, the peak positions (n/spl lambda//2) can be used as clock nodes. For the mesh and plane shape, the skew is controlled within 10% of /spl tau//sub clk/ using the standing wave method.

  • 286.
    Shen, Meigen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tjurkanoff, Esa
    Isoaho, Jouni
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Concurrent chip-package design for 10GHz global clock distribution network2005In: 55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings, 2005, p. 1554-1559Conference paper (Refereed)
    Abstract [en]

    As a result of the continuous downscaling of the CMOS technology, on chip frequency for high performance microprocessor will soon arrive 10GHz according to international technology roadmap for semiconductors (ITRS). In this paper, a 10GHz global clock distribution network using standing wave approach was analyzed on chip and package level. On chip level, a 10GHz standing wave oscillator (SWO) for global clock distribution network using 0.18um, 1P6M CMOS technology, is designed and analyzed. The simulation results show that the skew is well controlled (about 1ps) while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On package level, we assume that the chip size is 20mm*20mm and flip-chip bonding technology is used. The simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of tau(clk) when the attenuation is about 1.5dB. For attenuation from 1.5dB to 6.7dB, the peak positions (n*lambda/2) can be used as clock node. For the mesh and plane shape, the skew is controlled within 10% of tau(clk) using standing wave method.

  • 287.
    Signell, Svante
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    ADDA - A versatile development platform for AD and DA-converters2007In: 2007 Norchip, 2007, p. 104-107Conference paper (Refereed)
    Abstract [en]

    ADDA is a versatile development platform for AD-and DA- converters. It contains performance analysis algorithms for converters enabling the user to characterise converters and create data-sheets. The converters characterised are either simulated or real products. Currently characterisation and modelling of Nyquist converters are included with delta-sigma converters to follow in a future release. The platform, written in C-language, is free software released with the Gnu General Public License (GPL) and is freely available for all parties interested to contribute with models, analysis methods or measurement setups. New models of converters are easily included in the platform following included templates and the instructions in the README.

  • 288.
    Signell, Svante
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Huang, Jinliang
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A matlab/octave simulation workbench for multi-antenna software defined radio2006In: 24th Norchip Conference, Proceedings / [ed] Johansson, T, IEEE , 2006, p. 145-148Conference paper (Refereed)
    Abstract [en]

    The current paper describes a generic workbench for multiple antennas Software Defined Radio (SDR) system in Matlab or Octave. The workbench is functionally modularized and make use of parameter lists for reconfiguration. Currently, it supports both narrow band MIMO systems and OFDM-based wideband systems with single or multiple antennas. It could also be easily extended to accommodate other wireless or wireline standards, such as GSM, WCDMA, xDSL, DVB-x, Wimax, Bluetooth, etc.

  • 289.
    Signell, Svante
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Huang, Jinliang
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A simulation environment for multi-antenna Software Defined Radio2007In: 2007 6th International Conference on Information, Communications and Signal Processing, Vols 1-4, 2007, p. 1328-1331Conference paper (Refereed)
    Abstract [en]

    This paper describes a generic simulation workbench for multiple antenna Software Defined Radio (SDR) systems in MATLAB or OCTAVE, for both Windows and Unix/Linux operating systems. The workbench is functionally modularized into blocks and sub-blocks with a common interface for the convenience of modification and reconfiguration. Currently, it accommodates a variety of transmission schemes, including single-carrier multiple-input multiple-output (MIMO), Orthogonal Frequency-Division Multiplexing (OFDM), multi-carrier MIMO, Wideband Code Division Multiple Access (WCDMA), filtered multitone (FMT), which have extensive applications in modern communication technologies, e.g., WLAN 802.11 a/b/g/n, WiMAX, UWB, 3G cellular network, ADSL, DVB, etc.

  • 290.
    Signell, Svante
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Shaber, Mezbah Uddin
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    High-speed pipelined DAC architecture using Gray coding2006In: 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, NEW YORK, NY: IEEE , 2006, p. 113-116Conference paper (Refereed)
    Abstract [en]

    This work describes a new architecture suitable for wide-band Digital to Analog Converters (DACs) for System-on-Chip. The architecture use a switched capacitor pipelined D/A converter design with selection inversion based on Gray coded bits. A 95dB DC-gain fully differential folded cascode gain-boosted OTA to be used in each pipelined DAC bit cell has been designed. Two bit Switched-Capacitor cells have been analysed, one amplifier offset-compensated version and one high-speed version. High linearity up to 64dB SFDR is achieved for a 1MHz input sine wave at a 10MHz update frequency of the first DAC bit cell and 20MHz update frequency for the second DAC bit cell. The speed limiting factor is the switch sizes, not the amplifier bandwidths.

  • 291.
    Sleiman, Sleiman Bou
    et al.
    Ohio State Univ, Analog VLSI Lab.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Wide-Division-Range High-Speed Fully Programmable Frequency Divider2008In: 2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, NEW YORK: IEEE , 2008, p. 17-20Conference paper (Refereed)
    Abstract [en]

    This paper presents the design and implementation of an all-programmable frequency divider with an ultra-wide division range for use in Phase-Locked Loops. The proposed divider uses a fully modular architecture and dynamic logic - implemented in TSMC 0.18 mu m - and can divide input frequencies up to 7.55GHz by any ratio between 8 and 255 while consuming 11mW from a 1.8V power supply. The divider compares very favorably to other implementations reported in literature in terms of division range and frequency of operation.

  • 292.
    Srinivasar, Sandeep Kowlgi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ultra-low power 2.4 GHz CMOS receiver front-end for sensor nodes2007In: 2007 European Conference On Circuit Theory And Design: Vols 1-3, 2007, p. 595-598Conference paper (Refereed)
    Abstract [en]

    This paper presents a fully integrated receiver front-end for a 2.4GHz RF transceiver. A system level design for the radio front end for which these components are designed is also presented. The proposed receiver front end (Low-Noise Amplifier, Single-to-Differential Converter and Mixer) is based on a direct conversion architecture designed in 0.18 mu m CMOS technology. It takes advantage of on-chip single to differential signal conversion to avoid the use of cost intensive off-chip balun and external passives. The post layout simulations of front end show that the RF front-end achieves a voltage gain of 8dB without the baseband amplifier, a noise figure of 8.9 dB and IIP3 better than -15 dBm. The flicker noise corner is less than 10 KHz, with a nominal DC offset. It consumes less than 1.6 mA from a 1.8V supply.

  • 293.
    Strak, Adain
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Analysis of timing jitter in inverters induced by power-supply noise2006In: IEEE DTIS: 2006 International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Proceedings / [ed] Girard, P; Masmoudi, M; Mouine, J; Renovell, M, 2006, p. 53-56Conference paper (Refereed)
    Abstract [en]

    This paper describes the transformation process of power-supply noise (PSN) to timing jitter of inverters. The focus is on the inverters used in multiphase clock-generator circuits (CGCs) commonly needed for Switched-Capacitor (SC) SigmaDelta (E-A) Analog-to-Digital Converters (ADCs). Closed form expressions relating timing jitter and PSN are presented and the results are compared with Monte-Carlo simulations performed in Spectre at 13SEN13-6 transistor model level using the processes ANIS 0.351im and UMC 0.18 mu m. The PSN is assumed to have a white frequency distribution with independent power and ground noise. The results show that the transformation process is approximately linear and that the jitter impact decreases as transistors move deeper into the submicron domain. Furthermore, the transformation process is not symmetrical and is dependent on switching direction, even if the PMOS and NMOS sizings are such that the effects due to difference in hole and electron mobility are mitigated.

  • 294.
    Strak, Adam
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Timing Uncertainty in Sigma-Delta Analog-to-Digital Converters2006Doctoral thesis, monograph (Other scientific)
    Abstract [en]

    This dissertation presents an investigation of the causes and effects of timing uncertainty in Sigma-Delta Analog-to-Digital Converters, with special focus on the switched-capacitor Sigma-Delta type. The investigated field for cause of timing uncertainty is digital clock generation and the field for effect is sampling. The granularity level of the analysis in this work begins at behavioral level and finishes at transistor level.

    The sampling circuit is the intuitive component to look for the causes to the effects of timing uncertainty in an Analog-to-Digital Converter since the transformation from real time to digital time takes place in the sampling circuit. Hence, the performance impact of timing uncertainties in a typical sampling circuit of a switched-capacitor Sigma-Delta Analog-to-Digital Converter has been thoroughly analysed, modelled, and described in this dissertation. During the analysis process, ideas of improved sampling circuits with inherent tolerance to timing uncertainties were conceived and analysed, and are also presented. Two cases of improved sampling topologies are presented: the Parallel Sampler and the Sigma- Delta sampler. The first obtains its timing uncertainty tolerance from taking advantage of a theorem in statistics whereas the second is tolerant against timing uncertainties because of spectral shaping that effectively pushes the in-band timing noise out of the signal band.

    Digital clock generation is a fundamental step of generating multiple clock signals that are needed for example in switched-capacitor versions of Sigma-Delta Analog-to-Digital Converters. The clock generation circuitry converts a single time reference, i.e. a clock signal, usually coming from a phase-locked loop into multiple time references. The two types of clock-generation circuits that are treated in this dissertation are used to create two nonoverlapping clocks from a single clock signal. The process that has been investigated and described is how power-supply noise and substrate noise transforms into timing uncertainty when a reference signal is passed through one of the aforementioned clock generation circuits.

    The results presented in this dissertation have been obtained using different analysis techniques. The modelling and descriptions have been done from a mathematical and physical perspective. This has the benefit of predicting the performance impact by different circuit parameters without the need for computer based simulations. The difficulty with the mathematical and physical modelling is the balance that has to be found between intractability and oversimplification. The other angle of approach has been the use of computer based simulations for both description and verification purposes. The simulation tools that have been used in this work are MATLAB and Spectre/Cadence. As mentioned, their purpose has been both for model and description verification and also as a means of obtaining result metrics. Generally speaking, simulation tools mentally decouple the result from the various circuit parameters and reaching a solid performance understanding can be difficult. However, obtaining a performance metric without full comprehension can at times be better than having no metric at all.

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  • 295. Strak, Adam
    et al.
    Gothenberg, Andreas
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Power-supply and substrate noise-induced timing jitter in nonoverlapping clock generation circuits2008In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, ISSN 1549-8328, Vol. 55, no 4, p. 1041-1054Article in journal (Refereed)
    Abstract [en]

    This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mu m CMOS process parameters, and a reference simulation in 0.18 mu m is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mu m process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.

  • 296.
    Strak, Adam
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Investigation of timing jitter in NAND and NOR gates induced by power-supply noise2006In: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, p. 1160-1163Conference paper (Refereed)
    Abstract [en]

    This paper analyses power-supply noise induced timing variations in NAND and NOR logical blocks. The focus of this work is on the NAND and NOR blocks used in nonoverlapping clock generation circuits used for switched capacitor sigma-delta analog-to-digital converters. Monte-Carlo simulations performed in Spectre at BSIM3v3 transistor model level using parameters from two manufacturing processes, 0.35 mu m and 0.18 mu m, are presented. The power-supply noise is assumed to have a gaussian amplitude distribution with independent power and ground noise. The results show that the timing jitter dependency on power-supply noise has a low-pass frequency characteristic and is approximately linear as we have previously shown for the inverter case. Furthermore, the jitter impact decreases as transistors move deeper into the submicron domain and for comparable transistor sizings, NAND blocks have a lower timing sensitivity to PSN compared with NOR blocks.

  • 297.
    Strak, Adam
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Power-supply noise attributed timing jitter in nonoverlapping clock generation circuits2006Conference paper (Refereed)
    Abstract [en]

    This work describes an analysis of timing jitter induced by power-supply noise in nonoverlapping clock generation circuits typically used in switched-capacitor sigma-delta modulators. Substrate noise effects are also included but not treated as a separate phenomenon since the MOSFET bulk contacts are connected to the power-supply or ground. Two different nonoverlapping clock generation circuits have been compared and treated independently: the NOR based and the NAND based architectures. Furthermore, all possible connection topologies of the circuit blocks in the clock generation circuits are investigated. Monte Carlo simulations have been performed in Spectre at BSIM3v3 transistor model level using parameters from a 0.18μm process to show which of the topologies is most suitable as clock generator for wideband applications. In terms of timing jitter sensitivity to power-supply noise, the NOR based architecture is slightly more robust and suitable for providing a timing reference to a sampling circuit.

  • 298.
    Sun, Yi-Ran
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Signell, Svante
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Generalized bandpass sampling with complex FIR filtering2006In: 2006 IEEE Asia Pacific Conference on Circuits and Systems, NEW YORK: IEEE , 2006, p. 1035-1038Conference paper (Refereed)
    Abstract [en]

    In this paper, Generalized Quadrature BandPass Sampling (GQBPS) with complex FIR filtering is studied with respect to both noise and jitter. GQBPS is a type of nonuniform sampling, and has been extended to Generalized Uniform BandPass Sampling (GUBPS). It is shown that GQBPS and GUBPS with complex FIR filtering perform both down-conversion and noise aliasing suppression in addition to sampling. Due to the averaging operation of FIR filtering, sampling jitter is also reduced to a certain degree by GQBPS and GUBPS. However, the performance by GQBPS is limited by the maximum effective sampling rate determined by the fixed time resolution of the sampling scheme. In contrast GUBPS avoids this problem.

  • 299.
    Sun, Yiran
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Signell, Svante
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Implementation aspects of generalized bandpass sampling2007In: 15th European Signal Processing Conference (EUSIPCO 2007), 2007, p. 1975-1979Conference paper (Refereed)
    Abstract [en]

    BandPass Sampling (BPS) realizes frequency down-conversion in radio receiver front-ends by a sampling rate that can be slightly larger than twice the information bandwidth compared to twice the highest frequency for traditional LowPass Sampling (LPS). However, some implementation problems, harmful signal spectral folding, noise aliasing and sampling jitter, are unavoidably present in conventional BPS systems. Under recent research, generalized bandpass sampling combined with filtering has been proposed for dealing with these problems. In this paper, the novel sampling architectures with intrinsic FIR and IIR filtering are implemented using a sampled-data technique called Switched-Capacitor (SC) circuit technique. Specifically complex SC filtering is designed and analyzed. Both the analysis and simulation results show that the designed complex SC filter fulfils the expectations of generalized bandpass sampling.

  • 300.
    Sun, Yi-Ran
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Signell, Svante
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Implementation of generalized uniform bandpass sampling with complex FIR and IIR filtering2007In: 2007 European Conference On Circuit Theory And Design: Vols 1-3, 2007, p. 476-479Conference paper (Refereed)
    Abstract [en]

    BandPass Sampling (BPS) realizes frequency down-conversion in radio receiver front-ends by a sampling rate that can be slightly larger than twice the information bandwidth compared to twice the highest frequency for traditional LowPass Sampling (LPS). However, some implementation problems, harmful signal spectral folding, noise aliasing and sampling jitter, are unavoidably present in conventional BPS systems. Under recent research, generalized bandpass sampling combined with filtering has been proposed for dealing with these problems. In this paper, the novel sampling architectures with intrinsic filtering are implemented using a sampled-data technique called Switched-Capacitor (SC) circuit technique. Specifically complex SC filtering is designed and analyzed. Both the analysis and simulation results show that the designed complex SC filter fulfils the expectations of generalized bandpass sampling.

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