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  • 101.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodriguez Duenas, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Device Modelling for 60 GHz Radio Front-ends in 65 nm CMOS2009In: 2009 NORCHIP, 2009Conference paper (Refereed)
    Abstract [en]

    This paper presents an electromagnetic simulation-based modelling solution for active and passive devices which targets 60 GHz front-end integrated circuits. An EM model, using existing transistor compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on EM simulation S-parameter data is also derived. The models are process and layout dependent, which have been verified by the design of a low noise amplifier in a 60 GHz radio front-end.

  • 102.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A 60 GHz receiver front-end in 65 nm CMOS2011In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 67, no 1, p. 61-71Article in journal (Refereed)
    Abstract [en]

    In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of -13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm x 0.44 mm.

  • 103. Tarim, T. B.
    et al.
    Ismail, Mohammed
    Robust design of low power CMOS analogue integrated circuits2001In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 148, no 4, p. 197-204Article in journal (Refereed)
    Abstract [en]

    As feature sizes move into the deep submicron ranges and power supply voltages are reduced, the effect of both device mismatch and inter-die process variations on the performance and reliability of analogue integrated circuits is magnified. The statistical MOS (SMOS) model accounts for both inter-die and intra-die variations. A low power analogue CMOS square-law cell, and a new transconductor and multiplier using this cell as the main budding block, are presented in the paper. The paper focuses on the robust design of the transconductor and multiplier circuits. The circuits operate in the saturation region with fully balanced input signals. Initial circuit simulation results are given. Response surface methodology and design of experiment techniques were used as statistical VLSI design techniques combined with the SMOS model. Device size optimisation and yield enhancement are demonstrated.

  • 104. Tarim, T. B.
    et al.
    Ismail, Mohammed
    Statistical design of a 10 bit current division network2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 29, no 3, p. 221-229Article in journal (Refereed)
    Abstract [en]

    The statistical design of the 10 bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in the circuit is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuit is fabricated through the MOSIS 2 mum process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.

  • 105. Tarim, T. B.
    et al.
    Ismail, Mohammed
    Statistical design of the four-MOSFET structure2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 28, no 1, p. 115-121Article in journal (Refereed)
    Abstract [en]

    The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor W and L values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 mum process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.

  • 106. Tarim, T. B.
    et al.
    Ismail, Mohammed
    Kuntman, H. H.
    Robust design and yield enhancement of low-voltage CMOS analog integrated circuits2001In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 48, no 4, p. 475-486Article in journal (Refereed)
    Abstract [en]

    Basic CMOS low-voltage analog cells are introduced and used in the design of low-voltage CMOS multipliers, A statistical design flow for enhancing the parametric functional yield of these low-voltage circuits, with the goal of achieving a robust performance,is described. The design flow is based on using the response surface methodology (RSM) and design of experiment (DOE) techniques as statistical VLSI design techniques together with the statistical MOS (SMOS) model. Offset and nonlinearity performances are statistically examined. The response surfaces show the trade-off between area and functional yield. Using these surface contours, the designer will be able to estimate the functional yield of the circuits before fabrication. The contours are also used in the statistical optimization of device sizes as they provide information regarding which transistor aspect ratios are to be altered to achieve a better functional yield.

  • 107. Tarim, T. B.
    et al.
    Kuntman, H. H.
    Ismail, Mohammed
    Statistical design of low power square-law CMOS cells for high yield2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 23, no 3, p. 237-248Article in journal (Refereed)
    Abstract [en]

    A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.

  • 108. Wu, Y.
    et al.
    Ding, X. H.
    Ismail, Mohammed
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    RF bandpass filter design based on CMOS active inductors2003In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 50, no 12, p. 942-949Article in journal (Refereed)
    Abstract [en]

    In this paper, a second-order RF bandpass filter based on active inductor has been implemented in a 0.35 mum CMOS process. Issues related to the intrinsic quality factor and dynamic range of the CMOS active inductor are addressed. Tuned at 900 MHz with Q=40, the filter has 28-dB spurious-free-dynamic-range (SFDR) and total current consumption (including buffer stage) is 17 mA with 2.7-V power supply. Experimental results also show the possibility of using them to build higher order RF filter and voltage-controlled oscillator (VCO).

  • 109. Wu, Y.
    et al.
    Ding, X.
    Ismail, Mohammed
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Inductorless CMOS RF bandpass filter2001In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 37, no 16, p. 1027-1029Article in journal (Refereed)
    Abstract [en]

    The design and experimental results of a novel CMOS RF filter are presented, Employing a pair of current-reused active inductors. a differential second-order bandpass filter working at 900 M Hz with Q = 41 has been implemented in a 0.35 mum CMOS process.

  • 110. Wu, Y.
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A SiGeHBT translinear harmonic mixer2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 31, no 1, p. 65-67Article in journal (Refereed)
    Abstract [en]

    A novel even-order harmonic mixer is proposed. Based on the translinear loop of BJT/HBTs, frequency doubling and single-to-differential conversion circuits have been employed in the design of harmonic mixer. The proposed mixer has been verified in a SiGe HBT process by SpectreRF simulations.

  • 111. Wu, Y.
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    CMOS VHF/RF CCO based on active inductors2001In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 37, no 8, p. 472-473Article in journal (Refereed)
    Abstract [en]

    A novel CMOS current controlled oscillator (CCO) is proposed, Based on the current-reused active inductors, a differential oscillator has been designed and fabricated. Measurement results show that it has very wide tuning-range and reasonable phase-noise performance.

  • 112. Wu, Y.
    et al.
    Shi, C. L.
    Ding, X. H.
    Ismail, Mohammed
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Design of CMOS VHF/RF biquadratic filters2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 33, no 3, p. 239-248Article in journal (Refereed)
    Abstract [en]

    In this paper, a class of CMOS biquadratic filter suitable to work at VHF/RF frequency range is presented. The proposed circuit has a simple structure which is analyzed and designed according to a universal G(m)-C biquad filter. Simulation and experimental results show that these filters can work in GHz range and have wide tuning range.

  • 113. Yoo, S. J.
    et al.
    Ismail, Mohammed
    A highly linear CMOS baseband chain for wideband wireless applications2004In: ETRI Journal, ISSN 1225-6463, E-ISSN 2233-7326, Vol. 26, no 5, p. 486-492Article in journal (Refereed)
    Abstract [en]

    The emergence of wide channel bandwidth wireless standards requires the use of a highly linear, wideband integrated CMOS baseband chain with moderate power consumption. In this paper, we present the design of highly linear, wideband active RC filters and a digitally programmable variable gain amplifier. To achieve a high unity gain bandwidth product with moderate power consumption, the feed-forward compensation technique is applied for the design of wideband active RC filters. Measured results from a 0.5 mum CMOS prototype baseband chain show a cutoff frequency of 10 MHz, a variable gain range of 33 dB, an in-band IIP3 of 13 dBV, and an input referred noise of 114 muVrms while dissipating 20 mW from a 3 V supply.

  • 114. Younus, M. D. I.
    et al.
    Ismail, Mohammed
    Phase calibration technique for mismatch optimization in image-reject receivers2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 46, no 2, p. 165-168Article in journal (Refereed)
    Abstract [en]

    This paper presents phase calibration technique without using any external tone for weaver image-reject receiver. Error signal (phase mismatch information) is generated using a simple algorithm and this signal is used for mismatch elimination. Calibration system has been implemented using simulink which shows an image rejection ratio of 59.5 dB can be achieved for RF signal operating at 1.8 GHz.

  • 115. Zhang, Ling
    et al.
    Kim, Hyung Joon
    Nadig, Vinay
    Ismail, Mohammed
    A 1.8 V tri-mode Sigma Delta modulator for GSM/WCDMA/WLAN wireless receiver2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 3, p. 323-341Article in journal (Refereed)
    Abstract [en]

    The next generation of cellular systems will be increasingly similar to a data communication system. Not only will it transfer voice and multimedia data, it will also be integrated with WLAN to access Internet whenever possible. Thus these cellular systems need highly integrated multi-standard receivers. The design of the A/D converter in such receivers is a big challenge. A GSM/WCDMA/WLAN tri-mode receiver is first designed on the system level. A reconfigurable Sigma Delta modulator, which is suitable for GSM/WCDMA/WLAN receiver, is then proposed in this paper. According to the different signal bandwidth and Dynamic Range (DR) specifications, this Sigma Delta modulator is reconfigured to achieve the required dynamic range with less power consumption. The prototype is implemented in TSMC 0.18-mu m CMOS process with 1.8 V power supply. The circuit achieves signal-to-noise-and-distortion-ratio of 82 dB for GSM, 75 dB for WCDMA and 58 dB for WLAN.

  • 116.
    Zhao, Kangqiao
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Amir, Saifullah
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Meng, Xiaozhou
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ali, Muhammad Mohsin
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Gustafsson, Martin
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A reconfigurable successive approximation ADC in 0.18μm CMOS technology2008In: 15th IEEE International Conference on Electronics, Circuits and Systems, 2008. ICECS 2008, IEEE conference proceedings, 2008, p. 646-649Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of a reconfigurable successive approximation analog to digital converter (ADC) for both ultra wideband and Bluetooth applications. The behavioral level design is presented along with the circuit implementation. The ADC architecture employs a split capacitor array DAC which reduces the power consumption. The ADC is implemented in a 0.18mum CMOS process and circuit level simulation results show that the ADC can achieve 28.9 dB SINAD at 66 MSPS in the UWB mode, and 53.9 dB SINAD at 1 MSPS in the Bluetooth mode.

  • 117.
    Zhao, Zongyang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Vertical handover for 4G multi-standard wireless transceivers2007In: 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS: VOLS 1-4, 2007, p. 1356-1359Conference paper (Refereed)
    Abstract [en]

    Future best-connected wireless solutions will involve a multitude of network standards between which the user can switch in order to optimize a set of benefits such as cost and performance. As a result of this convergence, the hardware design of the mobile device will require knowledge about the restrictions imposed by the upper networking layers. This paper starts by presenting the requirements for the connection initialization in the WLAN, WiMAX and 3G standards as they pertain to the mobile transceiver design. It is assumed that the mobile device is based on the dual front-end transceiver architecture where the primary transceiver handles the current network connection while the secondary transceiver (Sniffer) searches for an alternative connection. The paper also presents the handover procedures between these standards that will provide, among other things, the timing requirements for the circuit design.

123 101 - 117 of 117
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