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  • 1.
    Feng, Chaochao
    et al.
    National University of Defense Technology, China.
    Lu, Zhonghai
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zhang, Minxuan
    A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip2012Inngår i: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E95D, nr 5, s. 1519-1522Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 7 x 7 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.

  • 2.
    Feng, Chaochao
    et al.
    National University of Defense Technology, China.
    Lu, Zhonghai
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zhang, Minxuan
    Yang, Xianju
    Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip2012Inngår i: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E95D, nr 4, s. 1052-1061Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper, we propose three Deflection-Routing-based Multicast (DRM) schemes for a bufferless NoC. The DRM scheme without packets replication (DRM_noPR) sends multicast packet through a non-deterministic path. The DRM schemes with adaptive packets replication (DRM_PR_src and DRM_PR_all) replicate multicast packets at the source or intermediate node according to the destination position and the state of output ports to reduce the average multicast latency. We also provide fault-tolerant supporting in these schemes through a reinforcement-learning-based method to reconfigure the routing table to tolerate permanent faulty links in the network. Simulation results illustrate that the DRM_PR_all scheme achieves 41%, 43% and 37% less latency on average than that of the DRM_noPR scheme and 27%, 29% and 25% less latency on average than that of the DRM_PR_src scheme under three synthetic traffic patterns respectively. In addition, all three fault-tolerant DRM schemes achieve acceptable performance degradation at various link fault rates without any packet lost.

  • 3.
    Kleijn, W. Bastiaan
    KTH, Tidigare Institutioner                               , Signaler, sensorer och system.
    Signal processing representations of speech2003Inngår i: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E86D, nr 3, s. 359-376Artikkel, forskningsoversikt (Fagfellevurdert)
    Abstract [en]

    Synergies in processing requirements and knowledge of human speech production and perception have led to a similarity of the speech signal representations used for the tasks of recognition, coding, and modification. The representations are generally composed of a description of the vocal-tract transfer function and, in the case of coding and modification, a description of the excitation signal. This paper provides an overview of commonly used representations. For coding and modification, autoregressive models represented by line spectral frequencies perform well for the vocal tract, and pitch-synchronous filter banks and modulation-domain filters perform well for the excitation. For recognition, good representations are based on a smoothed magnitude response of the vocal tract.

  • 4.
    Larsson, Erik
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Preemptive system-on-chip test scheduling2004Inngår i: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E87D, nr 3, s. 620-629Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.

  • 5. Lind, Kenneth
    et al.
    Heldal, R.
    Comp size: A model-based and automated approach to size estimation of embedded software components2012Inngår i: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E95-D, nr 9, s. 2183-2192Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Accurate estimation of Software Code Size is important for developing cost-efficient embedded systems. The Code Size affects the amount of system resources needed, like ROM and RAM memory, and processing capacity. In our previous work, we have estimated the Code Size based on CFP (COSMIC Function Points) within 15% accuracy, with the purpose of deciding how much ROM memory to fit into products with high cost pressure. Our manual CFP measurement process would require 2.5 man years to estimate the ROM size required in a typical car. In this paper, we want to investigate how the manual effort involved in estimation of Code Size can be minimized. We define a UML Profile capturing all information needed for estimation of Code Size, and develop a tool for automated estimation of Code Size based on CFP. A case study will show how UML models save manual effort in a realistic case.

  • 6.
    Maki, Atsuto
    et al.
    KTH, Skolan för datavetenskap och kommunikation (CSC), Datorseende och robotik, CVAP.
    Uhlin, Tomas
    Disparity Selection in Binocular Pursuit1995Inngår i: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E78-D, nr 12, s. 1591-1597Artikkel i tidsskrift (Fagfellevurdert)
  • 7.
    Nakajima, Masayuki
    Uppsala universitet, Humanistisk-samhällsvetenskapliga vetenskapsområdet, Historisk-filosofiska fakulteten, Institutionen för speldesign. Tokyo Inst Technol, Imaging Sci & Engn Lab, Tokyo, Japan.;Tokyo Inst Technol, Dept Comp Sci, Tokyo, Japan.;Tokyo Inst Technol, Grad Sch Informat Sci & Engn, Tokyo, Japan.;Tokyo Inst Technol, Tokyo, Japan.;Kanagawa Inst Technol, Kanagawa, Japan.;IEICE, Informat & Syst Soc, Oxford, England..
    FOREWORD2016Inngår i: IEICE transactions on information and systems, ISSN 0916-8532, E-ISSN 1745-1361, Vol. E99D, nr 4, s. 1023-1023Artikkel i tidsskrift (Annet vitenskapelig)
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