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  • 351.
    Shah, Ghafoor
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Arslan, Saad
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Design of an in-field Embedded Test Controller2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Electronic systems installed in their operation environments often require regular testing. The nanometer transistor size in new IC design technologies makes the electronic systems more vulnerable to defects. Due to certain reasons like wear out or over heating and difficulty to access systems in remote areas, in-field testing is vital. For in-field testing, embedded test controllers are more effective in terms of maintenance cost than external testers. For in-field testing, fault coverage, high memory requirements, test application time, flexibility and diagnosis are the main challenges.

    In this thesis, an Embedded Test Controller (ETC) is designed and implemented which provides flexible in-field testing and diagnostic capability with high fault coverage. The ETC has relatively low memory requirements for storing deterministic test data as compared to storing complete test vectors. The test patterns used by the ETC are stored separately for each component of the device under test, in system memory. The test patterns for each component are concatenated during test application according to a flexible test command. To address test application time (which corresponds to down time of the system), two different versions of the ETC are designed and implemented. These versions provide a trade off between test application time and hardware overhead. Hence, a system integrator can select which version to use depending on the cost factors at hand. The ETC can make use of an embedded CPU in the Device Under Test (DUT), for performing test on the DUT. For DUTs where no embedded CPU is available, there is the additional cost of a test specific CPU for the ETC. To access the DUT during the test application, the IEEE 1149.1 (JTAG) interface is used. The ETC generates test result that provides information of failing ICs and patterns.

    The designed and implemented versions of the ETC are validated through experimentations. An FPGA platform is used for experimental validation of the ETC versions. A set of tools are developed for automating the experimental setup. Performance and hardware cost of the ETC versions are evaluated using the ITC'02 benchmarks.

  • 352.
    Singh, Virendra
    et al.
    Supercomputer Education and Research Centre SERC Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    On Reduction of Capture Power for Modular System-on-Chip Test2008In: IEEE Workshop on RTL and High Level Testing WRTLT08,2008, 2008Conference paper (Refereed)
    Abstract [en]

      

  • 353.
    Sjölund, Micael
    et al.
    Linköping University, Department of Computer and Information Science, MDALAB - Human Computer Interfaces. Linköping University, The Institute of Technology.
    Larsson, Anders
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Berglund, Erik
    Linköping University, Department of Computer and Information Science, MDALAB - Human Computer Interfaces. Linköping University, The Institute of Technology.
    Smartphone views: Building multi-device distributed user interfaces2004In: Mobile Human-Computer Interaction - MobileHCI 2004: 6th International Symposium, MobileHCI, Glasgow, UK, September 13 - 16, 2004. Proceedings / [ed] Stephen Brewster and Mark Dunlop, Springer Berlin/Heidelberg, 2004, Vol. 3160, 507-511 p.Chapter in book (Refereed)
    Abstract [en]

    This paper introduces a prototype of a distributed user interface (DUI) on dual devices, a workstation and a Windows Mobile-powered smartphone. By porting the XML-compliant GUT system Views to the smartphone platform, we explore one possibility of distributing CUT components among heterogeneous devices. We describe problems and conclusions from designing and implementing the system.

  • 354.
    Subramanyan, Pramod
    et al.
    Indian Institute of Science, Bangalore.
    Jangir, Ram Rakesh
    Government Polytechnic, Hisar.
    Tudu, Jaynarayan T.
    Indian Institute of Science, Bangalore.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore.
    Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation2009In: 7th IEEE East-West Design & Test Symposium (EWDTS), Moscow, Russia, September 18-21, 2009., 2009, 1-4 p.Conference paper (Refereed)
    Abstract [en]

    Technology scaling has caused Negative Bias Temperature Instability (NBTI) to emerge as a major circuit reliability concern. Simultaneously leakage power is becoming a greater fraction of the total power dissipated by logic circuits. As both NBTI and leakage power are highly dependent on vectors applied at the circuit’s inputs, they can be minimized by applying carefully chosen input vectors during periods when the circuit is in standby or idle mode. Unfortunately input vectors that minimize leakage power are not the ones that minimize NBTI degradation, so there is a need for a methodology to generate input vectors that minimize both of these variables.This paper proposes such a systematic methodology for the generation of input vectors which minimize leakage power under the constraint that NBTI degradation does not exceed a specified limit. These input vectors can be applied at the primary inputs of a circuit when it is in standby/idle mode and are such that the gates dissipate only a small amount of leakage power and also allow a large majority of the transistors on critical paths to be in the “recovery” phase of NBTI degradation. The advantage of this methodology is that allowing circuit designers to constrain NBTI degradation to below a specified limit enables tighter guardbanding, increasing performance. Our methodology guarantees that the generated input vector dissipates the least leakage power among all the input vectors that satisfy the degradation constraint.We formulate the problem as a zero-one integer linear program and show that this formulation produces input vectors whose leakage power is within 1% of a minimum leakage vector selected by a search algorithm and simultaneously reduces NBTI by about 5.75% of maximum circuit delay as compared to the worst case NBTI degradation. Our paper also proposes two new algorithms for the identification of circuit paths that are affected the most by NBTI degradation. The number of such paths identified by our algorithms are an order of magnitude fewer than previously proposed heuristics.

  • 355.
    Subramanyan, Pramod
    et al.
    Indian Institute of Science.
    Singh, Virendra
    Indian Institute of Science.
    Saluja, Kewal K.
    University of Wisconsin-Madison.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding2010In: The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10), Fairmont Chicago, Millennium Park, Chicago, Illinois, USA, June 28-July 1, 2010., 2010, 121-130 p.Conference paper (Refereed)
    Abstract [en]

    Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper we introduce a new energy-efficient fault-tolerant CMP architecture known as Redundant Execution using Critical Value Forwarding (RECVF). RECVF is based on two observations: (i) forwarding critical instruction results from the leading to the trailing core enables the latter to execute faster, and (ii) this speedup can be exploited to reduce energy consumption by operating the trailing core at a lower voltage-frequency level. Our evaluation shows that RECVF consumes 37% less energy than conventional dual modular redundant (DMR) execution of a program. It consumes only 1.26 times the energy of a nonfault- tolerant baseline and has a performance overhead of just 1.2%.

  • 356.
    Subramanyan, Pramod
    et al.
    Indian Institute of Science.
    Singh, Virendra
    Indian Institute of Science.
    Saluja, Kewal K.
    University of Wisconsin.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Energy-Efficient Redundant Execution for Chip Multiprocessors2010In: Great Lakes Symposium on VLSI on (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010., New York, USA: ACM , 2010, 143-146 p.Conference paper (Refereed)
    Abstract [en]

    Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.

  • 357.
    Subramanyan, Pramod
    et al.
    Supercomputer Education and Research Center, Indian Institute of Science, Bangalore, India.
    Singh, Virendra
    Supercomputer Education and Research Center, Indian Institute of Science, Bangalore, India.
    Saluja, Kewal K.
    Electrical and Computer Engg. Dept., University of Wisconsin-Madison, Madison, WI, United States.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors2010In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2010, 1572-1577 p.Conference paper (Refereed)
    Abstract [en]

    Continued CMOS scaling is expected to make future micro-processors susceptible to transient faults, hard faults, manufacturing defects and process variations causing fault tolerance to become important even for general purpose processors targeted at the commodity market. Tomitigate the effect of decreased reliability, a number of fault-tolerant architectures have been proposed that exploit the natural coarse-grained redundancy available in chip multiprocessors (CMPs). These architectures execute a single application using two threads, typically as one leading thread and one trailing thread. Errors are detected by comparing the outputs produced by these two threads. These architectures schedule a single application on two cores or two thread contexts of a CMP. As a result, besides the additional energy consumption and performance overhead that is required to provide fault tolerance, such schemes also impose a throughput loss. Consequently a CMP which is capable of executing 2n threads in non-redundant mode can only execute half as many (n) threads in fault-tolerant mode. In this paper we propose multiplexed redundant execution (MRE), a low-overhead architectural technique that executes multiple trailing threads on a single processor core. MRE exploits the observation that it is possible to accelerate the execution of the trailing thread by providing execution assistance from the leading thread. Execution assistance combined with coarse-grained multithreading allows MRE to schedule multiple trailing threads concurrently on a single core with only a small performance penalty. Our results show that MRE increases the throughput of fault-tolerant CMP by 16% over an ideal dual modular redundant (DMR) architecture. © 2010 EDAA.

  • 358.
    Subramanyan, Pramod
    et al.
    Indian Institute of Science, Bangalore.
    Singh, Virendra
    Indian Institute of Science, Bangalore.
    Saluja, Kewal K.
    University of Wisconsin-Madison.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Power Efficient Redundant Execution for Chip Multiprocessors2009In: Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June 29, 2009., 2009, 1-6 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.

  • 359. Subramanyan, Pramod
    et al.
    Singh, Virendra
    Saluja, Kewal
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors2011In: Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2011, 419-426 p.Conference paper (Refereed)
    Abstract [en]

    Relentless scaling of CMOS fabrication technology has made contemporary integrated circuits increasingly susceptible to transient faults, wearout-related permanent faults, intermittent faults and process variations. Therefore, mechanisms to mitigate the effects of decreased reliability are expected to become essential components of future general-purpose microprocessors. In this paper, we introduce a new throughput-efficient architecture for multiplexed fault-tolerant chip multiprocessors (CMPs). Our proposal relies on the new technique of adaptive execution assistance, which dynamically varies instruction outcomes forwarded from the leading core to the trailing core based on measures of trailing core performance. We identify policies and design low overhead hardware mechanisms to achieve this. Our work also introduces a new priority-based thread-scheduling algorithm for multiplexed architectures that improves multiplexed fault tolerant CMP throughput by prioritizing stalled threads. Through simulation-based evaluation, we And that our proposal delivers 17.2% higher throughput than perfect dual modular redundant (DMR) execution and outperforms previous proposals for throughput-efficient CMP architectures.

  • 360.
    Suri, Bharath
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Accelerating the knapsack problem on GPUs2011Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
    Abstract [en]

    The knapsack problem manifests itself in many domains like cryptography, financial domain and bio-informatics. Knapsack problems are often inside optimization loops in system-level design and analysis of embedded systems as well. Given a set of items, each associated with a profit and a weight, the knapsack problem deals with how to choose a subset of items such that the profit is maximized and the total weight of the chosen items is less than the capacity of the knapsack. There exists several variants and extensions of this knapsack problem. In this thesis, we focus on the multiple-choice knapsack problem, where the items are grouped into disjoint classes.

    However, the multiple-choice knapsack problem is known to be NP-hard. While many different heuristics and approximation schemes have been proposed to solve the problem in polynomial-time, such techniques do not return the optimal solution. A dynamic programming algorithm to solve the problem optimally is known, but has a pseudo-polynomial running time. This leads to high running times of tools in various application domains where knapsack problems must be solved. Many system-level design tools in the embedded systems domain, in particular, would suffer from high running when such a knapsack problem must be solved inside a larger optimization loop.

    To mitigate the high running times of such algorithms, in this thesis, we propose a GPU-based technique to solve the multiple-choice knapsack problem. We study different approaches to map the dynamic programming algorithm on the GPU and compare their performance in terms of the running times. We employ GPU specific methods to further improve the running times like exploiting the GPU on-chip shared memory. Apart from results on synthetic test-cases, we also demonstrate the applicability of our technique in practice by considering a case-study from system-level design. Towards this, we consider the problem of instruction-set selection for customizable processors.

  • 361.
    Suri, Bharath
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    A Scalable GPU-Based Approach to Accelerate the Multiple-Choice Knapsack Problem2012In: Design Automation and Test in Europe (DATE12) (short paper), Dresden, Germany, March 12-16, 2012., IEEE , 2012, 1126-1129 p.Conference paper (Refereed)
    Abstract [en]

    Variants of the 0-1 knapsack problem manifest themselves at the core of several system-level optimization problems. The running times of such system-level optimization techniques are adversely affected because the knapsack problem is NP-hard. In this paper, we propose a new GPU-based approach to accelerate the multiple-choice knapsack problem, which is a general version of the 0-1 knapsack problem. Apart from exploiting the parallelism offered by the GPUs, we also employ a variety of GPU-specific optimizations to further accelerate the running times of the knapsack problem. Moreover, our technique is scalable in the sense that even when running large instances of the multiple-choice knapsack problems, we can efficiently utilize the GPU compute resources and memory bandwidth to achieve significant speedups.

  • 362.
    Söderman, Michael
    et al.
    Linköpings Universitet.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Response Compression for Diagnosis in Volume Production2008In: DAC08 Workshop on Diagnostic Services in Network-on-Chips DSNOC,2008, 2008Conference paper (Refereed)
  • 363.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Reliability-Aware Frame Packing for the Static Segment of FlexRay2011In: EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software                         , Association for Computing Machinery (ACM), 2011, 175-184 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay is gaining wide acceptance as the next generation bus protocol for automotive networks. This has led to tremendous research interest in techniques for scheduling signals, which are generated by real-time applications, on the FlexRay bus. Signals are first packed together into frames at the application-level and the frames are then transmitted over the bus. To ensure reliability of frames in the presence of faults, frames must be retransmitted over the bus but this comes at the cost of higher bandwidth utilization. To address this issue, in this paper, we propose a novel frame packing method for FlexRay bus. Our method computes the required number of retransmissions of frames that ensures the specified reliability goal. The proposed frame packing method also ensures that none of the signals violates its deadline and that the desired reliability goal for guaranteeing fault-tolerance is met at the minimum bandwidth cost. Extensive experiments on synthetic as well as a industrial case study demonstrate the benefits of our method.

  • 364.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling for Fault-Tolerant Communication on the Static Segment of FlexRay2010In: 31st IEEE Real-Time Systems Symposium (RTSS10), San Diego, CA, USA, November 30-December 3, 2010., IEEE Computer Society , 2010, 385-394 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay has been widely accepted as the next generation bus protocol for automotive networks. This has led to tremendous research interest in techniques for scheduling messages on the FlexRay bus, in order to meet the hard realtime deadlines of the automotive applications. However, these techniques do not generate reliable schedules in the sense that they do not provide any performance guarantees in the presence of faults. In this work, we will present a framework for generating fault-tolerant message schedules on the time-triggered (static) segment of the FlexRay bus. We provide formal guarantees that the generated fault-tolerant schedules achieve the reliability goal even in the presence of transient and intermittent faults. Moreover, our technique minimizes the required number of retransmissions of the messages in order to achieve such fault tolerant schedules, thereby, optimizing the bandwidth utilization. Towards this, we formulate the optimization problem in Constraint Logic Programming (CLP), which returns optimal results. However, this procedure is computationally intensive and hence, we also propose an efficient heuristic. The heuristic guarantees the reliability of the constructed schedules but might be sub-optimal with respect to bandwidth utilization. Extensive experiments run on synthetic test cases and real-life case studies illustrate that the heuristic performs extremely well. The experiments also establish that our heuristic scales significantly better than the CLP formulation.

  • 365.
    Tseng, Kuei-Hsi
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    TAM Design for Parallel Testing under Bus Bandwidth Limit2010Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
    Abstract [en]

    The complexity of electronic system is increasing rapidly and many of the electronic systems   are   embedded   systems   implemented   as   system-on-chip   (SoC).   This increasing  complexity  of  SoC  leads  to  longer  test  application  time  (TAT).  One approach  to  reduce  the  TAT  is  to  perform  tests  to  several  cores  in  parallel,  which requests transporting test data in parallel instead of sequentially.

    In IEEE Std. 1500, it supports parallel test mode by incorporating a user-defined, parallel   test   access   mechanism   (TAM)   to   speed   up   the   testing   process.   The user-defined  TAM  means  the  detail  of  TAM  design  is  excluded  from  standard  and decided by system integrator. Therefore, we propose a customized TAM structure and two approaches to guarantee full-spatial-parallelism under a bus width limit, and aim to  minimize  the  total  number  of  wire  connections.  In  order  to  know  how  close  to optimal  solution  our  solutions  are,  we  implement  a  Simulated  Annealing  (SA) algorithm to do the comparison.

    The  experimental  results  of  the  two  proposed  approaches  based  on  benchmark ISCAS’89  and  ITC’02  show  the  parallelism  can  be  guaranteed  by  our  approaches while using only a few wire connections per pin, and the execution times of them are shorter compared with the SA algorithm.

  • 366.
    Tudu, Jaynarayan T.
    et al.
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Test Scheduling of Modular System-on-Chip under Capture Power Constraint2010In: Workshop on RTL ATPG & DFT (WRTLT10), Shanghai, China, December 2010., 2010Conference paper (Refereed)
  • 367.
    Tudu, Jaynarayan T.
    et al.
    Indian Institute of Science.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science.
    Agrawal, Vishwani
    Auburn University.
    On Minimization of Peak Power for Scan Circuit during Test2009In: Proceedings of the 14th IEEE European Test Symposium, ETS 2009, 2009, 25-30 p.Conference paper (Refereed)
    Abstract [en]

    Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.

  • 368.
    Tudu, Jaynarayan T.
    et al.
    Indian Institute of Science.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science.
    Fujiwara, Hideo
    Nara Institute of Science and Technology.
    Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power2010In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, New York, USA: ACM , 2010, 73-78 p.Conference paper (Refereed)
    Abstract [en]

    Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.

  • 369.
    Tudu, Jaynarayan T.
    et al.
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Fujiwara, Hideo
    Nara Institute of Science and Technology, Japan.
    Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC2009In: 10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), Hongkong, China, November 27-28, 2009., 2009, 43-48 p.Conference paper (Refereed)
  • 370.
    Tudu, Jaynarayan T.
    et al.
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Fujiwara, Hideo
    Nara Institute of Science and Technology, Japan.
    Scan Cells Reordering to Minimize Peak Power During Test Cycle: A Graph Theoretic Approach2010In: IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010., IEEE , 2010, 259-259 p.Conference paper (Refereed)
    Abstract [en]

    Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

  • 371.
    Tudu, Jaynarayan T.
    et al.
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Singh, Adit
    Capture Power Reduction for Modular System-on-Chip Test2009In: IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 8-10, 2009., 2009Conference paper (Refereed)
  • 372.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Jenihhin, Maksim
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture2004In: The 5th IEEE Latin-American Test Workshop,2004, 2004, 98-103 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents an approach to the test time minimization problem for parallel hybrid BIST with test pattern broadcasting in core-based systems. The hybrid test set is assembled from pseudorandom test patterns that are generated online and deterministic test patterns that are generated off-line and stored in the system. The pseudorandom patterns are broadcasted and applied to all cores in parallel. The deterministic patterns are, on the other hand, generated for particular cores, one at a time, but applied (broadcasted) in parallel to all other cores and used for the rest of the system as pseudorandom patterns. We propose an iterative algorithm to find the optimal combination between those two test sets under given memory constraints, so that the systems testing time is minimized. Our approach employs a fast cost estimation method in order to avoid exhaustive search and to speed-up the optimization process. Experimental results have shown the efficiency of the algorithm to find a near-optimal solution with very few iterations.

  • 373.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Jenihhin, Maksim
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting2004In: The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004,2004, 2004Conference paper (Refereed)
    Abstract [en]

    This paper introduces a technique for hybrid BIST time optimization for testing core-based systems that use test pattern broadcasting for both pseudorandom and deterministic patterns. First we formulate the test time minimization problem for such an architecture. Thereafter we present algorithms for finding an efficient combination of pseudorandom and deterministic test sets under given memory constraints, so that the system testing time can be shortened. We also analyze the significance of the pseudorandom sequence quality for the final results. The results are illustrated and the efficiency of the approach is demonstrated by experimental results.

  • 374.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Jenihhin, Maksim
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting2003In: The 21st NORCHIP Conference,2003, 2003, 112-116 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes a hybrid BIST architecture for testing core-based systems together with a method for test time minimization. The approach uses test pattern broadcasting for both pseudorandom and deterministic patterns. To overcome the high complexity of the test time minimization problem we propose a fast algorithm to find an efficient combination of pseudorandom and deterministic test sets under given memory constraints. The efficiency of the approach is demonstrated by experimental results.

  • 375.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Orasson, Elmet
    Dept. Computer Engineering Tallinn University of Technology.
    Raidma, Rein
    Dept. Computer Engineering Tallinn University of Technology.
    Fast Test Cost Calculation for Hybrid BIST in Digital Systems2001In: Euromicro Symposium on Digital Systems Design,2001, Warsaw, Poland: IEEE Computer Society Press , 2001, 318- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored precomputed deterministic test patterns. A procedure is proposed for fast calculation of the cost of hybrid BIST at different lengths of pseudorandom test to find an optimal balance between test sets, and to perform core test with minimum cost of both, time and memory, and without losing in test quality. Compared to the previous approach, based on iterative use of deterministic ATPG for evaluating the cost of stored patterns, in this paper a new, extremely fast procedure is proposed, which calculates costs on a basis of fault table manipulations. Experiments on the ISCAS benchmark circuits show that the new procedure is about two orders of magnitude faster than the previous one.

  • 376.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Kruus, Helena
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Using Tabu Search Method for Optimizing the Cost of Hybrid BIST2001In: 16th Conference on Design of Circuits and Integrated Systems DCIS 2001,2001, 2001, 445-450 p.Conference paper (Refereed)
    Abstract [en]

    This paper deals with a hybrid BIST solution for testing systems-on-chip, which combines pseudo-random test patterns with stored precomputed deterministic test patterns. A method is proposed for finding the optimal balance between pseudorandom and stored test patterns to perform core test with minimum cost of time and memory, and without losing test quality. As a generalization of local optimization, Tabu search method is used for finding the optimal balance. Unlike local search which stops when no improved new solution is found in the current neighborhood, tabu search continues the search from the best solution in the neighborhood even if it is worse than the current solution. To speed up the optimization procedure, a fast method for predicting the location of optimum solution is also used. Experimental results on benchmark circuits have proved the efficiency of the proposed approach for BIST optimization.

  • 377.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bao, Min
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Steady-State Dynamic Temperature Analysis and Reliability Optimization for Embedded Multiprocessor Systems2012In: 49th ACM/EDAC/IEEE Design Automation Conference (DAC), 3-7 June 2012, San Francisco, ACM/ IEEE , 2012, 197-204 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we propose an analytical technique for the steady-state dynamic temperature analysis (SSDTA) of multiprocessor systems with periodic applications. The approach is accurate and, moreover, fast, such that it can be included inside an optimization loop for embedded system design. Using the proposed solution, a temperature-aware reliability optimization, based on the thermal cycling failure mechanism, is presented. The experimental results con firm the quality and speed of our SSDTA technique, compared to the state of the art. They also show that the lifetime of an embedded system can significantly be improved, without sacrificing its energy efficiency, by taking into consideration, during the design stage, the steady-state dynamic temperature profile of the system.

  • 378.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Probabilistic Analysis of Power and Temperature Under Process Variation for Electronic System Design2014In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 33, no 6, 931-944 p.Article in journal (Refereed)
    Abstract [en]

    Electronic system design based on deterministic techniques for power-temperature analysis is, in the context of current and future technologies, both unreliable and inefficient since the presence of uncertainty, in particular, due to process variation, is disregarded. In this paper, we propose a flexible probabilistic framework targeted at the quantification of the transient power and temperature variations of an electronic system. The framework is capable of modeling diverse probability laws of the underlying uncertain parameters and arbitrary dependencies of the system on such parameters. For the considered system, under a given workload, our technique delivers analytical representations of the corresponding stochastic power and temperature profiles. These representations allow for a computationally efficient estimation of the probability distributions and accompanying quantities of the power and temperature characteristics of the system. The approximation accuracy and computational time of our approach are assessed by a range of comparisons with Monte Carlo simulations, which confirm the efficiency of the proposed technique.

  • 379.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Villani, Mattias
    Linköping University, Department of Computer and Information Science, Statistics. Linköping University, Faculty of Arts and Sciences.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Statistical Analysis of Process Variation Based on Indirect Measurements for Electronic System Design2014In: 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), New York: IEEE conference proceedings, 2014, 436-442 p.Conference paper (Refereed)
    Abstract [en]

    We present a framework for the analysis of process variation across semiconductor wafers. The framework is capable of quantifying the primary parameters affected by process variation, e.g., the effective channel length, which is in contrast with the former techniques wherein only secondary parameters were considered, e.g., the leakage current. Instead of taking direct measurements of the quantity of interest, we employ Bayesian inference to draw conclusions based on indirect observations, e.g., on temperature. The proposed approach has low costs since no deployment of expensive test structures might be needed or only a small subset of the test equipments already deployed for other purposes might need to be activated. The experimental results present an assessment of our framework for a wide range of configurations.

  • 380.
    Varea, Mauricio
    et al.
    Dept. Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Cortes, Luis-Alejandro
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Symbolic Model Checking of Dual Transition Petri Nets2002In: 10th International Symposium on HardwareSoftware Codesign CODES 2002,2002, Estes Park, Colorado, USA: IEEE Computer Society Press , 2002, 43- p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the formal verification of the recently introduced Dual Transition Petri Net (DTPN) models, using model checking techniques. The methodology presented addresses the symbolic model checking of embedded systems behavioural properties, expressed in either computation tree logics (CTL) or linear temporal logics (LTL). The embedded system specification is given in terms of DTPN models, where elements of the model are captured in a four-module library which implements the behaviour of the model. Key issues in the development of the methodology are the heterogeneity and the nondeterministic nature of the model. This is handled by introducing some modifications in both structure and behaviour of the model, thus reducing the points of nondeterminism. Several features of the methodology are discussed and two examples are given in order to show the validity of the model.

  • 381.
    Varea, Mauricio
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al-Hashimi, Bashir
    Dept. of Electronics and Computer Science University of Southampton.
    Cortes, Luis-Alejandro
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Dual Flow Nets: Modelling the Control/Data-Flow Relation in Embedded Systems2006In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 5, no 1, 54-81 p.Article in journal (Refereed)
    Abstract [en]

    This paper addresses the interrelation between control and data flow in embedded system models through a new design representation, called Dual Flow Net (DFN). A modeling formalism with a very close-fitting control and data flow is achieved by this representation, as a consequence of enhancing its underlying Petri net structure. The work presented in this paper does not only tackle the modeling side in embedded systems design, but also the validation of embedded system models through formal methods. Various introductory examples illustrate the applicability of the DFN principles, whereas the capability of the model to with complex designs is demonstrated through the design and verification of a real-life Ethernet coprocessor.

  • 382.
    Vayrynen, M.
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Singh, V.
    Supercomputer Education and Research Centre, Indian Institute of Science, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips2009In: Proceedings -Design, Automation and Test in Europe, DATE, 2009, 484-489 p.Conference paper (Refereed)
    Abstract [en]

    Fault-tolerance is due to the semiconductor technology development important, not only for safety-critical systems but also for general-purpose (non-safety critical) systems. However, instead of guaranteeing that deadlines always are met, it is for general-purpose systems important to minimize the average execution time (AET) while ensuring fault-tolerance. For a given job and a soft (transient) error probability, we define mathematical formulas for AET that includes bus communication overhead for both voting (active replication) and rollback-recovery with checkpointing (RRC). And, for a given multi-processor system-on-chip (MPSoC), we define integer linear programming (ILP) models that minimize AET including bus communication overhead when: (1) selecting the number of checkpoints when using RRC, (2) finding the number of processors and job-to-processor assignment when using voting, and (3) defining fault-tolerance scheme (voting or RRC) per job and defining its usage for each job. Experiments demonstrate significant savings in AET.

  • 383. Vinay, N.S.
    et al.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules2009In: DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 20-24, 2009., 2009Conference paper (Refereed)
  • 384. Vinay, N.S.
    et al.
    Rawat, Indira
    Gaur, M.S.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules2010In: IEEE East-West Design & Test Symposium (EWDTS10), St. Petersburg, Russia, September 17-20, 2010., IEEE , 2010, 343-349 p.Conference paper (Refereed)
  • 385.
    Väyrynen, Mikael
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Fault-Tolerant Average Execution Time Optimization for System-On-Chips2009In: Frontiers of High Performance Embedded Computing, Bangalore, India, January, 2009., 2009Conference paper (Refereed)
  • 386.
    Wu, Dong
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems2003In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 150, no 5, 302-312 p.Article in journal (Refereed)
    Abstract [en]

    A dynamic voltage scaling (DVS) technique for embedded systems expressed as conditional task graphs (CTGs) is described. The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also the effect of combining a genetic algorithm based mapping with the DVS technique is examined and it is shown that further energy reduction can be achieved. The techniques are tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with an energy saving of up to 24%. Furthermore, it is shown that savings of up to 51% are achieved by considering during the mapping optimisation. Finally, the impact of communications and communication link selection on the scheduling and mapping technique is investigated and results are reported.

  • 387.
    Wu, Dong
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems2003In: Design Automation and Test in Europe DATE 2003 Conference,2003, Munich, Germany: IEEE Computer Society Press , 2003, 90- p.Conference paper (Refereed)
    Abstract [en]

    This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.

  • 388.
    Wu, Dong
    et al.
    School of Electronics and Computer Science University of Southampton.
    Al-Hashimi, Bashir M.
    School of Electronics and Computer Science University of Southampton.
    Schmitz, Marcus T.
    School of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction2005In: 8th Euromicro Conference on Digital System Design DSD2005,2005, Porto, Portugal: IEEE Computer Society Press , 2005, 34- p.Conference paper (Refereed)
    Abstract [en]

    Recent research has shown that the combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) yields high energy reductions in embedded systems. Nevertheless, the implementation of DVS and ABB requires a significant system cost, making it less attractive for many small systems. In this paper we demonstrate that it is possible to reduce this system cost and to achieve comparable energy saving to that obtained using combined DVS and ABB scheme through a co-synthesis methodology which is aware of the tasks' power-composition profile (the ratio of the dynamic power to the leakage power). In particular, the presented methodology performs a power management selection at the architectural level, i.e., it decides upon which processing elements to be equipped with which power management scheme (DVS, ABB, or combined DVS and ABB) - with the aim to achieve high energy savings at a reduced implementation cost. The proposed technique maps, schedules, and voltage scales applications specified as task graphs with timing constraints. Detailed experiments including a real-life benchmark are conducted to demonstrate the effectiveness of the proposed methodology.

  • 389.
    Yang, Tianruo
    et al.
    IDA Linköpings Universitet.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Improved Register-Transfer Level Functional Partioning Approach for Testability2000In: Journal of systems architecture, ISSN 1383-7621, Vol. 46, no 3, 209-223 p.Article in journal (Refereed)
  • 390.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Asani, Golnaz
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints2011In: Proceedings of the Asian Test Symposium, IEEE , 2011, 525-531 p.Conference paper (Refereed)
    Abstract [en]

    In contrast to IEEE 1149.1, IEEE P1687 allows, through segment insertion bits, flexible scan paths for accessing on-chip instruments, such as test, debug, monitoring, measurement and configuration features. Flexible access to embedded instruments allows test time reduction, which is important at production test. However, the test access scheme should be carefully selected such that resource constraints are not violated and power constraints are met. For IEEE P1687, we detail in this paper session-based and session-less test scheduling, and propose resource and power-aware test scheduling algorithms for the detailed scheduling types. Results using the implementation of our algorithms shows on ITC’02-based benchmarks significant test time reductions when compared to non-optimized test schedules.

  • 391.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Automated Design for IEEE P16872011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011., 2011Conference paper (Other academic)
  • 392.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Design Automation for IEEE P16872011In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2011, 1-6 p.Conference paper (Refereed)
    Abstract [en]

    The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total access time and average access time.

  • 393.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Larsson, Erik
    Lund University, Sweden.
    Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P16872012In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 29, no 2, 79-88 p.Article in journal (Refereed)
    Abstract [en]

    This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE P1687 standard in an era where reuse of existing functional elements and integration of IP blocks is accelerating rapidly. It briefly discusses the deficiencies of existing 1149.1 (JTAG) and 1500 standards and demonstrates how the new standard, P1687, plugs these exposures by specifying JTAG as an off-chip to on-chip interface to the instrument access infrastructure. It provides a simple example to underscore the need for the standard and then builds on this example to show how the standard can be used for more complex situations.

  • 394.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Time Analysis for IEEE P16872010In: Proceedings of the Asian Test Symposium, 2010, 455-460 p.Conference paper (Refereed)
    Abstract [en]

    The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.

  • 395.
    Zadegan, Farrokh Ghani
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    A Study of Instrument Reuse and Retargeting in P16872011In: IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011., 2011Conference paper (Refereed)
    Abstract [en]

    Modern chips may contain a large number of embedded test, debug, configuration, and monitoring features, called instruments. An instrument and its instrument data, instrument access procedures, may be pre-developed and reused and instruments may be accessed in different ways through the life-time of the chip, which requires retargeting. To address instruments reuse and retargeting, IEEE P1678 specifies a hardware architecture, a hardware description language, and an access procedure description language. In this paper, we investigate how P1687 facilitates instrument access procedure reuse and retargeting.

  • 396.
    Zhang, Xia
    et al.
    University of Electronic Science and Technology of China, Chengdu.
    Zhan, Jinyu
    University of Electronic Science and Technology of China, Chengdu.
    Jiang, Wei
    University of Electronic Science and Technology of China, Chengdu.
    Ma, Yue
    University of Electronic Science and Technology of China, Chengdu.
    Jiang, Ke
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Design Optimization of Energy- and Security-Critical Distributed Real-Time Embedded Systems2013In: 15th Workshop on Advances in Parallel and Distributed Computational Models (APDCM 2013), Boston, USA, May 20, 2013., IEEE Press, 2013, 741-750 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we approach the design of energy- and security-critical distributed real-time embedded systems from the early mapping and scheduling phases. Modern Distributed Embedded Systems (DESs) are common to be connected to external networks, which is beneficial for various purposes, but also opens up the gate for potential security attacks. However, security protections in DESs result in significant time and energy overhead. In this work, we focus on the problem of providing the best confidentiality protection of internal communication in DESs under time and energy constraints. The complexity of finding the optimal solution grows exponentially as problem size grows. Therefore, we propose an efficient genetic algorithm based heuristic for solving the problem. Extensive experiments demonstrate the efficiency of the proposed technique.

  • 397.
    Zhang, Ying
    et al.
    School of Software Engineering, Tongji University, China.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Jiang, Jianhui
    School of Software Engineering, Tongji University, China.
    Li, Huawei
    State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China.
    Fujita, Masahiro
    VLSI Design and Education Center, University of Tokyo, Japan .
    Temperature-Aware Software-Based Self-Testing for Delay Faults2015In: Proc. Design, Automation and Test in Europe Conference (DATE’15), Grenoble, France, Mar. 9-13, 2015., 2015Conference paper (Refereed)
    Abstract [en]

    Delay defects under high temperature have been one of the most critical factors to affect the reliability of computer systems, and the current test methods don’t address this problem properly. In this paper, a temperature-aware software-based selftesting (SBST) technique is proposed to self-heat the processors within a high temperature range and effectively test delay faults under high temperature. First, it automatically generates highquality test programs through automatic test instruction generation (ATIG), and avoids over-testing caused by nonfunctional patterns. Second, it exploits two effective powerintensive program transformations to self-heat up the processors internally. Third, it applies a greedy algorithm to search the optimized schedule of the test templates in order to generate the test program while making sure that the temperature of the processor under test is within the specified range. Experimental results show that the generated program is successful to guarantee delay test within the given temperature range, and achieves high test performance with functional patterns.

  • 398.
    Zhirkov, Igor
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Thin Film Physics. Linköping University, Faculty of Science & Engineering.
    Petruhins, Andrejs
    Linköping University, Department of Physics, Chemistry and Biology, Thin Film Physics. Linköping University, Faculty of Science & Engineering.
    Rosén, Jakob
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Effect of cathode composition and nitrogen pressure on macroparticle generation and type of arc discharge in a DC arc source with Ti-Al compound cathodes2015In: Surface & Coatings Technology, ISSN 0257-8972, E-ISSN 1879-3347, Vol. 281, 20-26 p.Article in journal (Refereed)
    Abstract [en]

    Thin films deposited with unfiltered DC arc plasma from Ti, Ti0.75Al0.25, Ti0.50Al0.50, Ti0.30Al0.70, and Al cathodes were characterized with a scanning electron microscope for quantification of extent of macroparticle incorporation. Depositions were performed in N-2 atmosphere in the pressure range from 10(-6) Torr up to 3 . 10(-2) Torr, and the formation of cathode surface nitride contamination was identified from X-ray diffraction analysis. Visual observation and photographic fixation of the arc spot behavior was simultaneously performed. A reduction in macroparticle generation with decreasing Al content and increasing N-2 pressure was demonstrated. A correlated transformation of the arc from type 2 to the type 1 was visually detected and found to be a function of N-2 pressure and at of Al in the cathode. For the Ti cathode, no arc transformation was detected. These observations can be explained by a comparatively high electrical resistivity and high melting point of Al rich surface nitrides, promoting an arc transformation and a reduction in macropartide generation. (C) 2015 Elsevier B.V. All rights reserved.

  • 399.
    Zhiyuan, He
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Rosinger, Paul
    University of Southampton.
    Al-Hashimi, Bashir
    University of Southampton.
    Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving2008In: Journal of electronic testing, ISSN 0923-8174, Vol. 24, no 1-3, 247-257 p.Article in journal (Refereed)
    Abstract [en]

    High temperature has become a major problem for system-on-chip testing. In order to reduce the test application time while keeping the temperatures of the cores under test within safe ranges, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test application time and, at the same time, prevent the temperatures of cores under test going beyond given limits. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling periods between test sequences so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, such that the cooling periods and the bandwidth of the test bus can be utilized for test data transportation, and hence the test application time can be reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use the constraint logic programming (CLP) to build the optimization model and find the optimal solution. As the optimization time of the CLP-based approach increases exponentially with the problem size, we also propose a heuristic which generates longer test schedules but requires substantially shorter optimization time. Experimental results have shown the efficiency of the proposed approach.

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