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  • 301.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Bus Access Optimisation for FlexRay-based Distributed Embedded Systems2007In: Design, Automation, and Test in Europe Conference DATE07,2007, Nice, France: IEEE Computer Society Press , 2007, 51- p.Conference paper (Refereed)
    Abstract [en]

    FlexRay will very likely become the de-facto standard for in-vehicle communications. Its main advantage is the combination of high speed static and dynamic transmission of messages. In our previous work we have shown that not only the static but also the dynamic segment can be used for hard-real time communication in a deterministic manner. In this paper, we propose techniques for optimising the FlexRay bus access mechanism of a distributed system, so that the hard real-time deadlines are met for all the tasks and messages in the system. We have evaluated the proposed techniques using extensive experiments.

  • 302.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Optimization of Hierarchically Scheduled Heterogeneous Embedded Systems2005In: 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA05,2005, Hong Kong: IEEE Computer Society Press , 2005, 67- p.Conference paper (Refereed)
    Abstract [en]

    We present an approach to the analysis and optimization of heterogeneous distributed embedded systems. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. When several scheduling policies share a resource, they are organized in a hierarchy. In this paper, we address design problems that are characteristic to such hierarchically scheduled systems: assignment of scheduling policies to tasks, mapping of tasks to hardware components, and the scheduling of the activities. We present algorithms for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

  • 303.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Andrei, Alexandru
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Timing analysis of the FlexRay communication protocol2008In: Real-time systems, ISSN 0922-6443, Vol. 39, no 1-3, 205-235 p.Article in journal (Refereed)
    Abstract [en]

    FlexRay is a communication protocol heavily promoted on the market by a large group of car manufacturers and automotive electronics suppliers. However, before it can be successfully used for safety-critical applications that require predictability, timing analysis techniques are necessary for providing bounds for the message communication times. In this paper, we propose techniques for determining the timing properties of messages transmitted in both the static and the dynamic segments of a FlexRay communication cycle. The analysis techniques for messages are integrated in the context of a holistic schedulability analysis that computes the worst-case response times of all the tasks and messages in the system. We have evaluated the proposed analysis techniques using extensive experiments. We also present and evaluate three optimisation algorithms that can be used to improve the schedulability of a system that uses FlexRay. © 2007 Springer Science+Business Media, LLC.

  • 304.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Andrei, Alexandru
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Timing Analysis of the FlexRay Communication Protocol2006In: 18th Euromicro Conference on Real-Time Systems ECRTS 06,2006, Dresden, Germany: IEEE Computer Society Press , 2006, 203- p.Conference paper (Refereed)
    Abstract [en]

    FlexRay will very likely become the de-facto standard for in-vehicle communications. However, before it can be successfully used for safety-critical applications that require predictability, timing analysis techniques are necessary for providing bounds for the message communication times. In this paper, we propose techniques for determining the timing properties of messages transmitted in both the static (ST) and the dynamic (DYN) segments of a FlexRay communication cycle. The analysis techniques for messages are integrated in the context of a holistic schedulability analysis that computes the worst-case response times of all the tasks and messages in the system. We have evaluated the proposed analysis techniques using extensive experiments.

  • 305.
    Pouget, Julien
    et al.
    ESLAB, IDA Linköpings Universitet.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    SOC Test Time Minimization Under Multiple Constraints2003In: 12th IEEE Asian Test Symposium ATS03,2003, Xian, China: IEEE Computer Society Press , 2003, 312- p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a SOC (system-on-chip) test scheduling technique that minimizes the test application time while considering test power limitations and test conflicts. The test power consumption is important to consider since exceeding the system's power limit might damage the system. Our technique takes also into account test conflicts that are due to cross-core testing (testing of interconnections), unit testing with multiple test sets, hierarchical SOCs where cores are embedded in cores, and the sharing of test access mechanism (TAM). Our technique handles these conflicts as well as precedence constraints, which is the order in which the tests has to be applied. We have implemented our algorithm and performed experiments, which shows the efficiency of our approach.

  • 306.
    Pouget, Julien
    et al.
    ESLAB, IDA Linköpings Universitet.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Flottes, Marie-Lise
    LIRMM Montpellier 2 University.
    Rouzeyre, Bruno
    LIRMM Montpellier 2 University.
    An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling2003In: IEEE European Test Workshop 2003 ETW03,2003, Maastricht, The Netherlands: IEEE Computer Society Press , 2003, 51- p.Conference paper (Refereed)
    Abstract [en]

    Test application time and core accessibility are two major issues in System-On-Chip (SOC) testing. The test application time must be minimised, and a test access mechanism (TAM) must be developed to transport test data to and from the cores. In this paper we present an approach to design a test interface (wrapper) at core level taking into account the P1500 restrictions, and to design a TAM architecture and its associated test schedule using a fast and efficient heuristic. A useful and new feature of our approach is that it supports also the testing of interconnections while considering power dissipation, test conflicts and precedence constraints. Another feature of our approach is that the TAM is designed with a central bus architecture, which is a generalisation of the TestBus architecture. The advantages and drawbacks of our approach are discussed, and the proposed architecture and heuristic are validated with experiments.

  • 307.
    Poulsen, Kåre
    et al.
    Informatics and Mathematical Modelling Dept. Technical University of Denmark.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Izosimov, Viacheslav
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Constraint Logic Programming Framework for the Synthesis of Fault-Tolerant Schedules for Distributed Embedded Systems2007In: 12th IEEE Conf. on Emerging Technologies and Factory Automation Work-In-Progress Section,2007, Patras, Greece: IEEE Computer Society Press , 2007, 756- p.Conference paper (Refereed)
    Abstract [en]

    We present a constraint logic programming (CLP) approach for synthesis of fault-tolerant hard real-time applications on distributed heterogeneous architectures. We address time-triggered systems, where processes and messages are statically scheduled based on schedule tables. We use process re-execution for recovering from multiple transient faults. We propose three scheduling approaches, which each present a trade-off between schedule simplicity and performance, (i) full transparency, (ii) slack sharing and (iii) conditional, and provide various degrees of transparency. We have developed a CLP framework that produces the fault-tolerant schedules, guaranteeing schedulability in the presence of transient faults. We show how the framework can be used to tackle design optimization problems.The proposed approach has been evaluated using extensive experiments.

  • 308.
    Poulsen, Kåre
    et al.
    Informatics and Mathematical Modelling Dept. Technical University of Denmark.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Izosimov, Viacheslav
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Energy-Aware Synthesis of Fault-Tolerant Schedules for Real-Time Distributed Embedded Systems2007In: 19th Euromicro Conference on Real-Time Systems ECRTS, Work-In-Progress Section,2007, Pisa, Italy: IEEE Computer Society Press , 2007, 21- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a design optimisation tool for distributed embedded real-time systems that 1) decides mapping, fault-tolerance policy and generates a fault-tolerant schedule, 2) is targeted for hard real-time, 3) has hard reliability goal, 4) generates static schedule for processes and messages, 5) provides fault-tolerance for k transient/soft faults, 6) optimises for minimal energy consumption, while considering impact of lowering voltages on the probability of faults, 7) uses constraint logic programming (CLP) based implementation.

  • 309.
    Rafiliu, Sergiu Aurel
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Low Overhead Dynamic QoS Optimization Under Variable Task Execution Times2010In: 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2010), Macau SAR, P.R.C.: IEEE, 2010Conference paper (Refereed)
    Abstract [en]

    Today's embedded systems are typically exposed to varying load, due to e.g. changing num- ber of tasks and variable task execution times. At the same time, many of the most frequent real-life applications are not characterized by hard real-time constraints and their design goal is not to satisfy certain hard deadlines in the worst case. Moreover, from the user's perspective, achieving a high level of processor utilization is also not a primary goal. What the user needs, is to exploit the available resources (in our case processor time) such that a high level of quality of service (QoS) is delivered. In this paper we propose efficient run-time approaches, able to distribute the processor bandwidth such that the global QoS pro- duced by a set of applications is maximized, in the context in which the processor demand from individual tasks is continuously varying. Extensive experiments demonstrate the efficiency of the proposed approaches.

  • 310.
    Rafiliu, Sergiu
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Stability Conditions of On-line Resource Managers for Systems with Execution Time Variations2011In: 23rd Euromicro conference on Real-Time Systems (ECRTS11), Porto, Portugal, July 6-8, 2011., IEEE, 2011Conference paper (Refereed)
    Abstract [en]

    Today's embedded systems are exposed to variations in load demand due to complex software applications, hardware platforms, and impact of the run-time environments. When these variations are large, and efficiency is required, on-line resource managers may be deployed on the system to help it control its resource usage. An often neglected problem is whether these resource managers are stable, meaning that the resource usage is controlled under all possible scenarios. In this paper we develop mathematical models for the real-time embedded system and we derive conditions which, if satisfied, lead to stable systems. For the developed system models, we also determine bounds on the worst case response times of tasks.

  • 311.
    Rafiliu, Sergiu
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Stability of adaptive feedback-based resource managers for systems with execution time variations2013In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, ISSN 0922-6443, Vol. 49, no 3, 367-400 p.Article in journal (Refereed)
    Abstract [en]

    Today’s embedded systems are exposed to variations in load demand due to complex software applications, dynamic hardware platforms, and the impact of the run-time environment. When these variations are large, and efficiency is required, adaptive on-line resource managers may be deployed on the system to control its resource usage. An often neglected problem is whether these resource managers are stable, meaning that the resource usage is controlled under all possible scenarios. In this paper we develop mathematical models for real-time embedded systems and we derive conditions which, if satisfied, lead to stable systems. For the developed system models, we also determine bounds on the worst case response times of tasks. We also give an intuition of what stability means in a real-time context and we show how it can be applied for several resource managers. We also discuss how our results can be extended in various ways.

  • 312. Rajesh, Venkat
    et al.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Gaur, Manoj S.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    An Even-Odd DFD Technique for Scan Chain Diagnosis2009In: Workshop on RTL and High Level Testing (WRTLT), Hongkong, China, November 27-28, 2009., 2009Conference paper (Refereed)
  • 313.
    Rosén, Jakob
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Predictable Real-Time Applications on Multiprocessor Systems-on-Chip2011Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Being predictable with respect to time is, by definition, a fundamental requirement for any real-time system. Modern multiprocessor systems impose a challenge in this context, due to resource sharing conflicts causing memory transfers to become unpredictable. In this thesis, we present a framework for achieving predictability for real-time applications running on multiprocessor system-on-chip platforms. Using a TDMA bus, worst-case execution time analysis and scheduling are done simultaneously. Since the worst-case execution times are directly dependent on the bus schedule, bus access design is of special importance. Therefore, we provide an efficient algorithm for generating bus schedules, resulting in a minimized worst-case global delay.

    We also present a new approach considering the average-case execution time in a predictable context. Optimization techniques for improving the average-case execution time of tasks, for which predictability with respect to time is not required, have been investigated for a long time in many different contexts. However, this has traditionally been done without paying attention to the worst-case execution time. For predictable real-time applications, on the other hand, the focus has been solely on worst-case execution time optimization, ignoring how this affects the execution time in the average case. In this thesis, we show that having a good average-case global delay can be important also for real-time applications, for which predictability is required. Furthermore, for real-time applications running on multiprocessor systems-on-chip, we present a technique for optimizing for the average case and the worst case simultaneously, allowing for a good average case execution time while still keeping the worst case as small as possible. The proposed solutions in this thesis have been validated by extensive experiments. The results demonstrate the efficiency and importance of the presented techniques.

  • 314.
    Rosén, Jakob
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Andrei, Alexandru
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip2007In: 28th IEEE Real-Time Systems Symposium RTSS07,2007, Tucson, Arizona, USA: IEEE Computer Society Press , 2007, 49- p.Conference paper (Refereed)
    Abstract [en]

    In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. This has a huge impact on worst-case execution time (WCET) analysis and, in general, on the predictability of real-time applications implemented on such systems. As opposed to the WCET analysis performed for a single processor system, where the cache miss penalty is considered constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks' WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this paper we present an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures. The emphasis of this paper is on the bus scheduling policy and its optimization, which is of huge importance for the performance of such a predictable multiprocessor application.

  • 315.
    Rosén, Jakob
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Andrei, Alexandru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Predictable Multiprocessor Systems2010In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper (Other academic)
  • 316.
    Rosén, Jakob
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Worst-Case Execution Time Analysis for Multiprocessor System-on-Chip Platforms2011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011, 2011Conference paper (Other academic)
  • 317.
    Rosén, Jakob
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Andrei, Alexandru
    Ericsson, Linköping, Sweden.
    Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip2011In: 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011., 2011Conference paper (Refereed)
    Abstract [en]

    Worst-case execution time analysis is the fundament of real-time system design, and is therefore an area which has been subject to great scientific interest for a long time. However, traditional worst-case execution time analysis techniques assume that the underlying hardware is a monoprocessor system, and this class of hardware platforms is getting less suitable for modern embedded applications, which demand more and more in terms of computational power. For multiprocessor systems, traditional worst-case analysis tools do not produce correct results and can consequently not be used. To solve this problem, we have previously proposed a technique for achieving predictability on multiprocessor systems-on-chip using a shared TDMA bus. One of the main benefits with our approach is that existing, traditional worstcase execution time analysis techniques can, after some small modifications, be applied. In this paper, we describe the nature of these modifications and how to handle different types of multiprocessor architectures.

  • 318.
    Rosén, Jakob
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Neikter, Carl-Fredrik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Burgio, Paolo
    University of Bologna, Italy.
    Benini, Luca
    University of Bologna, Italy.
    Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip2011In: 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'11), Chicago, IL, USA, April 11-14, 2011., 2011Conference paper (Refereed)
    Abstract [en]

    Optimization techniques for improving the average-case execution time of an application, for which predictability with respect to time is not required, have been investigated for a long time in many different contexts. However, this has traditionally been done without paying attention to the worst-case execution time. For predictable real-time applications, on the other hand, the focus has been solely on worst-case execution time optimization, ignoring how this affects the execution time in the average case. In this paper, we show that having a good average-case delay can be important also for real-time applications for which predictability is required. Furthermore, for real-time applications running on multiprocessor systems-on-chip, we present a technique for optimizing the average case and the worst case simultaneously, allowing for a good average-case execution time while still keeping the worst case as small as possible.

  • 319.
    Ruggiero, Martino
    et al.
    University of Bologna.
    Bertozzi, Davide
    University of Ferrara.
    Benini, Luca
    University of Bologna.
    Milano, Michela
    University of Bologna.
    Andrei, Alexandru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms2009In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 28, no 3, 378-391 p.Article in journal (Refereed)
    Abstract [en]

    This paper proposes a novel approach to solve the allocation and scheduling problems for variable voltage/frequency multiprocessor systems-on-chip, which minimizes overall system energy dissipation. The optimality of derived system configurations is guaranteed, while the computation efficiency of the optimizer allows for solving problem instances that were traditionally considered beyond reach for exact solvers (optimality gap). Furthermore, this paper illustrates the development- and run-time software infrastructures that assist the user in developing applications and implementing optimizer solutions. The proposed approach guarantees a high level of power, performance, and constraint satisfaction predictability as from validation on the target platform, thus bridging the abstraction gap.

  • 320.
    Ruggiero, Martino
    et al.
    DEIS University of Bologna, Italy.
    Gioia, Pari
    DEIS University of Bologna, Italy.
    Alessio, Guerri
    DEIS University of Bologna, Italy.
    Benini, Luca
    DEIS University of Bologna, Italy.
    Michela, Milano
    DEIS University of Bologna, Italy.
    Bertozzi, Davide
    ENDIF University of Ferrara, Italy.
    Andrei, Alexandru
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs2006In: Intl. Symposium on System-on-Chip SOC06,2006, 2006Conference paper (Refereed)
    Abstract [en]

    Most problems addressed by the software optimization flow for multi-processor systems-on-chip (MPSoCs) are NP-complete, and have been traditionally tackled by means of heuristics and highlevel approximations. Complete approaches have been effectively deployed only under unrealistic simplifying assumptions. We propose a novel methodology to formulate and solve to optimality the allocation, scheduling and discrete voltage selection problem for variable voltage/frequency MPSoCs, minimizing the system energy dissipation and the overhead for frequency switching. We integrate the optimization and validation steps to increase the accuracy of cost models and the confidence in quality of results. Two demonstrators are used to show the viability of the proposed methodology.

  • 321.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cervin, Anton
    Dept. of Automatic Control, Lund University, Sweden.
    Control-Quality Optimization for Distributed Embedded Systems with Adaptive Fault Tolerance2012In: ECRTS 2012, IEEE, 2012Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a design framework for distributed embedded control systems that ensures reliable execution and high quality of control even if some computation nodes fail. When a node fails, the configuration of the underlying distributed system changes and the system must adapt to this new situation by activating tasks at operational nodes. The task mapping as well as schedules and control laws that are customized for the new configuration influence the control quality and must, therefore, be optimized. The number of possible configurations due to faults is exponential in the number of nodes in the system. This design-space complexity leads to unaffordable design time and large memory requirements to store information related to mappings, schedules, and controllers. We demonstrate that it is sufficient to synthesize solutions for a small number of base and minimal configurations to achieve fault tolerance with an inherent minimum level of control quality. We also propose an algorithm to further improve control quality with a priority-based search of the set of configurations and trade-offs between task migration and replication.

  • 322.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cervin, A.
    Department of Automatic Control, Lund University, Sweden.
    Ion Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Integrated scheduling and synthesis of control applications on distributed embedded systems2009In: Proceedings -Design, Automation and Test in Europe, DATE, 2009, 57-62 p.Conference paper (Refereed)
    Abstract [en]

    Many embedded control systems comprise several control loops that are closed over a network of computation nodes. In such systems, complex timing behavior and communication lead to delay and jitter, which both degrade the performance of each control loop and must be considered during the controller synthesis. Also, the control performance should be taken into account during system scheduling. The contribution of this paper is a control-scheduling co-design method that integrates controller design with both static and priority-based scheduling of the tasks and messages, and in which the overall control performance is optimized.

  • 323.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cervin, Anton
    Dept. of Automatic Control, Lund University, Sweden.
    Design Optimization and Synthesis of FlexRay Parameters for Embedded Control Applications2011In: 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011., IEEE, 2011Conference paper (Refereed)
    Abstract [en]

    FlexRay is a popular communication protocol in modern automotive systems with several computation nodes and communication units. The complex temporal behavior of such systems depends highly on the FlexRay configuration and influences the performance of running control applications. In our previous work, we presented a design framework for integrated scheduling and design of embedded control applications, where control quality is the optimization objective. This paper presents our extension to the design framework to handle FlexRay-based embedded control systems. Our contribution is a method for the decision of FlexRay parameters and optimization of control quality.

  • 324.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cervin, Anton
    Dept. of Automatic Control Lund University, Lund.
    Quality-Driven Synthesis of Embedded Multi-Mode Control Systems2009In: DAC '09 Proceedings of the 46th Annual Design Automation Conference: , IEEE Computer Society, 2009, 864-869 p.Conference paper (Refereed)
    Abstract [en]

    At runtime, an embedded control system can switch between alternative functional modes. In each mode, the system operates by using a schedule and controllers that exploit the available computation and communication resources to optimize the control performance in the running mode. The number of modes is usually exponential in the number of control loops, which means that all controllers and schedules cannot be produced in affordable design-time and stored in memory. This paper addresses synthesis of multi-mode embedded control systems. Our contribution is a method that trades control quality with optimization time, and that efficiently selects the schedules and controllers to be synthesized and stored in memory.

  • 325.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Tabuada, Paulo
    Cervin, Anton
    Dynamic Scheduling and Control-Quality Optimization of Self-Triggered Control Applications2010In: 31st IEEE Real-Time Systems Symposium (RTSS10), San Diego, CA, USA, November 30-December 3, 2010., IEEE , 2010Conference paper (Refereed)
    Abstract [en]

    Time-triggered periodic control implementations are over provisioned for many execution scenarios in which the states of the controlled plants are close to equilibrium. To address this inefficient use of computation resources, researchers have proposed self-triggered control approaches in which the control task computes its execution deadline at runtime based on the state and dynamical properties of the controlled plant. The potential advantages of this control approach cannot, however, be achieved without adequate online resource-management policies. This paper addresses scheduling of multiple self-triggered control tasks that execute on a uniprocessor platform, where the optimization objective is to find tradeoffs between the control performance and CPU usage of all control tasks. Our experimental results show that efficiency in terms of control performance and reduced CPU usage can be achieved with the heuristic proposed in this paper.

  • 326.
    Samii, Soheil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Chakrabarty, Krishnendu
    Dept. of Electrical and Computer Eng. Duke University.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling2006In: International Test Conference,2006, Santa Clara: IEEE Computer Society Press , 2006, 32.1- p.Conference paper (Refereed)
    Abstract [en]

    Concurrent testing of the cores in a modular core-based System-on-Chip reduces the test application time but increases the test power consumption. Power models and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is pessimistic but simple for a scheduling algorithm to handle. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding scheduling algorithm. The model takes into account the switching activity in the scan chains caused by both the test stimuli and the test responses during scan-in, launch-and-capture, and scan-out. Further, we allow a unique power model per wrapper chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be substantially reduced (on average 16.5% reduction) by using the proposed cycle-accurate test power model.

  • 327.
    Samii, Soheil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Rafiliu, Sergiu Aurel
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems2008In: Design, Automation, and Test in Europe DATE 2008,2008, Munich, Germany: IEEE Computer Society Press , 2008, 556- p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a simulation-based methodology for worst-case response time estimation of distributed real-time systems. Schedulability analysis produces pessimistic upper bounds on process response times. Consequently, such an analysis can lead to overdesigned systems resulting in unnecessarily increased costs. Simulations, if well conducted, can lead to tight lower bounds on worst-case response times, which can be an essential input at design time. Moreover, such a simulation methodology is very important in situations when the running application or the underlying platform is such that no formal timing analysis is available. Another important application of the proposed simulation environment is the validation of formal analysis approaches, by estimating their degree of pessimism. We have performed such an estimation of pessimism for two response-time analysis approaches for distributed embedded systems based on two of the most important automotive communication protocols: CAN and FlexRay.

  • 328.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Selkälä, Mikko
    Ericsson, Linköping.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Chakrabarty, Krishnendu
    Duke University, USA.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling2008In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 27, no 5, 973-977 p.Article in journal (Refereed)
    Abstract [en]

    Concurrent testing of the cores in a core-based system- on-chip reduces the test application time but increases the test power consumption. Power models, test architecture design, and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is simple for a scheduling algorithm to handle but is pessimistic. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding test architecture design and scheduling algorithm. The power model takes into account the switching activity in the scan chains caused by both the test stimuli and the expected test responses during scan-in, launch-and-capture, and scan-out. Furthermore, we allow a unique power model per wrapper-chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Through circuit simulations on ISCAS'89 benchmarks, we demonstrate a high correlation between the real test power dissipation and our cycle-accurate test power model. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be reduced substantially by using the proposed cycle-accurate test power model.

  • 329.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Yin, Yanfei
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ion Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Zhang, Yuanping
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Immune Genetic Algorithms for Optimization of Task Priorities and FlexRay Frame Identifiers2009In: Intl. Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Beijing, China, August 24-26, 2009., IEEE COMPUTER SOC , 2009, 486-493 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay is an automotive communication protocol that combines the comprehensive time-triggered paradigm with an adaptive phase that is more suitable for event-based communication. We study optimization of average response times by assigning priorities and frame identifiers to tasks and messages. Our optimization approach is based on immune genetic algorithms, where in addition to the crossover and mutation operators, we use a vaccination operator that results in considerable improvements in optimization time and quality.

  • 330.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities2003In: Design Automation and Test in Europe DATE 2003 Conference,2003, Munich, Germany: IEEE Computer Society Press , 2003, 960- p.Conference paper (Refereed)
    Abstract [en]

    Multi-mode systems are characterised by a set of interacting operational modes to support different functionalities and standards. In this paper, we present a co-design methodology for multi-mode embedded systems that produces energy-efficient implementations. Based on the key observation that operational modes are executed with different probabilities, i.e., the system spends uneven amounts of time in the different modes, we develop a novel codesign technique that exploits this property to significantly reduce energy dissipation. We conduct several experi-ments, including a smart phone real-life example, that demonstrate the effectiveness of our approach. Reductions in power consumption of up to 64% are reported.

  • 331.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems2002In: Design Automation and Test in Europe Conference DATE 2002,2002, Paris, France: IEEE Computer Society Press , 2002, 514- p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we present an efficient two-step iterative synthesis approach for distributed embedded systems containing dynamic voltage scalable processing elements (DVS-PEs), based on genetic algorithms. The approach partitions, schedules, and voltage scales multi-rate specifications given as task graphs with multiple deadlines. A distinguishing feature of the proposed synthesis is the utilisation of a generalised DVS method. In contrast to previous techniques, which simply exploit available slack time, this generalised technique additionally considers the PE power profile during a refined voltage selection to further increase the energy savings. Extensive experiments are conducted to demonstrate the efficiency of the proposed approach. We report up to 43.2% higher energy reductions compared to previous DVS scheduling approaches based on constructive techniques and total energy savings of up to 82.9% for mapping and scheduling optimised DVS systems.

  • 332.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Iterative Schedule Optimisation for Voltage scalable Distributed Embedded Systems2004In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 3, no 1, 182-217 p.Article in journal (Refereed)
    Abstract [en]

    We present an iterative schedule optimisation for multi-rate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs).To achieve a high degree of energy reduction, we formulate a generalised DVS problem, taking into account the power variations among the executing tasks. An efficient heuristic is presented that identifies optimised supply voltages by not only "simply" exploiting slack time, but under the additional consideration of the power profiles. Thereby, this algorithm minimises the energy dissipation of heterogeneous architectures, including power managed processing elements, effectively. Further, we address the simultaneous schedule optimisation towards timing behaviour and DVS utilisation by integrating the proposed DVS heuristic into a genetic list scheduling approach. We investigate and analyse the possible energy reduction at both steps of the co-synthesis (voltage scaling and scheduling), including the power variations effects. Extensive experiments indicate that the presented work produces solutions with high quality.

  • 333.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Synthesizing Energy-Efficient Embedded Systems with LOPOCOS2002In: Design automation for embedded systems, ISSN 0929-5585, Vol. 6, no 4, 401-424 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that includedynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimization steps during design space exploration for DVS enable architectures. The optimization steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimization for scheduling and communication mapping based on genetic algorithm, optimizes simultaneously execution order and communication mapping towards the utilization of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimization steps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm.

  • 334.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    System-Level Design Techniques for Energy-Efficient Embedded Systems2004Book (Other academic)
    Abstract [en]

    By shrinking feature sizes, deep-submicron technology is enabling the design of systems with increased complexity on a single chip, but it is also introducing a productivity design gap. Additionally, system designers have to cope with an ever-increasing application complexity and shrinking time-to-market windows. Design re-use and system-level co-synthesis are two approaches that are being employed to bridge the design gap and to aid system designers. Power consumption has become one of the main barriers in embedded computing systems design and therefore, methodologies and techniques that provide power-aware hardware/software co-design are necessary. System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the development and validation of co-synthesis techniques that allow an effective design of embedded systems with low energy dissipation. The book provides an overview of a system-level co-design flow, illustrating through examples how system performance is influenced at various steps of the flow including allocation, mapping, and scheduling. The book places special emphasis upon system-level co-synthesis techniques for architectures that contain voltage scalable processors, which can dynamically trade off between computational performance and power consumption. Throughout the book, the introduced co-synthesis techniques, which target both single-mode systems and emerging multi-mode applications, are applied to numerous benchmarks and real-life examples including a realistic smart phone. System-Level Design Techniques for Energy-Efficient Embedded Systems will be of interest to advanced undergraduates, graduate students, and designers, whom are interested in energy-efficient embedded systems design.

  • 335. Schmitz, M.T.
    et al.
    Al-Hashimi, B.M.
    Sch. of Electron. and Comp. Science, University of Southampton, Southampton SO17 1BJ, United Kingdom.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities2005In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 24, no 2, 153-169 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a novel co-design methodology for the synthesis of energy-efficient embedded systems. In particular, we concentrate on distributed embedded systems that accommodate several different applications within a single device, i.e., multimode embedded systems. Based on the key observation that operational modes are executed with different probabilities, that is, the system spends uneven amounts of time in the different modes, we develop a new co-design technique that exploits this property to significantly reduce energy dissipation. Energy and cost savings are achieved through a suitable synthesis process that yields better hardware-resource-sharing opportunities. We conduct several experiments, including a realistic smart phone example, that demonstrate the effectiveness of our approach. Reductions in power consumption of up to 64% are reported.

  • 336.
    Schneider, Andre
    et al.
    EAS Fraunhofer Institute for Integrated Circuits.
    Diener, Karl-Heinz
    EAS Fraunhofer Institute for Integrated Circuits.
    Ivask, Eero
    Dept. Computer Engineering Tallinn University of Technology.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Gramatova, Elena
    Inst. of Informatics, Slovak Republic.
    Hollstein, Thomas
    Technical University of Darmstadt.
    Kuzmicz, Wieslaw
    Warsaw University of Technology.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Integrated Design and Test Generation Under Internet Based Environment MOSCITO2002In: EUROMICRO Symposium on Digital System Design DSD2002,2002, Dortmund, Germany: IEEE Computer Society Press , 2002, 187- p.Conference paper (Refereed)
    Abstract [en]

    This paper describes an environment for internetbased collaboration in the field of design and test of digital systems. Automatic Test Pattern Generation (ATPG) and fault simulation tools at behavioral, logical and hierarchical levels available at geographically different places running under the virtual environment using the MOSCITO system are presented. The interfaces between the integrated tools and also commercial design tools were developed. The tools can be used separately, or in multiple applications in different design and test flows. The functionality of the integrated design and test system was verified in several collaborative experiments over internet by partners locating in different geographical sites.

  • 337.
    Schneider, Andre
    et al.
    EAS Fraunhofer Institute for Integrated Circuits.
    Diener, Karl-Heinz
    EAS Fraunhofer Institute for Integrated Circuits.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Raik, Jaan
    Dept. Computer Engineering Tallinn Technical University.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Hollstein, Thomas
    Technical University of Darmstadt.
    Glesner, Manfred
    Technical University of Darmstadt.
    High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory2002In: The 8th biennial Baltic Electronics Conference BEC 2002,2002, 2002, 287-290 p.Conference paper (Refereed)
    Abstract [en]

    The paper describes the results of the COPERNICUS europroject JEP-97-7133 VILAB (Virtual LABoratory) obtained in a Internet-based joint activities of high-level design and hierarchical test generation of digital systems. Different CAD tools at geographically different places running under virtual environment were used for joint research purposes. The interfaces and convertors between the integrated tools were developed during the project. The tools can be used separately over Internet, or in multiple applications in different complex flows. The functionality of the virtual laboratory in a collaborative research on HW/SW codesign, high-level synthesis and test generation was tested and is described in the paper.

  • 338.
    Schneider, Reinhard
    et al.
    Technical University of Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Goswami, Dip
    Technical University of Munich, Germany.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Optimized Schedule Synthesis under Real-Time Constraints for the Dynamic Segment of FlexRay2010In: International Conference of Embedded and Ubiquitous Computing, Hong Kong SAR, China, 2010Conference paper (Refereed)
    Abstract [en]

    The design process for automotive electronics isan iterative process, where new components and distributedapplications are added over several design cycles incrementally.Hence, at each design iteration an existing communicationschedule is extended by new messages that have to be scheduledappropriately. In this paper, the goal has been to synthesizeschedules under real-time constraints for the dynamic segmentof FlexRay with respect to the 64-cycle protocol specification. Wepropose a flexible scheduling framework to generate all feasibleschedules for a set of messages satisfying real-time and protocolconstraints. Further, we present an optimization procedure toretain schedules according to suitable design metrics. Eventhough the size of the possible design space is exponential inthe number of messages, our proposed method keeps down theschedule synthesis time to practically acceptable values as shownin the experiments.

  • 339.
    Schneider, Reinhard
    et al.
    Technical University of Munich, Germany.
    Goswami, Dip
    Technical University of Munich, Germany.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    On the Quantification of Sustainability and Extensibility of FlexRay Schedules2011In: Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, New York, USA: ACM , 2011, 375-380 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay has emerged as the de-facto next generation in-vehicle communication protocol. Messages are scheduled incrementally on FlexRay according to the automotive design paradigm where new applications are added iteratively. On this account, the schedules must be (i) sustainable, i.e., when messages are added in later iterations, they must preserve deadline guarantees of existing messages and (ii) extensible, i.e., they must accommodate future messages without changes to existing schedules. Unfortunately, traditionally used metrics of sustainability and extensibility for timing and schedulability analysis are generic and can not be trivially adapted to FlexRay schedules. This is because of platform-specific properties of FlexRay like being a hybrid paradigm, where both time-triggered and event-triggered segments are used for communication. In this paper, we first introduce new notions of sustainability and extensibility for FlexRay that capture protocol-specific properties and then present novel metrics to quantify sustainable and extensible schedules. We demonstrate the applicability of our results with industrial-size case studies and show that our proposed metrics may be visually represented allowing easy interpretation by system designers in the automotive industry.

  • 340.
    Sciuto, D.
    et al.
    Politecnico di Milano, Italy.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Proceedings -Design, Automation and Test in Europe, DATE: Foreword2008In: Design, Automation and Test in Europe, ISSN 1530-1591Other (Other academic)
    Abstract [en]

    [No abstract available]

  • 341.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Power Constrained Test Scheduling for 3D Stacked Chips: (poster)2010In: 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA., 2010Conference paper (Refereed)
  • 342.
    Sengupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling Tests for 3D Stacked Chips under Power Constraints2012In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 28, no 1, 121-135 p.Article in journal (Refereed)
    Abstract [en]

    This paper addresses Test Application Time (TAT) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the TAT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in TAT.

  • 343.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling Tests for 3D Stacked Chips under Power Constraints2011In: Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011, Queenstown, NZ, Washington, DC, USA: IEEE Computer Society , 2011, 72-77 p.Conference paper (Refereed)
    Abstract [en]

    This paper addresses Test Application Time (TAT)reduction for core-based 3D Stacked ICs (SICs). Applyingtraditional test scheduling methods used for non-stacked chiptesting where the same test schedule is applied both at wafer testand at final test to SICs, leads to unnecessarily high TAT. This isbecause the final test of 3D-SICs includes the testing of all thestacked chips. A key challenge in 3D-SIC testing is to reduce TATby co-optimizing the wafer test and the final test while meetingpower constraints. We consider a system of chips with coresequipped with dedicated Built-In-Self-Test (BIST)-engines andpropose a test scheduling approach to reduce TAT while meetingthe power constraints. Depending on the test schedule, the controllines that are required for BIST can be shared among severalBIST engines. This is taken into account in the test schedulingapproach and experiments show significant savings in TAT.

  • 344.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling Tests for Stacked 3D Chips under Power Constraints2010In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper (Other academic)
  • 345.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias2011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011, 2011Conference paper (Other academic)
    Abstract [en]

    In this paper we have proposed a test cost model for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike in the case of non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the most cost-efficient test flow for 3D TSV-SICs is yet undefined. Therefore, analysing the various alternatives of test flow, we present a cost model with the optimal test flow. In the test flow alternatives, we analyse the effect of all possible moments of testing for a 3D TSV-SIC, viz., wafer sort, intermediate test and package test. For the optimal test flow, we have performed experiments with various varying yield and test time parameters, which further support our claim.

  • 346.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Planning for 3D Stacked ICs with Through-Silicon Vias2011In: 3D-TEST, 2011Conference paper (Refereed)
    Abstract [en]

    Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs and 3D TSV-SICs with two chips in the stack. We have implemented our techniques and experiments show significant reduction of test cost.

  • 347.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Planning for Core-based 3D Stacked ICs under Power Constraints2012In: RASDAT 2012, 2012Conference paper (Refereed)
    Abstract [en]

    Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D SICs with two chips and 3D SICs with an arbitrary number of chips. We motivate the problem by demostrating the trade-off between test time and hardware, within a power constraint, while arriving at the minimal cost.

  • 348.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias2012In: VLSI 2012, IEEE , 2012Conference paper (Refereed)
    Abstract [en]

    Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSVSICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

  • 349.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias (poster)2011In: European Test Symposium (ETS11), Trondheim, Norway, May 23-27, 2011., 2011Conference paper (Refereed)
  • 350.
    SenGupta, Breeta
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Scheduling for 3D Stacked ICs under Power Constraints2011In: 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011, 2011Conference paper (Refereed)
    Abstract [en]

    This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.

45678 301 - 350 of 399
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