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  • 251.
    Schneider, Andre
    et al.
    EAS Fraunhofer Institute for Integrated Circuits.
    Diener, Karl-Heinz
    EAS Fraunhofer Institute for Integrated Circuits.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Raik, Jaan
    Dept. Computer Engineering Tallinn Technical University.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Hollstein, Thomas
    Technical University of Darmstadt.
    Glesner, Manfred
    Technical University of Darmstadt.
    High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory2002In: The 8th biennial Baltic Electronics Conference BEC 2002,2002, 2002, 287-290 p.Conference paper (Refereed)
    Abstract [en]

    The paper describes the results of the COPERNICUS europroject JEP-97-7133 VILAB (Virtual LABoratory) obtained in a Internet-based joint activities of high-level design and hierarchical test generation of digital systems. Different CAD tools at geographically different places running under virtual environment were used for joint research purposes. The interfaces and convertors between the integrated tools were developed during the project. The tools can be used separately over Internet, or in multiple applications in different complex flows. The functionality of the virtual laboratory in a collaborative research on HW/SW codesign, high-level synthesis and test generation was tested and is described in the paper.

  • 252.
    Schneider, Reinhard
    et al.
    Technical University of Munich, Germany.
    Goswami, Dip
    Technical University of Munich, Germany.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    On the Quantification of Sustainability and Extensibility of FlexRay Schedules2011In: Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, New York, USA: ACM , 2011, 375-380 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay has emerged as the de-facto next generation in-vehicle communication protocol. Messages are scheduled incrementally on FlexRay according to the automotive design paradigm where new applications are added iteratively. On this account, the schedules must be (i) sustainable, i.e., when messages are added in later iterations, they must preserve deadline guarantees of existing messages and (ii) extensible, i.e., they must accommodate future messages without changes to existing schedules. Unfortunately, traditionally used metrics of sustainability and extensibility for timing and schedulability analysis are generic and can not be trivially adapted to FlexRay schedules. This is because of platform-specific properties of FlexRay like being a hybrid paradigm, where both time-triggered and event-triggered segments are used for communication. In this paper, we first introduce new notions of sustainability and extensibility for FlexRay that capture protocol-specific properties and then present novel metrics to quantify sustainable and extensible schedules. We demonstrate the applicability of our results with industrial-size case studies and show that our proposed metrics may be visually represented allowing easy interpretation by system designers in the automotive industry.

  • 253.
    Schneider, Reinhard
    et al.
    Technical University of Munich, Germany .
    Goswami, Dip
    Eindhoven University of Technology, Netherlands .
    Chakraborty, Samarjit
    Technical University of Munich, Germany .
    Bordoloi, Unmesh
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Quantifying Notions of Extensibility in FlexRay Schedule Synthesis2014In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, Vol. 19, no 4, 32- p.Article in journal (Refereed)
    Abstract [en]

    FlexRay has now become a well-established in-vehicle communication bus at most original equipment manufacturers (OEMs) such as BMW, Audi, and GM. Given the increasing cost of verification and the high degree of crosslinking between components in automotive architectures, an incremental design process is commonly followed. In order to incorporate FlexRay-based designs in such a process, the resulting schedules must be extensible, that is: (i) when messages are added in later iterations, they must preserve deadline guarantees of already scheduled messages, and (ii) they must accommodate as many new messages as possible without changes to existing schedules. Apart from extensible scheduling having not received much attention so far, traditional metrics used for quantifying them cannot be trivially adapted to FlexRay schedules. This is because they do not exploit specific properties of the FlexRay protocol. In this article we, for the first time, introduce new notions of extensibility for FlexRay that capture all the protocol-specific properties. In particular, we focus on the dynamic segment of FlexRay and we present a number of metrics to quantify extensible schedules. Based on the introduced metrics, we propose strategies to synthesize extensible schedules and compare the results of different scheduling algorithms. We demonstrate the applicability of the results with industrial-size case studies and also show that the proposed metrics may also be visually represented, thereby allowing for easy interpretation.

  • 254.
    Sciuto, D.
    et al.
    Politecnico di Milano, Italy.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Proceedings -Design, Automation and Test in Europe, DATE: Foreword2008In: Design, Automation and Test in Europe, ISSN 1530-1591Other (Other academic)
    Abstract [en]

    [No abstract available]

  • 255.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Correlation-Aware Probabilistic Timing Analysis for the Dynamic Segment of FlexRay2016In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 15, no 3, 54:1-54:31 p.Article in journal (Refereed)
    Abstract [en]

    We propose an analytical framework for probabilistic timing analysis of the event-triggered Dynamic segment of the FlexRay communication protocol. Specifically, our framework computes the Deadline Miss Ratio of each message. The core problem is formulated as a Mixed Integer Linear Program (MILP). Given the intractability of the problem, we also propose several techniques that help to mitigate the running times of our tool. This includes the re-engineering of the problem to run it on GPUs as well as reformulating the MILP itself.

    Most importantly, we also show how our framework can handle correlations between the queuing events of messages. This is challenging because one cannot apply the convolution operator in the same way as in the case of independent queuing events.

  • 256.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bordoloi, Unmesh D
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Probabilistic Response Time and Joint Analysis of Periodic Tasks2015In: PROCEEDINGS OF THE 2015 27TH EUROMICRO CONFERENCE ON REAL-TIME SYSTEMS (ECRTS 2015), IEEE Communications Society, 2015, 235-246 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we address the problem of computing the probability response time distribution of periodic tasks scheduled on a uniprocessor systems. Our framework assumes an arbitrary non-idling preemptive scheduling policy that may be either a fixed-priority scheduler (such as Rate Monotonic - RM) or a dynamic-priority scheduler (such as Earliest Deadline First - EDF). At the same time, our framework can handle arbitrary execution time distributions arbitrary deadlines providing numerically accurate results. We also show how the framework can be extended to compute the correlation coefficients between the response times of different jobs by performing the joint analysis.

  • 257.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Reliability-Aware Frame Packing for the Static Segment of FlexRay2011In: EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software                         , Association for Computing Machinery (ACM), 2011, 175-184 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay is gaining wide acceptance as the next generation bus protocol for automotive networks. This has led to tremendous research interest in techniques for scheduling signals, which are generated by real-time applications, on the FlexRay bus. Signals are first packed together into frames at the application-level and the frames are then transmitted over the bus. To ensure reliability of frames in the presence of faults, frames must be retransmitted over the bus but this comes at the cost of higher bandwidth utilization. To address this issue, in this paper, we propose a novel frame packing method for FlexRay bus. Our method computes the required number of retransmissions of frames that ensures the specified reliability goal. The proposed frame packing method also ensures that none of the signals violates its deadline and that the desired reliability goal for guaranteeing fault-tolerance is met at the minimum bandwidth cost. Extensive experiments on synthetic as well as a industrial case study demonstrate the benefits of our method.

  • 258.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling for Fault-Tolerant Communication on the Static Segment of FlexRay2010In: 31st IEEE Real-Time Systems Symposium (RTSS10), San Diego, CA, USA, November 30-December 3, 2010., IEEE Computer Society , 2010, 385-394 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay has been widely accepted as the next generation bus protocol for automotive networks. This has led to tremendous research interest in techniques for scheduling messages on the FlexRay bus, in order to meet the hard realtime deadlines of the automotive applications. However, these techniques do not generate reliable schedules in the sense that they do not provide any performance guarantees in the presence of faults. In this work, we will present a framework for generating fault-tolerant message schedules on the time-triggered (static) segment of the FlexRay bus. We provide formal guarantees that the generated fault-tolerant schedules achieve the reliability goal even in the presence of transient and intermittent faults. Moreover, our technique minimizes the required number of retransmissions of the messages in order to achieve such fault tolerant schedules, thereby, optimizing the bandwidth utilization. Towards this, we formulate the optimization problem in Constraint Logic Programming (CLP), which returns optimal results. However, this procedure is computationally intensive and hence, we also propose an efficient heuristic. The heuristic guarantees the reliability of the constructed schedules but might be sub-optimal with respect to bandwidth utilization. Extensive experiments run on synthetic test cases and real-life case studies illustrate that the heuristic performs extremely well. The experiments also establish that our heuristic scales significantly better than the CLP formulation.

  • 259.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Probabilistic Timing Analysis for the Dynamic Segment of FlexRay2013In: 25th Euromicro Conference on Real-Time Systems (ECRTS), IEEE , 2013, 135-144 p.Conference paper (Refereed)
    Abstract [en]

    We propose an analytical framework for probabilistic timing analysis of the event-triggered Dynamic segment of the FlexRay communication protocol. Specifically, our framework computes the Deadline Miss Ratios of each message. The core problem is formulated as a Mixed Integer Linear Program (MILP). Given the intractability of the problem, we also propose several techniques that help to mitigate the running times of our tool. This includes the re-engineering of the problem to run it on GPUs as well as re-formulating the MILP itself.

  • 260.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Kosuch, Stefanie
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Schedulability Analysis for the Dynamic Segment of FlexRay: A Generalization to Slot Multiplexing2012Conference paper (Refereed)
    Abstract [en]

    FlexRay, developed by a consortium of over hundred automotive companies, is a real-time communication protocol for automotive networks. In this paper, we propose a new approach for timing analysis of the event-triggered component of FlexRay, known as the dynamic segment. Our technique accounts for the fact that the FlexRay standard allows slot multiplexing, i.e., the same priority can be assigned to more than one message. Existing techniques have either ignored slot multiplexing in their analysis or made simplifying assumptions that severely limit achieving high bandwidth utilization. Moreover, we show that our technique returns less pessimistic results compared to previously known techniques even in the case where slot multiplexing is ignored.

  • 261.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Jenihhin, Maksim
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture2004In: The 5th IEEE Latin-American Test Workshop,2004, 2004, 98-103 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents an approach to the test time minimization problem for parallel hybrid BIST with test pattern broadcasting in core-based systems. The hybrid test set is assembled from pseudorandom test patterns that are generated online and deterministic test patterns that are generated off-line and stored in the system. The pseudorandom patterns are broadcasted and applied to all cores in parallel. The deterministic patterns are, on the other hand, generated for particular cores, one at a time, but applied (broadcasted) in parallel to all other cores and used for the rest of the system as pseudorandom patterns. We propose an iterative algorithm to find the optimal combination between those two test sets under given memory constraints, so that the systems testing time is minimized. Our approach employs a fast cost estimation method in order to avoid exhaustive search and to speed-up the optimization process. Experimental results have shown the efficiency of the algorithm to find a near-optimal solution with very few iterations.

  • 262.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Jenihhin, Maksim
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting2004In: The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004,2004, 2004Conference paper (Refereed)
    Abstract [en]

    This paper introduces a technique for hybrid BIST time optimization for testing core-based systems that use test pattern broadcasting for both pseudorandom and deterministic patterns. First we formulate the test time minimization problem for such an architecture. Thereafter we present algorithms for finding an efficient combination of pseudorandom and deterministic test sets under given memory constraints, so that the system testing time can be shortened. We also analyze the significance of the pseudorandom sequence quality for the final results. The results are illustrated and the efficiency of the approach is demonstrated by experimental results.

  • 263.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Jenihhin, Maksim
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting2003In: The 21st NORCHIP Conference,2003, 2003, 112-116 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes a hybrid BIST architecture for testing core-based systems together with a method for test time minimization. The approach uses test pattern broadcasting for both pseudorandom and deterministic patterns. To overcome the high complexity of the test time minimization problem we propose a fast algorithm to find an efficient combination of pseudorandom and deterministic test sets under given memory constraints. The efficiency of the approach is demonstrated by experimental results.

  • 264.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Orasson, Elmet
    Dept. Computer Engineering Tallinn University of Technology.
    Raidma, Rein
    Dept. Computer Engineering Tallinn University of Technology.
    Fast Test Cost Calculation for Hybrid BIST in Digital Systems2001In: Euromicro Symposium on Digital Systems Design,2001, Warsaw, Poland: IEEE Computer Society Press , 2001, 318- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored precomputed deterministic test patterns. A procedure is proposed for fast calculation of the cost of hybrid BIST at different lengths of pseudorandom test to find an optimal balance between test sets, and to perform core test with minimum cost of both, time and memory, and without losing in test quality. Compared to the previous approach, based on iterative use of deterministic ATPG for evaluating the cost of stored patterns, in this paper a new, extremely fast procedure is proposed, which calculates costs on a basis of fault table manipulations. Experiments on the ISCAS benchmark circuits show that the new procedure is about two orders of magnitude faster than the previous one.

  • 265.
    Ubar, Raimund
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Kruus, Helena
    Dept. Computer Engineering Tallinn University of Technology.
    Jervan, Gert
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Using Tabu Search Method for Optimizing the Cost of Hybrid BIST2001In: 16th Conference on Design of Circuits and Integrated Systems DCIS 2001,2001, 2001, 445-450 p.Conference paper (Refereed)
    Abstract [en]

    This paper deals with a hybrid BIST solution for testing systems-on-chip, which combines pseudo-random test patterns with stored precomputed deterministic test patterns. A method is proposed for finding the optimal balance between pseudorandom and stored test patterns to perform core test with minimum cost of time and memory, and without losing test quality. As a generalization of local optimization, Tabu search method is used for finding the optimal balance. Unlike local search which stops when no improved new solution is found in the current neighborhood, tabu search continues the search from the best solution in the neighborhood even if it is worse than the current solution. To speed up the optimization procedure, a fast method for predicting the location of optimum solution is also used. Experimental results on benchmark circuits have proved the efficiency of the proposed approach for BIST optimization.

  • 266.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bao, Min
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Steady-State Dynamic Temperature Analysis and Reliability Optimization for Embedded Multiprocessor Systems2012In: 49th ACM/EDAC/IEEE Design Automation Conference (DAC), 3-7 June 2012, San Francisco, ACM/ IEEE , 2012, 197-204 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we propose an analytical technique for the steady-state dynamic temperature analysis (SSDTA) of multiprocessor systems with periodic applications. The approach is accurate and, moreover, fast, such that it can be included inside an optimization loop for embedded system design. Using the proposed solution, a temperature-aware reliability optimization, based on the thermal cycling failure mechanism, is presented. The experimental results con firm the quality and speed of our SSDTA technique, compared to the state of the art. They also show that the lifetime of an embedded system can significantly be improved, without sacrificing its energy efficiency, by taking into consideration, during the design stage, the steady-state dynamic temperature profile of the system.

  • 267.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Probabilistic Analysis of Electronic Systems via Adaptive Hierarchical Interpolation2017In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 36, no 11, 1883-1896 p.Article in journal (Refereed)
    Abstract [en]

    We present a framework for system-level analysis of electronic systems whose runtime behaviors depend on uncertain parameters. The proposed approach thrives on hierarchical interpolation guided by an advanced adaptation strategy, which makes the framework general and suitable for studying various metrics that are of interest to the designer. Examples of such metrics include the end-to-end delay, total energy consumption, and maximum temperature of the system under consideration. The framework delivers a light generative representation that allows for a straightforward, computationally efficient calculation of the probability distribution and accompanying statistics of the metric at hand. Our technique is illustrated by considering a number of uncertainty-quantification problems and comparing the corresponding results with exhaustive simulations.

  • 268.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Probabilistic Analysis of Power and Temperature Under Process Variation for Electronic System Design2014In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 33, no 6, 931-944 p.Article in journal (Refereed)
    Abstract [en]

    Electronic system design based on deterministic techniques for power-temperature analysis is, in the context of current and future technologies, both unreliable and inefficient since the presence of uncertainty, in particular, due to process variation, is disregarded. In this paper, we propose a flexible probabilistic framework targeted at the quantification of the transient power and temperature variations of an electronic system. The framework is capable of modeling diverse probability laws of the underlying uncertain parameters and arbitrary dependencies of the system on such parameters. For the considered system, under a given workload, our technique delivers analytical representations of the corresponding stochastic power and temperature profiles. These representations allow for a computationally efficient estimation of the probability distributions and accompanying quantities of the power and temperature characteristics of the system. The approximation accuracy and computational time of our approach are assessed by a range of comparisons with Monte Carlo simulations, which confirm the efficiency of the proposed technique.

  • 269.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Temperature-Centric Reliability Analysis and Optimization of Electronic Systems under Process Variation2015In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 23, no 11, 2417-2430 p.Article in journal (Refereed)
    Abstract [en]

    Electronic system designs that ignore process variationare unreliable and inefficient. In this paper, we propose asystem-level framework for the analysis of temperature-inducedfailures that considers the uncertainty due to process variation.As an intermediate step, we also develop a probabilistic techniquefor dynamic steady-state temperature analysis. Given an electronicsystem under a certain workload, our framework deliversthe corresponding survival function, founded on the basis ofwell-established reliability models, with a closed-form stochasticparameterization in terms of the quantities that are uncertain atthe design stage. The proposed solution is exemplified consideringsystems with periodic workloads that suffer from the thermalcyclingfatigue. The analysis of this fatigue is a challengingproblem as it requires the availability of detailed temperatureprofiles, which are uncertain due to the variability of processparameters. To demonstrate the computational efficiency of ourframework, we undertake a design-space exploration procedureto minimize the expected energy consumption under a set oftiming, thermal, and reliability constraints.

  • 270.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Marculescu, Diana
    Department of Electrical and Computer Engineering, Carnegie Mellon University, USA.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Fast Synthesis of Power and Temperature Profiles for the Development of Data-Driven Resource Managers2017Report (Other academic)
    Abstract [en]

    The goal of this work is to facilitate the development of proactive power- and temperature-aware resource managers that leverage machine learning in order to attain their objectives. In this context, the availability of sufficiently large amounts of relevant data, which are essential for learning and, therefore, exploration of research ideas, is elusive. In order to fulfill the need, we present a toolchain for fast generation of realistic power and temperature profiles of computer systems. The toolchain provides profuse representative data to learn from during development stages. The overreaching objective is to help research by making it tractable to experiment with the highly promising but data-demanding state-of-the-art techniques for prediction.

  • 271.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Marculescu, Diana
    Department of Electrical and Computer Engineering, Carnegie Mellon University, USA.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Fine-Grained Long-Range Prediction of Resource Usage in Computer Clusters2017Report (Other academic)
    Abstract [en]

    In order to facilitate the development of intelligent resource managers of computer clusters, we investigate the utility of the state-of-the-art neural networks for the purpose of fine-grained long-range prediction of the resource usage in one such cluster. We consider a large data set of real-life traces and describe in detail our workflow, starting from making the data accessible for learning and finishing by predicting the resource usage of individual tasks multiple steps ahead. The experimental results indicate that such fine-grained traces as the ones considered possess a certain structure, and that this structure can be extracted by advanced machine-learning techniques and subsequently utilized for making informed predictions.

  • 272.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Villani, Mattias
    Linköping University, Department of Computer and Information Science, Statistics. Linköping University, Faculty of Arts and Sciences.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Statistical Analysis of Process Variation Based on Indirect Measurements for Electronic System Design2014In: 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), New York: IEEE conference proceedings, 2014, 436-442 p.Conference paper (Refereed)
    Abstract [en]

    We present a framework for the analysis of process variation across semiconductor wafers. The framework is capable of quantifying the primary parameters affected by process variation, e.g., the effective channel length, which is in contrast with the former techniques wherein only secondary parameters were considered, e.g., the leakage current. Instead of taking direct measurements of the quantity of interest, we employ Bayesian inference to draw conclusions based on indirect observations, e.g., on temperature. The proposed approach has low costs since no deployment of expensive test structures might be needed or only a small subset of the test equipments already deployed for other purposes might need to be activated. The experimental results present an assessment of our framework for a wide range of configurations.

  • 273.
    Varea, Mauricio
    et al.
    Dept. Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Cortes, Luis-Alejandro
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Symbolic Model Checking of Dual Transition Petri Nets2002In: 10th International Symposium on HardwareSoftware Codesign CODES 2002,2002, Estes Park, Colorado, USA: IEEE Computer Society Press , 2002, 43- p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the formal verification of the recently introduced Dual Transition Petri Net (DTPN) models, using model checking techniques. The methodology presented addresses the symbolic model checking of embedded systems behavioural properties, expressed in either computation tree logics (CTL) or linear temporal logics (LTL). The embedded system specification is given in terms of DTPN models, where elements of the model are captured in a four-module library which implements the behaviour of the model. Key issues in the development of the methodology are the heterogeneity and the nondeterministic nature of the model. This is handled by introducing some modifications in both structure and behaviour of the model, thus reducing the points of nondeterminism. Several features of the methodology are discussed and two examples are given in order to show the validity of the model.

  • 274.
    Varea, Mauricio
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al-Hashimi, Bashir
    Dept. of Electronics and Computer Science University of Southampton.
    Cortes, Luis-Alejandro
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Dual Flow Nets: Modelling the Control/Data-Flow Relation in Embedded Systems2006In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 5, no 1, 54-81 p.Article in journal (Refereed)
    Abstract [en]

    This paper addresses the interrelation between control and data flow in embedded system models through a new design representation, called Dual Flow Net (DFN). A modeling formalism with a very close-fitting control and data flow is achieved by this representation, as a consequence of enhancing its underlying Petri net structure. The work presented in this paper does not only tackle the modeling side in embedded systems design, but also the validation of embedded system models through formal methods. Various introductory examples illustrate the applicability of the DFN principles, whereas the capability of the model to with complex designs is demonstrated through the design and verification of a real-life Ethernet coprocessor.

  • 275.
    Wang, Q.
    et al.
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Wallin, A.
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Izosimov, Viacheslav
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Ingelsson, Urban
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Test tool qualification through fault injection2012In: Test Symposium (ETS 2012), IEEE , 2012Conference paper (Other academic)
    Abstract [en]

    According to ISO 26262, a recent automotive functional safety standard, verification tools shall undergo qualification, e.g. to ensure that they do not fail to detect faults that can lead to violation of functional safety requirements. We present a semi-automatic qualification method involving a monitor and fault injection that reduce cost in the qualification process. We experiment on a verification tool implemented in LabVIEW.

  • 276.
    Yang, Tianruo
    et al.
    IDA Linköpings Universitet.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Improved Register-Transfer Level Functional Partioning Approach for Testability2000In: Journal of systems architecture, ISSN 1383-7621, Vol. 46, no 3, 209-223 p.Article in journal (Refereed)
  • 277.
    Zhang, Ying
    et al.
    School of Software Engineering, Tongji University, China.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Jiang, Jianhui
    School of Software Engineering, Tongji University, China.
    Li, Huawei
    State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China.
    Fujita, Masahiro
    VLSI Design and Education Center, University of Tokyo, Japan .
    Temperature-Aware Software-Based Self-Testing for Delay Faults2015In: Proc. Design, Automation and Test in Europe Conference (DATE’15), Grenoble, France, Mar. 9-13, 2015., 2015Conference paper (Refereed)
    Abstract [en]

    Delay defects under high temperature have been one of the most critical factors to affect the reliability of computer systems, and the current test methods don’t address this problem properly. In this paper, a temperature-aware software-based selftesting (SBST) technique is proposed to self-heat the processors within a high temperature range and effectively test delay faults under high temperature. First, it automatically generates highquality test programs through automatic test instruction generation (ATIG), and avoids over-testing caused by nonfunctional patterns. Second, it exploits two effective powerintensive program transformations to self-heat up the processors internally. Third, it applies a greedy algorithm to search the optimized schedule of the test templates in order to generate the test program while making sure that the temperature of the processor under test is within the specified range. Experimental results show that the generated program is successful to guarantee delay test within the given temperature range, and achieves high test performance with functional patterns.

  • 278.
    Zhang, Ying
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Automatic Test Program Generation for Out-of-Order Superscalar Processors2012In: 21st IEEE Asian Test Symposium (ATS12), Niigata, Japan, November 19-22, 2012., IEEE, 2012Conference paper (Refereed)
    Abstract [en]

    This paper presents a high-level automatic test instruction generation (HATIG) technical that allows, for the first time, to test the scheduling unit of an out-of-order super scalar processor. This technique leverages on existing bounded model checking tools in order to generate software-based self-testing programs from a global EFSM model of the processor under test. The experimental results have demonstrated the efficiency of the proposed technique.

  • 279.
    Zhiyuan, He
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Rosinger, Paul
    University of Southampton.
    Al-Hashimi, Bashir
    University of Southampton.
    Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving2008In: Journal of electronic testing, ISSN 0923-8174, Vol. 24, no 1-3, 247-257 p.Article in journal (Refereed)
    Abstract [en]

    High temperature has become a major problem for system-on-chip testing. In order to reduce the test application time while keeping the temperatures of the cores under test within safe ranges, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test application time and, at the same time, prevent the temperatures of cores under test going beyond given limits. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling periods between test sequences so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, such that the cooling periods and the bandwidth of the test bus can be utilized for test data transportation, and hence the test application time can be reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use the constraint logic programming (CLP) to build the optimization model and find the optimal solution. As the optimization time of the CLP-based approach increases exponentially with the problem size, we also propose a heuristic which generates longer test schedules but requires substantially shorter optimization time. Experimental results have shown the efficiency of the proposed approach.

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