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  • 251.
    Nikolov, Dimitar
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing2010In: Proceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010, IEEE , 2010, 281-285 p.Conference paper (Refereed)
    Abstract [en]

    The probability for errors to occur in electronic systems is not known in advance, but depends on many factors including influence from the environment where the system operates. In this paper, it is demonstrated that inaccurate estimates of the error probability lead to loss of performance in a well known fault tolerance technique, Roll-back Recovery with checkpointing (RRC). To regain the lost performance, a method for estimating the error probability along with an adjustment technique are proposed. Using a simulator tool that has been developed to enable experimentation, the proposed method is evaluated and the results show that the proposed method provides useful estimates of the error probability leading to near-optimal performance of the RRC fault-tolerant technique.

  • 252.
    Nikolov, Dimitar
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization2011In: 5th Workshop on Dependable and Secure Nanocomputing (WSDN 2011), Hong Kong, June 27, 2011, IEEE , 2011Conference paper (Refereed)
    Abstract [en]

    Increasing soft error rates for semiconductor devices manufactured in later technologies enforces the use of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). However, RRC introduces time overhead that increases the completion (execution) time. For non-real-time systems, research have focused on optimizing RRC and shown that it is possible to find the optimal number of checkpoints such that the average execution time is minimal. While minimal average execution time is important, it is for real-time systems important to provide a high probability that deadlines are met. Hence, there is a need of probabilistic guarantees that jobs employing RRC complete before a given deadline. First, we present a mathematical framework for the evaluation of level of confidence, the probability that a given deadline is met, when RRC is employed. Second, we present an optimization method for RRC that finds the number of checkpoints that results in the minimal completion time while the minimal completion time satisfies a given level of confidence requirement. Third, we use the proposed framework to evaluate probabilistic guarantees for RRC optimization in non-real-time systems.

  • 253.
    Nikolov, Dimitar
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Singh, Virendra
    Indian Institute of Science, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Level of Confidence Study for Roll-back Recovery with Checkpointing2011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011, 2011Conference paper (Other academic)
    Abstract [en]

    Increasing soft error rates for semiconductor devices manufactured in later technologies enforces the use of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). However, RRC introduces time overhead that increases the completion (execution) time. For non-real-time systems, research have focused on optimizing RRC and shown that it is possible to find the optimal number of checkpoints such that the average execution time is minimal. While minimal average execution time is important, it is for real-time systems important to provide a high probability of meeting given deadlines. Hence, there is a need of probabilistic guarantees that jobs employing RRC complete before a given deadline. Therefore, in this paper we present a mathematical framework for the evaluation of level of confidence, the probability that a given deadline is met, when RRC is employed.

  • 254.
    Nikolov, Dimitar
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    On-line Techniques to Adjust and Optimize Checkpointing Frequency2010In: IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010, 2010, 29-33 p.Conference paper (Refereed)
    Abstract [en]

    Due to increased susceptibility to soft errors in recent semiconductor technologies, techniques for detecting and recovering from errors are required. Roll-back Recovery with Checkpointing (RRC) is one well known technique that copes with soft errors by taking and storing checkpoints during execution of a job. Employing this technique, increases the average execution time (AET), i.e. the expected time for a job to complete, and thus impacts performance. To minimize the AET, the checkpointing frequency is to be optimized. However, it has been shown that optimal checkpointing frequency depends highly on error probability. Since error probability cannot be known in advance and can change during time, the optimal checkpointing frequency cannot be known at design time. In this paper we present techniques that are adjusting the checkpointing frequency on-line (during operation) with the goal to reduce the AET of a job. A set of experiments have been performed to demonstrate the benefits of the proposed techniques. The results have shown that these techniques adjust the checkpointing frequency so well that the resulting AET is close to the theoretical optimum.

  • 255.
    Nikolov, Dimitar
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Study on the Level of Confidence for Roll-back Recovery with Checkpointing2011In: 1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011), Trondheim, Norway, May 26-27, 2011, 2011Conference paper (Refereed)
    Abstract [en]

    Increasing soft error rates for semiconductor devices manufactured in later technologies enforces the use of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). However, RRC introduces time overhead that increases the completion (execution) time. For non-real-time systems, research have focused on optimizing RRC and shown that it is possible to find the optimal number of checkpoints such that the average execution time is minimal. While minimal average execution time is important, it is for real-time systems important to provide a high probability of meeting given deadlines. Hence, there is a need of probabilistic guarantees that jobs employing RRC complete before a given deadline. Therefore, in this paper we present a mathematical framework for the evaluation of level of confidence, the probability that a given deadline is met, when RRC is employed.

  • 256.
    Nikolov, Dimitar
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Karlsson, Erik
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, Bangalore, India.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC2010In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper (Other academic)
  • 257.
    Nikolov, Dimitar
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Väyrynen, Mikael
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Singh, Virendra
    Indian Institute of Science, India.
    Optimizing Fault Tolerance for Multi-Processor System-on-Chip2010In: Design and Test Technology for Dependable Systems-on-chip / [ed] Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, Information Science Publishing , 2010, 578- p.Chapter in book (Other academic)
    Abstract [en]

    Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.

    Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined "classical" design and test topics and solutions for IC test technology and fault-tolerant systems.

  • 258.
    Nilsson, Peter
    et al.
    Department of Electro Science Lund University.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Tenhunnen, Hannu
    Department of Electronics Royal Institute of Technology.
    SOCWARE: A New Swedish Design Cluster For System-On-Chip2001In: International Conference on Microelectronic Systems Education,2001, Las Vegas, USA: IEEE Computer Society Press , 2001, 44- p.Conference paper (Refereed)
    Abstract [en]

    Socware is the name for a new design cluster in Sweden, which intends to unify university, research institutes, and industry towards a common goal, namely System-on-Chip. In this paper, one of the programs within the cluster, the Socware Research & Education Program, is presented. The program aims to organize a new education curriculum for System-on-Chip design. The education is directed to undergraduate and graduate students as well as Master's in industry. Totally, the Socware Design Cluster has 50 Meuro of public funds, where 15 Meuro are reserved for the Socware Research & Education program.

  • 259.
    Nunna, Swaroop
    et al.
    TU Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Chakraborty, Samarjit
    TU Munich, Germany.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Exploiting GPU On-Chip Shared Memory for Accelerating Schedulability Analysis2010In: International Symposium on Electronic System Design (ISED10), Bhubaneswar, India, December 2010., 2010Conference paper (Refereed)
    Abstract [en]

    Embedded electronic devices like mobile phones and automotive control units must perform under strict timing constraints. As such, schedulability analysis constitutes an important phase of the design cycle of these devices. Unfortunately, schedulability analysis for most realistic task models turn out to be computationally intractable (NP-hard). Naturally, in the recent past, different techniques have been proposed to accelerate schedulability analysis algorithms, including parallel computing on Graphics Processing Units (GPUs). However, applying traditional GPU programming methods in this context restricts the effective usage of on-chip memory and in turn imposes limitations on fully exploiting the inherent parallel processing capabilities of GPUs. In this paper, we explore the possibility of accelerating schedulability analysis algorithms on GPUs while exploiting the usage of on-chip memory. Experimental results demonstrate upto 9× speedup of our GPU-based algorithms over the implementations on sequential CPUs.

  • 260.
    Palmberg, Jenny
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ren, Lili
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    OSEK-kompatibilitet hos Enea OSEck2008Independent thesis Advanced level (degree of Master (One Year)), 20 credits / 30 HE creditsStudent thesis
    Abstract [sv]

    Målet med examensarbetet var att undersöka om det var möjligt att genomett kompatibilitetsbibliotek se till att Eneas realtidsoperativsystem OSEckkan uppfylla kraven i operativsystemsstandarden OSEK.OSEck visade sig tillhandahålla all efterfrågad funktionalitet och ett kompatibilitetsbiblioteksom innehöll OSEK’s API kunde därmed implementeras.Ett verktyg togs fram för att utifrån en fil, innehållandes objekt beskrivna iOSEK’s konfigurationsspråk OIL, plocka ut den information som behövdesf¨or att konfigurera både OSEck och OSEK.

    Slutsatsen av examensarbetet blev att det gick att göra OSEck OSEKkompatibeltgenom ett yttre lager och att inga ändringar i OSEck’s kärnavar nödvändiga. Givetvis påverkar lagret operativsystemets prestanda negativtmen det får ändå anses att dess prestanda fortfarande är så pass braatt en integration i OSEck’s kärna ej behövs.För att ett operativsystem ska kunna göras OSEK-kompatibelt måste detha prioritetsbaserad schemaläggning samt att task som blir avbrutna hamnarförst i sin prioritetskö. Dessutom måste det vara möjligt att exekverakod precis innan ett task börjar köra för första gången eftersom det skafinnas stöd för en PreTaskHook.

  • 261.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Building Reliable Embedded Systems with Unreliable Components2010In: Invited Paper - Proc. Intl. Conf. on Signals and Electronic Systems (ICSES10), Gliwice, Poland, September 7-10, 2010., 2010, 9-13 p.Conference paper (Other academic)
    Abstract [en]

    This paper deals with the design of embedded systems for safety-critical applications, where both fault-tolerance and real-time requirements should be taken into account at the same time. With silicon technology scaling, integrated circuits are implemented with smaller transistors, operate at higher clock frequency, and run at lower voltage levels. As a result, they are subject to more faults, in particular, transient faults. Additionally, in nano-scale technology, physics-based random variations play an important role in many device performance metrics, and have led to many new defects. We are therefore facing the challenge of how to build reliable and predictable embedded systems for safety-critical applications with unreliable components. This paper describes several key challenges and presents several emerging solutions to the design and optimization of such systems. In particular, it discusses the advantages of using time-redundancy based fault-tolerance techniques that are triggered by fault occurrences to handle transient faults and the hardware/software trade-offs related to fault detection and fault tolerance.

  • 262.
    Peng, Zebo
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    He, Zhiyuan
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Challenges and solutions for thermal-aware SOC testing2007In: Informacije midem, ISSN 0352-9045, Vol. 37, no 4, 220-227 p.Article in journal (Refereed)
    Abstract [en]

    High temperature has negative impact on the performance, reliability and lifespan of a system on chip. During testing, the chip can be overheated due to a substantial increase of switching activities and concurrent tests in order to reduce test application time. This paper discusses several issues related to the thermal problem during SoC testing. It will then present a thermal-aware SoC test scheduling technique to generate the shortest test schedule such that the temperature constraints of individual cores and the constraint on the test-bus bandwidth are satisfied. In order to avoid overheating during the test, we partition test sets into shorter test sub-sequences and add cooling periods in between. Further more, we interleave the test sub-sequences from different test sets in such a manner that the test-bus bandwidth reserved for one core is utilized during its cooling period for the test transportation and application of the other cores. We have developed a heuristic to minimize the test application time by exploring alternative test partitioning and interleaving schemes with variable length of test sub-sequences and cooling periods. Experimental results have shown the efficiency of the proposed heuristic.

  • 263.
    Peng, Zebo
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Emerging strategies for resource-constrained testing of system chips2005In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 152, no 1, 65-66 p.Other (Other academic)
  • 264.
    Pettersson, Ola
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Deliberation in a mobile robot2000Licentiate thesis, monograph (Other academic)
    Abstract [en]

        In the future mobile robots could be used in our offices as service robots. helping us with tasks such as picking up and delivering mail, returning borrowed books, or bringing coffee. To manage these service tasks in an unpredictable environment, the robot must have the ability to move robustly without bumping into people or furniture and to recognize its current location. The robot must also have high-level control that can reason about its given goals and find new ways to achieve its goals if something goes wrong. That is, it must "deliberate." Moreover, since the real world is unpredictable and the robot's sensors give noisy and sometimes incomplete information. the robot must be able to do so under uncertainty.

    The initial motivation of the research presented here is to study the problems involved in deliberation under uncertainty. Although the term "deliberation" is often applied to different components of robot architectures, we have found that this concept is not well defined in the literature. Therefore this work presents our analysis of deliberation itself. as a necessary prerequisite to a deeper study of specific techniques that are needed in deliberation. This analysis leads us to propose a working definition of deliberation. During the analysis we make a few preliminary experiments on a simulated mobile robot. These experiments give us a deeper understanding of the problems involved in deliberation and help us forming the working definition.

    This document is the midway milestone in an ongoing study of deliberation under uncertainty, intended to result in a Ph.D. thesis.

  • 265.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Analysis and Synthesis of Communication-Intensive Heterogeneous Real-Time Systems2004Other (Other (popular science, discussion, etc.))
  • 266.
    Pop, Paul
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Analysis and Synthesis of Communication-Intensive Heterogeneous Real-Time Systems2003Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Embedded computer systemsare now everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded computer systems. An important class of embedded computer systems is that of real-time systems, which have to fulfill strict timing requirements. As real-time systems become more complex, they are often implemented using distributed heterogeneous architectures.

    The main objective of the thesis is to develop analysis and synthesis methods for communication-intensive heterogeneous hard real-time systems. The systems are heterogeneous not only in terms of platforms and communication protocols, but also in terms of scheduling policies. Regarding this last aspect, in this thesis we consider time-driven systems, event-driven systems, and a combination of both, called multi-cluster systems. The analysis takes into account the heterogeneous interconnected nature of the architecture, and is based on an application model that captures both the dataflow and the flow of control. The proposed synthesis techniques derive optimized implementations of the system that fulfill the design constraints. An important part of the system implementation is the synthesis of the communication infrastructure, which has a significant impact on the overall system performance and cost.

    To reduce the time-to-market of products, the design of real-time systems seldom starts from scratch. Typically, designers start from an already existing system, running certain applications, and the design problem is to implement new functionality on top of this system. Hence, in addition to the analysis and synthesis methods proposed, we have also considered mapping and scheduling within such an incremental design process.

    The analysis and synthesis techniques proposed have been thoroughly evaluated using a solid experimental platform. Besides the evaluations, performed using a large number of generated example applications, we have also validated our approaches using a realistic case study consisting of a vehicle cruise controller.

  • 267.
    Pop, Paul
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Embedded systems design: Optimization challenges2005In: Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems: Second International Conference, CPAIOR 2005, Prague, Czech Republic, May 31-June 1, 2005. Proceedings / [ed] Roman Barták and Michela Milano, Springer Berlin/Heidelberg, 2005, Vol. 3524, 16-16 p.Chapter in book (Refereed)
    Abstract [en]

    Embedded systems are everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded systems. Over 99% of the microprocessors produced today are used in embedded systems, and recently the number of embedded systems in use has become larger than the number of humans on the planet.

  • 268.
    Pop, Paul
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling and Communication Synthesis for Distributed Real-Time Systems2000Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Embedded systems are now omnipresent: from cellular phones to pagers, from microwave ovens to PDAs, almost all the devices we use are controlled by embedded systems. Many embedded systems have to fulfill strict requirements in terms of performance and cost efficiency. Emerging designs are usually based on heterogeneous architectures that integrate multiple programmable processors and dedicated hardware components. New tools which extend design automation to system level have to support the integrated design of both the hardware and software components of such systems. This thesis concentrates on aspects of scheduling and communication for embedded real-time systems. Special emphasis has been placed on the impact of the communication infrastructure and protocol on the overall system performance. The scheduling and communication strategies proposed are based on an abstract graph representation which captures, at process level, both the dataflow and the flow of control. We have considered non-preemptive static cyclic scheduling and preemptive scheduling with static priorities for the scheduling of processes, while the communications are statically scheduled according to the time triggered protocol. We have developed static cyclic scheduling algorithms for time-driven systems with control and data dependencies. We show that by considering aspects of the communication protocol, significant improvements can be gained in the schedule quality. In the context of event-driven systems we have proposed a less pessimistic schedulability analysis that is able to handle both control and data dependencies. Moreover, we have provided a schedulability analysis for the time-triggered protocol, and we have proposed several optimization strategies for the synthesis of communication protocol parameters. Extensive experiments as well as real-life examples demonstrate the efficiency of our approaches.

  • 269.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Scheduling, Mapping and Communication Synthesis for Distributed Real-Time Systems2002Other (Other (popular science, discussion, etc.))
  • 270.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Analysis and optimisation of heterogeneous real-time embedded systems2006In: System On Chip: Next Generation Electronics / [ed] Al-Hashimi, Bashir, Stevenage, Herts, United Kingdom: The Institution of Engineering and Technology , 2006, 75-120 p.Chapter in book (Other academic)
    Abstract [en]

    We have presented an analysis for multi-cluster systems and outlined several characteristic design problems, related to the partitioning and mapping of functionality and the optimisation of the access to the communication infrastructure. An approach to schedulability-driven frame packing for the synthesis of multi-cluster systems was presented as an example of solving such a design optimisation problem. We have developed two optimisation heuristics for frame configuration synthesis which are able to determine frame configurations that lead to a schedulable system. We have shown that by considering the frame packing problem, we are able to synthesise schedulable hard real-time systems and to potentially reduce the overall cost of the architecture.

  • 271.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Analysis and optimisation of heterogeneous real-time embedded systems2005In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 152, no 2, 130-147 p.Article in journal (Refereed)
    Abstract [en]

    An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous, not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can have its own scheduling policy, and several scheduling policies can share a processor. In this context, the task of designing such systems is becoming increasingly important and difficult at the same time. The success of such new design methods depends on the availability of analysis and optimisation techniques. Analysis and optimisation techniques for heterogeneous real-time embedded systems are presented in the paper. The authors address in more detail a particular class of such systems called multi-clusters, composed of several networks interconnected via gateways. They present a schedulability analysis for safety-critical applications distributed on multi-cluster systems and briefly highlight characteristic design optimisation problems: the partitioning and mapping of functionality, and the packing of application messages to frames. Optimisation heuristics for frame packing aimed at producing a schedulable system are presented. Extensive experiments and a real-life example show the efficiency of the frame-packing approach.

  • 272.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Analysis and Optimization of Heterogeneous Real-Time Embedded Systems2005In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 152, no 2, 130-147 p.Article in journal (Refereed)
    Abstract [en]

    An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can have its own scheduling policy, and several scheduling policies can share a processor. In this context, the task of designing such systems is becoming increasingly important and difficult at the same time. The success of such new design methods depends on the availability of analysis and optimization techniques. In this paper, we present analysis and optimization techniques for heterogeneous real-time embedded systems. We address in more detail a particular class of such systems called multi-clusters, composed of several networks interconnected via gateways. We present a schedulability analysis for safety-critical applications distributed on multi-cluster systems and briefly highlight characteristic design optimization problems: the partitioning and mapping of functionality, and the packing of application messages to frames. Optimization heuristics for frame packing aiming at producing a schedulable system are presented. Extensive experiments and a real-life example show the efficiency of the frame-packing approach.

  • 273.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Analysis and Synthesis of Distributed Real-Time Embedded Systems2004Book (Other academic)
    Abstract [en]

    Embedded computer systems are now everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded computers. An important class of embedded computer systems is that of hard real-time systems, which have to fulfill strict timing requirements. As real-time systems become more complex, they are often implemented using distributed heterogeneous architectures. Analysis and Synthesis of Distributed Real-Time Embedded Systems addresses the design of real-time applications implemented using distributed heterogeneous architectures. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Regarding this last aspect, time-driven and event-driven systems, as well as a combination of the two, are considered. Such systems are used in many application areas like automotive electronics, real-time multimedia, avionics, medical equipment, and factory systems. The proposed analysis and synthesis techniques derive optimized implementations that fulfill the imposed design constraints. An important part of the implementation processis the synthesis of the communication infrastructure, which has a significant impact on the overall system performance and cost. Analysis and Synthesis of Distributed Real-Time Embedded Systems considers the mapping and scheduling tasks within an incremental design process. To reduce the time-to-market of products, the design of real-time systems seldom starts from scratch. Typically, designers start from an already existing system, running certain applications, and the design problem is to implement new functionality on top of this system. Supporting such an incremental design process provides a high degree of flexibility, and can result in important reductions of design costs. Analysis and Synthesis of Distributed Real-Time Embedded Systems will be of interest to advanced undergraduates, graduate students, researchers and designers involved in the field of embedded systems.

  • 274.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications2006In: ARTES -: A network for Real-Time research and graduate Education in Sweden 1997-2006 / [ed] Hans Hansson, Uppsala: The Department of Information Technology , 2006, 49-101 p.Chapter in book (Other academic)
    Abstract [en]

    An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can have its own scheduling policy, and several scheduling policies can share a processor. In this context, the task of designing such systems is becoming increasingly important and difficult at the same time. The success of such new design methods depends on the availability of analysis and optimization techniques. In this paper, we present analysis and optimization techniques for heterogeneous real-time embedded systems. We address in more detail a particular class of such systems called multi-clusters, composed of several networks interconnected via gateways. We present a schedulability analysis for safety-critical applications distributed on multi-cluster systems and briey highlight characteristic design optimization problems: the partitioning and mapping of functionality, and the packing of application messages to frames. Optimization heuristics for frame packing aiming at producing a schedulable system are presented. Extensive experiments and a real-life example show the efficiency of the frame-packing approach.

  • 275.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Distributed Embedded Real-Time Systems - Analysis and Exploration2005In: Embedded Systems Design: The ARTIST Roadmap for Research and Development / [ed] Bruno Bouyssounouse ; Joseph Sifakis, New York: Springer Verlag , 2005, 406-422 p.Chapter in book (Other academic)
    Abstract [en]

    This extensive and increasing use of embedded systems and their integration in everyday products mark a significant evolution in information science and technology. Nowadays embedded systems design is subject to seamless integration with the physical and electronic environment while meeting requirements like reliability, availability, robustness, power consumption, cost, and deadlines. Thus, embedded systems design raises challenging problems for research, such as security, reliable and mobile services, large-scale heterogeneous distributed systems, adaptation, component-based development, and validation and tool-based certification.

    This book results from the ARTIST FP5 project funded by the European Commision. By integration 28 leading European research institutions with many top researchers in the area, this book assesses and strategically advances the state of the art in embedded systems. The coherently written monograph-like book is a valuable source of reference for researchers active in the field and serves well as an introduction to scientists and professionals interested in learning about embedded systems design.

  • 276.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Flexibility Driven Scheduling and Mapping for Distributed Real-Time Systems2002In: 8th International Conference on Real-Time Computing Systems and Applications RTCSA 2002,2002, 2002, 337-346 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to mapping and scheduling of distributed hard real-time systems, aiming at improving the flexibility of the design process. We consider an incremental design process that starts from an already existing system running a set of applications, with preemptive priority based scheduling at the process level, and time triggered static scheduling at the communication level. We are interested to implement new functionality so that the already running applications are disturbed as little as possible and there is a good chance that, later, new functionality can easily be added to the resulted system. The mapping and scheduling problems are considered in the context of a realistic communication model based on a TDMA protocol. Extensive experiments as well as a real life example demonstrate the relevance of this problem and the efficiency of our solutions.

  • 277.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Performance Estimation for Embedded Systems with Data and Control Dependencies2000In: 8th International Workshop on HardwareSoftware Codesign CODES 2000,2000, San Diego, USA: IEEE Computer Society Press , 2000, 62-66 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to performance estimation for hard real-time systems. We consider architectures consisting of multiple processors. The scheduling policy is based on a preemptive strategy with static priorities. Our model of the system captures both data and control dependencies, and the analysis is able to reduce the pessimism of the estimation by using the knowledge about these dependencies. Extensive experiments as well as a real life example demonstrate the efficiency of our approach.

  • 278.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems2003In: Design Automation and Test in Europe DATE 2003 Conference,2003, Munich, Germany: IEEE Computer Society Press , 2003, 184- p.Conference paper (Refereed)
    Abstract [en]

    We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

  • 279.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems2003In: IEE journal on computers and digital techniques / Institution of electrical engineers, ISSN 0140-1335, Vol. 150, no 5, 303-312 p.Article in journal (Refereed)
    Abstract [en]

    We present an approach to schedulability analysis for the synthesis of multicluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst-case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

  • 280.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis for Systems with Data and Control Dependencies2000In: 12th Euromicro Conference on Real-Time Systems,2000, Stockholm, Sweden: IEEE Computer Society Press , 2000, 201-208 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to schedulability analysis for hard real-time systems with control and data dependencies. We consider distributed architectures consisting of multiple programmable processors, and the scheduling policy is based on a static priority preemptive strategy. Our model of the system captures both data and control dependencies, and the schedulability approach is able to reduce the pessimism of the analysis by using the knowledge about control and data dependencies. Extensive experiments as well as a real life example demonstrate the efficiency of our approach.

  • 281.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems2006In: ARTES: A network for Real-Time research and graduate Education in Sweden 1997-2006 / [ed] Hans Hansson, Uppsala: The Department of Information Technology , 2006, 537-569 p.Chapter in book (Other academic)
    Abstract [en]

    We present an approach to static priority preemptive process scheduling for the synthesis of hard real-time distributed embedded systems where communication plays an important role. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays with four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the synthesis of communication are developed, and the four approaches to message scheduling are compared using extensive experiments.

  • 282.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability-Driven Communication Synthesis for Time-Triggered Embedded Systems2004In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 26, no 3, 297-325 p.Article in journal (Refereed)
    Abstract [en]

    We present an approach to static priority preemptive process scheduling for the synthesis of hard real-time distributed embedded systems where communication plays an important role. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays with four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the synthesis of communication are developed, and the four approaches to message scheduling are compared using extensive experiments.

  • 283.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Schedulability-Driven Frame Packing for Multi-Cluster Distributed Embedded Systems2003In: LCTES '03 Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems, New York, NY, United States: Association for Computing Machinery (ACM), 2003, Vol. 38 issue 7, 113-122 p.Conference paper (Other academic)
    Abstract [en]

    We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable. Thus, we have also proposed a schedulability analysis for applications consisting of mixed event-triggered and time-triggered processes and messages, and a worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for frame packing aiming at producing a schedulable system have been proposed. Extensive experiments and a real-life example show the efficiency of our frame-packing approach.

  • 284.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Schedulability-driven frame packing for multicluster distributed embedded systems2005In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 4, no 1, 112-140 p.Article in journal (Refereed)
    Abstract [en]

    We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable, thus the end-to-end message communication constraints are satisfied. We have proposed a schedulability analysis for applications consisting of mixed event-triggered and timetriggered processes and messages, and a worst-case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for frame packing aiming at producing a schedulable system have been proposed. Extensive experiments and a real-life example show the efficiency of our frame-packing approach.

  • 285.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Izosimov, Viacheslav
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems2004In: 16th Euromicro Conference on Real-Time Systems,2004, Catania, Sicily: IEEE Computer Society Press , 2004, 91- p.Conference paper (Refereed)
    Abstract [en]

    We present an approach to partitioning and mapping for multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have proposed a schedulability analysis for such systems, including a worst-case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Based on this analysis, we address design problems which are characteristic to multi-clusters: partitioning of the system functionality into time-triggered and event-triggered domains, and process mapping. We present a branch and bound algorithm for solving these problems. Our heuristic is able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

  • 286.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Izosimov, Viacheslav
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Hellring, Magnus
    Dept. of Electronics and Software Volvo Technology Corporation.
    Bridal, Olof
    Dept. of Electronics and Software Volvo Technology Corporation.
    Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications2004In: Design, Automation and Test in Europe DATE 2004,2004, Paris, France: IEEE Computer Society Press , 2004, 1028- p.Conference paper (Refereed)
    Abstract [en]

    We present an approach to design optimization of multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In this paper, we address design problems which are characteristic to multi-clusters: partitioning of the system functionality into time-triggered and event-triggered domains, process mapping, and the optimization of parameters corresponding to the communication protocol. We present several heuristics for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example.

  • 287.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Traian
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Analysis and optimization of distributed real-time embedded systems2006In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 11, no 3, 593-625 p.Article in journal (Refereed)
    Abstract [en]

    An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous not only in terms of hardware and software components, but also in terms of communication protocols and scheduling policies. In this context, the task of designing such systems is becoming increasingly difficult. The success of new adequate design methods depends on the availability of efficient analysis as well as optimization techniques. In this article, we present both analysis and optimization approaches for such heterogeneous distributed real-time embedded systems. More specifically, we discuss the schedulability analysis of hard real-time systems, highlighting particular aspects related to the heterogeneous and distributed nature of the applications. We also introduce several design optimization problems characteristic of this class of systems: mapping of functionality, the optimization of access to communication channel, and the assignment of scheduling policies to processes. Optimization heuristics aiming at producing a schedulable system with a given amount of resources are presented. © 2006 ACM.

  • 288.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Traian
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems2004In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 12, no 8, 793-811 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, we present an approach to mapping and scheduling of distributed embedded systems for hard real-time applications, aiming at a minimization of the system modification cost. We consider an incremental design process that starts from an already existing system running a set of applications. We are interested in implementing new functionality such that the timing requirements are fulfilled and the following two requirements are also satisfied: 1) the already running applications are disturbed as little as possible and 2) there is a good chance that later, new functionality can easily be added to the resulted system. Thus, we propose a heuristic that finds the set of already running applications which have to be remapped and rescheduled at the same time with mapping and scheduling the new application, such that the disturbance on the running system (expressed as the total cost implied by the modifications) is minimized. Once this set of applications has been determined, we outline a mapping and scheduling algorithm aimed at fulfilling the requirements stated above. The approaches have been evaluated based on extensive experiments using a large number of generated benchmarks as well as a real-life example.

  • 289.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Traian
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Approach to Incremental Design of Distributed Embedded Systems2001In: 38th Design Automation Conference DAC,2001, Las Vegas, USA: IEEE Computer Society Press , 2001, 450-455 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to incremental design of distributed embedded systems for hard real-time applications. We start from an already existing system running a set of applications and the design problem is to implement new functionality on this system. Thus, we propose mapping strategies of functionality so that the already running functionality is not disturbed and there is a good chance that, later, new functionality can easily be mapped on the resulted system. The mapping and scheduling for hard real-time embedded systems are considered the context of a realistic communication model. Several experiments demonstrate the efficiency of the approach.

  • 290.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Traian
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Minimizing System Modification in an Incremental Design Approach2001In: International Workshop on HardwareSoftware Codesign CODES 2001,2001, Copenhagen, Denmark: IEEE Computer Society Press , 2001, 183- p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to mapping and scheduling of distributed embedded systems for hard real-time applications, aiming at minimizing the system modification cost. We consider an incremental design process that starts from an already existing sys-tem running a set of applications. We are interested to implement new functionality so that the already running applications are dis-turbed as little as possible and there is a good chance that, later, new functionality can easily be added to the resulted system. The mapping and scheduling problem are considered in the context of a realistic communication model based on a TDMA protocol.

  • 291.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ernst, Rolf
    IDA Technical University of Braunschweig.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Automotive Industry2005In: Embedded Systems Design: The ARTIST Roadmap for Research and Development / [ed] Bruno Bouyssounouse and Joseph Sifakis, New York: Springer Verlag , 2005, 377-382 p.Chapter in book (Other academic)
    Abstract [en]

    This extensive and increasing use of embedded systems and their integration in everyday products mark a significant evolution in information science and technology. Nowadays embedded systems design is subject to seamless integration with the physical and electronic environment while meeting requirements like reliability, availability, robustness, power consumption, cost, and deadlines. Thus, embedded systems design raises challenging problems for research, such as security, reliable and mobile services, large-scale heterogeneous distributed systems, adaptation, component-based development, and validation and tool-based certification.

    This book results from the ARTIST FP5 project funded by the European Commision. By integration 28 leading European research institutions with many top researchers in the area, this book assesses and strategically advances the state of the art in embedded systems. The coherently written monograph-like book is a valuable source of reference for researchers active in the field and serves well as an introduction to scientists and professionals interested in learning about embedded systems design.

  • 292.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Goller, A
    TTTech Computertechnik AG.
    Pop, Traian
    Ericsson AB, Sweden.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Development Tools2012In: Time-Triggered Communication / [ed] Roman Obermaisser, Boca Raton, FL, USA: CRC Press, 2012, 1, 361-493 p.Chapter in book (Other academic)
    Abstract [en]

    Addressing key concepts, properties, and algorithms, this book offers a conceptual foundation of time-triggered communication. Contributions from experts help readers understand the various time-triggered communication protocols, including their differences and commonalities. Communication protocols covered include TTP, FlexRay, TTEthemet, SAFEbus, TTCAN and LIN. Protocols range from low-cost time-triggered fieldbus networks to ultra-reliable time-triggered networks for safety-critical applications. The text also presents information about the use of FlexRay in cars, TTP in railway and avionic systems, and TTEthemet in aerospace applications"-- 

    • "Embedded computers are by far the most common type of computer in use today. Ninety-eight percent of all computing devices are embedded in different kinds of electronic equipment such as automotive, industrial automation, telecommunications, consumer electronics and health/medical systems. Due to the many different and, partially, contradicting requirements, there exists no single model for building embedded systems. Well-known tradeoffs are predictability versus flexibility or resource adequacy versus best-effort strategies. Therefore, the chosen system model depends strongly on the requirements of the application"-- 
  • 293.
    Pop, Paul
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Izosimov, Viacheslav
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ion Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng , Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication2009In: IEEE Transactions on VLSI Systems, ISSN 1063-8210 , Vol. 17, no 3, 389-402 p.Article in journal (Refereed)
    Abstract [en]

    We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes and communications are statically scheduled. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that multiple transient faults are tolerated and the timing constraints of the application are satisfied. We present several design optimization approaches which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

  • 294.
    Pop, Paul
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Poulsen, Kåre
    Informatics and Mathematical Modelling Dept. Technical University of Denmark.
    Izosimov, Viacheslav
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Scheduling and Voltage Scaling for Energy/Reliability Trade-offs in Fault-Tolerant Time-Triggered Embedded Systems2007In: 5th Intl. Conf. on Hardware/Software Codesign and System Synthesis CODES+ISSS,2007, Salzburg, Austria: IEEE Computer Society Press , 2007, 233- p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to the scheduling and voltage scaling of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. Addressing simultaneously energy and reliability is especially challenging because lowering the voltage to reduce the energy consumption has been shown to exponentially increase the number of transient faults. In addition, time-redundancy based fault-tolerance techniques such as re-execution and dynamic voltage scaling-based low-power techniques are competing for the slack in the schedules. Our approach decides the voltage levels and start times of processes and the transmission times of messages, such that the transient faults are tolerated, the timing constraints of the application are satisfied and the energy is minimized. We present a constraint logic programming- based approach which is able to find reliable and schedulable implementations within limited energy and hardware resources. The developed algorithms have been evaluated using extensive experiments.

  • 295.
    Pop, Traian
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Analysis and Optimisation of Distributed Embedded Systems with Heterogeneous Scheduling Policies2007Doctoral thesis, monograph (Other academic)
    Abstract [en]

    The growing amount and diversity of functions to be implemented by the current and future embedded applications (like, for example, in automotive electronics) have shown that, in many cases, time-triggered and event-triggered functions have to coexist on the computing nodes and to interact over the communication infrastructure. When time-triggered and event-triggered activities have to share the same processing node, a natural way for the execution support can be provided through a hierarchical scheduler. Similarly, when such heterogeneous applications are mapped over a distributed architecture, the communication infrastructure should allow for message exchange in both time-triggered and event-triggered manner in order to ensure a straightforward interconnection of heterogeneous components.

    This thesis studies aspects related to the analysis and design optimisation for safety-critical hard real-time applications running on hierarchically scheduled distributed embedded systems. It first provides the basis for the timing analysis of the activities in such a system, by carefully taking into consideration all the interferences that appear at run-time between the processes executed according to different scheduling policies. Moreover, due to the distributed nature of the architecture, message delays are also taken into consideration during the timing analysis. Once the schedulability analysis has been provided, the entire system can be optimised by adjusting its configuration parameters. In our work, the entire optimisation process is directed by the results from the timing analysis, with the goal that in the end the timing constraints of the application are satisfied. The analysis and design methodology proposed in the first part of the thesis is applied next on the particular category of distributed systems that use FlexRay as a communication protocol. We start by providing a schedulability analysis for messages transmitted over a FlexRay bus, and then by proposing a bus access optimisation algorithm that aims at improving the timing properties of the entire system.

    For all the problems that we investigated, we have carried out extensive experiments in order to measure the efficiency of the proposed solutions. The results have confirmed both the importance of the addressed aspects during system-level design, and the applicability of our techniques for analysing and optimising the studied systems.

  • 296.
    Pop, Traian
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling and Optimisation of Heterogeneous Time/Event-Triggered Distributed Embedded Systems2003Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Day by day, we are witnessing a considerable increase in number and range of applications which entail the use of embedded computer systems. This increase is closely followed by the growth in complexity of applications controlled by embedded systems, often involving strict timing requirements, like in the case of safety-critical applications. Efficient design of such complex systems requires powerful and accurate tools that support the designer from the early phases of the design process.

    This thesis focuses on the study of real-time distributed embedded systems and, in particular, we concentrate on a certain aspect of their real-time behavior and implementation: the time-triggered (TT) and event-triggered (ET) nature of the applications and of the communication protocols. Over the years, TT and ET systems have been usually considered independently, assuming that an application was entirely ET or TT. However, nowadays, the growing complexity of current applications has generated the need for intermixing TT and ET functionality. Such a development has led us to the identification of several interesting problems that are approached in this thesis. First, we focus on the elaboration of a holistic schedulability analysis for heterogeneous TT/ET task sets which interact according to a communication protocol based on both static and dynamic messages. Second, we use the holistic schedulability analysis in order to guide decisions during the design process. We propose a design optimisation heuristic that partitions the task-set and the messages into the TT and ET domains, maps and schedules the partitioned functionality, and optimises the communication protocol parameters. Experiments have been carried out in order to measure the efficiency of the proposed techniques.

  • 297.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems2003In: CODES-ISSS 2003 merged conference,2003, Newport Beach, California: IEEE Computer Society Press , 2003, 83- p.Conference paper (Refereed)
    Abstract [en]

    Distributed embedded systems implemented with mixed, event-triggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases, are emerging as the new standard in application areas such as automotive electronics. In a previous paper, we have developed a fholistic timing analysis and scheduling approach for this category of systems. Based on this result, in the present paper, new design problems are solved, whichwe identified as characteristic for such hybrid systems: partitioning of the system functionality into time-triggered and event-triggered domains and the optimization of parameters corresponding to the communication protocol. We addressed both problems in the context of a heuristic which performs mapping and scheduling of the system functionality. We demonstrated the efficiency of the proposed technique with extensive experiments.

  • 298.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Holistic Scheduling and Analysis of Mixed Time/Event-Triggered Distributed Embedded Systems2002In: 10th International Symposium on HardwareSoftware Codesign CODES 2002,2002, Estes Park, Colorado, USA: IEEE Computer Society Press , 2002, 187- p.Conference paper (Refereed)
    Abstract [en]

    This paper deals with specific issues related to the design of distributed embedded systems implemented with mixed, event-triggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases. Such systems are emerging as the new standard for automotive applications. We have developed a holistic timing analysis and scheduling approach for this category of systems. We have also identified several new design problems characteristic to such hybrid systems. An example related to bus access optimization in the context of a mixed static/dynamic bus protocol is presented. Experimental results prove the efficiency of such an optimization approach.

  • 299.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis for Distributed Heterogeneous Time/Event-Triggered Real-Time Systems2003In: 15th Euromicro Conference on Real-Time Systems ECRTS 2003,2003, Porto, Portugal: IEEE Computer Society Press , 2003, 257- p.Conference paper (Refereed)
    Abstract [en]

    This paper deals with specific issues related to the design of distributed embedded systems implemented with mixed, event-triggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases. Such systems are emerging as a new standard for automotive applications. We have developed a holistic timing analysis and scheduling approach for this category of systems. Three alternative scheduling heuristics are presented and compared. We have also identified several new design problems characteristic to such hybrid systems. An example related to bus access optimization in the context of a mixed static/dynamic bus protocol is presented. Experimental results prove the efficiency of such an optimization approach.

  • 300.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, P.
    Informatics and Mathematical Modelling, Technical University of Denmark, Building 322, Kongens Lyngby 2800, Denmark.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Analysis and optimisation of hierarchically scheduled multiprocessor embedded systems2008In: International journal of parallel programming, ISSN 0885-7458, E-ISSN 1573-7640, Vol. 36, no 1, 37-67 p.Article in journal (Refereed)
    Abstract [en]

    We present an approach to the analysis and optimisation of heterogeneous multiprocessor embedded systems. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. When several scheduling policies share a resource, they are organised in a hierarchy. In this paper, we first develop a holistic scheduling and schedulability analysis that determines the timing properties of a hierarchically scheduled system. Second, we address design problems that are characteristic to such hierarchically scheduled systems: assignment of scheduling policies to tasks, mapping of tasks to hardware components, and the scheduling of the activities. We also present several algorithms for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilisation of the system. The developed algorithms are evaluated using extensive experiments and a real-life example. © 2007 Springer Science+Business Media, LLC.

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