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  • 201.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Andrei, Alexandru
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Timing analysis of the FlexRay communication protocol2008In: Real-time systems, ISSN 0922-6443, Vol. 39, no 1-3, 205-235 p.Article in journal (Refereed)
    Abstract [en]

    FlexRay is a communication protocol heavily promoted on the market by a large group of car manufacturers and automotive electronics suppliers. However, before it can be successfully used for safety-critical applications that require predictability, timing analysis techniques are necessary for providing bounds for the message communication times. In this paper, we propose techniques for determining the timing properties of messages transmitted in both the static and the dynamic segments of a FlexRay communication cycle. The analysis techniques for messages are integrated in the context of a holistic schedulability analysis that computes the worst-case response times of all the tasks and messages in the system. We have evaluated the proposed analysis techniques using extensive experiments. We also present and evaluate three optimisation algorithms that can be used to improve the schedulability of a system that uses FlexRay. © 2007 Springer Science+Business Media, LLC.

  • 202.
    Pop, Traian
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Andrei, Alexandru
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Timing Analysis of the FlexRay Communication Protocol2006In: 18th Euromicro Conference on Real-Time Systems ECRTS 06,2006, Dresden, Germany: IEEE Computer Society Press , 2006, 203- p.Conference paper (Refereed)
    Abstract [en]

    FlexRay will very likely become the de-facto standard for in-vehicle communications. However, before it can be successfully used for safety-critical applications that require predictability, timing analysis techniques are necessary for providing bounds for the message communication times. In this paper, we propose techniques for determining the timing properties of messages transmitted in both the static (ST) and the dynamic (DYN) segments of a FlexRay communication cycle. The analysis techniques for messages are integrated in the context of a holistic schedulability analysis that computes the worst-case response times of all the tasks and messages in the system. We have evaluated the proposed analysis techniques using extensive experiments.

  • 203.
    Rafiliu, Sergiu Aurel
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Low Overhead Dynamic QoS Optimization Under Variable Task Execution Times2010In: 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2010), Macau SAR, P.R.C.: IEEE, 2010Conference paper (Refereed)
    Abstract [en]

    Today's embedded systems are typically exposed to varying load, due to e.g. changing num- ber of tasks and variable task execution times. At the same time, many of the most frequent real-life applications are not characterized by hard real-time constraints and their design goal is not to satisfy certain hard deadlines in the worst case. Moreover, from the user's perspective, achieving a high level of processor utilization is also not a primary goal. What the user needs, is to exploit the available resources (in our case processor time) such that a high level of quality of service (QoS) is delivered. In this paper we propose efficient run-time approaches, able to distribute the processor bandwidth such that the global QoS pro- duced by a set of applications is maximized, in the context in which the processor demand from individual tasks is continuously varying. Extensive experiments demonstrate the efficiency of the proposed approaches.

  • 204.
    Rafiliu, Sergiu Aurel
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru Lon
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Lemmon, Michael
    University of Notre Dame, IN 46556 USA.
    Stability of Online Resource Managers for Distributed Systems under Execution Time Variations2015In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 14, no 2, 21- p.Article in journal (Refereed)
    Abstract [en]

    Todays embedded systems are exposed to variations in resource usage due to complex software applications, hardware platforms, and impact of the runtime environments. When these variations are large and efficiency is required, on-line resource managers may be deployed on the system to help it control its resource usage. An often neglected problem is whether these resource managers are stable, meaning that the resource usage is controlled under all possible scenarios. In distributed systems, this problem is particularly hard because applications distributed overmany resources generate complex dependencies between their resources. In this article, we develop a mathematical model of the system, and derive conditions that, if satisfied, guarantee stability.

  • 205.
    Rafiliu, Sergiu
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Stability Conditions of On-line Resource Managers for Systems with Execution Time Variations2011In: 23rd Euromicro conference on Real-Time Systems (ECRTS11), Porto, Portugal, July 6-8, 2011., IEEE, 2011Conference paper (Refereed)
    Abstract [en]

    Today's embedded systems are exposed to variations in load demand due to complex software applications, hardware platforms, and impact of the run-time environments. When these variations are large, and efficiency is required, on-line resource managers may be deployed on the system to help it control its resource usage. An often neglected problem is whether these resource managers are stable, meaning that the resource usage is controlled under all possible scenarios. In this paper we develop mathematical models for the real-time embedded system and we derive conditions which, if satisfied, lead to stable systems. For the developed system models, we also determine bounds on the worst case response times of tasks.

  • 206.
    Rafiliu, Sergiu
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Stability of adaptive feedback-based resource managers for systems with execution time variations2013In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, ISSN 0922-6443, Vol. 49, no 3, 367-400 p.Article in journal (Refereed)
    Abstract [en]

    Today’s embedded systems are exposed to variations in load demand due to complex software applications, dynamic hardware platforms, and the impact of the run-time environment. When these variations are large, and efficiency is required, adaptive on-line resource managers may be deployed on the system to control its resource usage. An often neglected problem is whether these resource managers are stable, meaning that the resource usage is controlled under all possible scenarios. In this paper we develop mathematical models for real-time embedded systems and we derive conditions which, if satisfied, lead to stable systems. For the developed system models, we also determine bounds on the worst case response times of tasks. We also give an intuition of what stability means in a real-time context and we show how it can be applied for several resource managers. We also discuss how our results can be extended in various ways.

  • 207.
    Rosén, Jakob
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Andrei, Alexandru
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip2007In: 28th IEEE Real-Time Systems Symposium RTSS07,2007, Tucson, Arizona, USA: IEEE Computer Society Press , 2007, 49- p.Conference paper (Refereed)
    Abstract [en]

    In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. This has a huge impact on worst-case execution time (WCET) analysis and, in general, on the predictability of real-time applications implemented on such systems. As opposed to the WCET analysis performed for a single processor system, where the cache miss penalty is considered constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks' WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this paper we present an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures. The emphasis of this paper is on the bus scheduling policy and its optimization, which is of huge importance for the performance of such a predictable multiprocessor application.

  • 208.
    Rosén, Jakob
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Andrei, Alexandru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Predictable Multiprocessor Systems2010In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper (Other academic)
  • 209.
    Rosén, Jakob
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Andrei, Alexandru
    Ericsson, Linköping, Sweden.
    Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip2011In: 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011., 2011Conference paper (Refereed)
    Abstract [en]

    Worst-case execution time analysis is the fundament of real-time system design, and is therefore an area which has been subject to great scientific interest for a long time. However, traditional worst-case execution time analysis techniques assume that the underlying hardware is a monoprocessor system, and this class of hardware platforms is getting less suitable for modern embedded applications, which demand more and more in terms of computational power. For multiprocessor systems, traditional worst-case analysis tools do not produce correct results and can consequently not be used. To solve this problem, we have previously proposed a technique for achieving predictability on multiprocessor systems-on-chip using a shared TDMA bus. One of the main benefits with our approach is that existing, traditional worstcase execution time analysis techniques can, after some small modifications, be applied. In this paper, we describe the nature of these modifications and how to handle different types of multiprocessor architectures.

  • 210.
    Rosén, Jakob
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Neikter, Carl-Fredrik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Burgio, Paolo
    University of Bologna, Italy.
    Benini, Luca
    University of Bologna, Italy.
    Bus Access Design for Combined Worst and Average Case Execution Time Optimization of Predictable Real-Time Applications on Multiprocessor Systems-on-Chip2011In: 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'11), Chicago, IL, USA, April 11-14, 2011., 2011Conference paper (Refereed)
    Abstract [en]

    Optimization techniques for improving the average-case execution time of an application, for which predictability with respect to time is not required, have been investigated for a long time in many different contexts. However, this has traditionally been done without paying attention to the worst-case execution time. For predictable real-time applications, on the other hand, the focus has been solely on worst-case execution time optimization, ignoring how this affects the execution time in the average case. In this paper, we show that having a good average-case delay can be important also for real-time applications for which predictability is required. Furthermore, for real-time applications running on multiprocessor systems-on-chip, we present a technique for optimizing the average case and the worst case simultaneously, allowing for a good average-case execution time while still keeping the worst case as small as possible.

  • 211.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cervin, Anton
    Dept. of Automatic Control, Lund University, Sweden.
    Control-Quality Optimization for Distributed Embedded Systems with Adaptive Fault Tolerance2012In: ECRTS 2012, IEEE, 2012Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a design framework for distributed embedded control systems that ensures reliable execution and high quality of control even if some computation nodes fail. When a node fails, the configuration of the underlying distributed system changes and the system must adapt to this new situation by activating tasks at operational nodes. The task mapping as well as schedules and control laws that are customized for the new configuration influence the control quality and must, therefore, be optimized. The number of possible configurations due to faults is exponential in the number of nodes in the system. This design-space complexity leads to unaffordable design time and large memory requirements to store information related to mappings, schedules, and controllers. We demonstrate that it is sufficient to synthesize solutions for a small number of base and minimal configurations to achieve fault tolerance with an inherent minimum level of control quality. We also propose an algorithm to further improve control quality with a priority-based search of the set of configurations and trade-offs between task migration and replication.

  • 212.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cervin, A.
    Department of Automatic Control, Lund University, Sweden.
    Ion Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Integrated scheduling and synthesis of control applications on distributed embedded systems2009In: Proceedings -Design, Automation and Test in Europe, DATE, 2009, 57-62 p.Conference paper (Refereed)
    Abstract [en]

    Many embedded control systems comprise several control loops that are closed over a network of computation nodes. In such systems, complex timing behavior and communication lead to delay and jitter, which both degrade the performance of each control loop and must be considered during the controller synthesis. Also, the control performance should be taken into account during system scheduling. The contribution of this paper is a control-scheduling co-design method that integrates controller design with both static and priority-based scheduling of the tasks and messages, and in which the overall control performance is optimized.

  • 213.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cervin, Anton
    Dept. of Automatic Control, Lund University, Sweden.
    Design Optimization and Synthesis of FlexRay Parameters for Embedded Control Applications2011In: 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011., IEEE, 2011Conference paper (Refereed)
    Abstract [en]

    FlexRay is a popular communication protocol in modern automotive systems with several computation nodes and communication units. The complex temporal behavior of such systems depends highly on the FlexRay configuration and influences the performance of running control applications. In our previous work, we presented a design framework for integrated scheduling and design of embedded control applications, where control quality is the optimization objective. This paper presents our extension to the design framework to handle FlexRay-based embedded control systems. Our contribution is a method for the decision of FlexRay parameters and optimization of control quality.

  • 214.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Cervin, Anton
    Dept. of Automatic Control Lund University, Lund.
    Quality-Driven Synthesis of Embedded Multi-Mode Control Systems2009In: DAC '09 Proceedings of the 46th Annual Design Automation Conference: , IEEE Computer Society, 2009, 864-869 p.Conference paper (Refereed)
    Abstract [en]

    At runtime, an embedded control system can switch between alternative functional modes. In each mode, the system operates by using a schedule and controllers that exploit the available computation and communication resources to optimize the control performance in the running mode. The number of modes is usually exponential in the number of control loops, which means that all controllers and schedules cannot be produced in affordable design-time and stored in memory. This paper addresses synthesis of multi-mode embedded control systems. Our contribution is a method that trades control quality with optimization time, and that efficiently selects the schedules and controllers to be synthesized and stored in memory.

  • 215.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Tabuada, Paulo
    Cervin, Anton
    Dynamic Scheduling and Control-Quality Optimization of Self-Triggered Control Applications2010In: 31st IEEE Real-Time Systems Symposium (RTSS10), San Diego, CA, USA, November 30-December 3, 2010., IEEE , 2010Conference paper (Refereed)
    Abstract [en]

    Time-triggered periodic control implementations are over provisioned for many execution scenarios in which the states of the controlled plants are close to equilibrium. To address this inefficient use of computation resources, researchers have proposed self-triggered control approaches in which the control task computes its execution deadline at runtime based on the state and dynamical properties of the controlled plant. The potential advantages of this control approach cannot, however, be achieved without adequate online resource-management policies. This paper addresses scheduling of multiple self-triggered control tasks that execute on a uniprocessor platform, where the optimization objective is to find tradeoffs between the control performance and CPU usage of all control tasks. Our experimental results show that efficiency in terms of control performance and reduced CPU usage can be achieved with the heuristic proposed in this paper.

  • 216.
    Samii, Soheil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Rafiliu, Sergiu Aurel
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems2008In: Design, Automation, and Test in Europe DATE 2008,2008, Munich, Germany: IEEE Computer Society Press , 2008, 556- p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a simulation-based methodology for worst-case response time estimation of distributed real-time systems. Schedulability analysis produces pessimistic upper bounds on process response times. Consequently, such an analysis can lead to overdesigned systems resulting in unnecessarily increased costs. Simulations, if well conducted, can lead to tight lower bounds on worst-case response times, which can be an essential input at design time. Moreover, such a simulation methodology is very important in situations when the running application or the underlying platform is such that no formal timing analysis is available. Another important application of the proposed simulation environment is the validation of formal analysis approaches, by estimating their degree of pessimism. We have performed such an estimation of pessimism for two response-time analysis approaches for distributed embedded systems based on two of the most important automotive communication protocols: CAN and FlexRay.

  • 217.
    Samii, Soheil
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Yin, Yanfei
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ion Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Zhang, Yuanping
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Immune Genetic Algorithms for Optimization of Task Priorities and FlexRay Frame Identifiers2009In: Intl. Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Beijing, China, August 24-26, 2009., IEEE COMPUTER SOC , 2009, 486-493 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay is an automotive communication protocol that combines the comprehensive time-triggered paradigm with an adaptive phase that is more suitable for event-based communication. We study optimization of average response times by assigning priorities and frame identifiers to tasks and messages. Our optimization approach is based on immune genetic algorithms, where in addition to the crossover and mutation operators, we use a vaccination operator that results in considerable improvements in optimization time and quality.

  • 218.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities2003In: Design Automation and Test in Europe DATE 2003 Conference,2003, Munich, Germany: IEEE Computer Society Press , 2003, 960- p.Conference paper (Refereed)
    Abstract [en]

    Multi-mode systems are characterised by a set of interacting operational modes to support different functionalities and standards. In this paper, we present a co-design methodology for multi-mode embedded systems that produces energy-efficient implementations. Based on the key observation that operational modes are executed with different probabilities, i.e., the system spends uneven amounts of time in the different modes, we develop a novel codesign technique that exploits this property to significantly reduce energy dissipation. We conduct several experi-ments, including a smart phone real-life example, that demonstrate the effectiveness of our approach. Reductions in power consumption of up to 64% are reported.

  • 219.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems2002In: Design Automation and Test in Europe Conference DATE 2002,2002, Paris, France: IEEE Computer Society Press , 2002, 514- p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we present an efficient two-step iterative synthesis approach for distributed embedded systems containing dynamic voltage scalable processing elements (DVS-PEs), based on genetic algorithms. The approach partitions, schedules, and voltage scales multi-rate specifications given as task graphs with multiple deadlines. A distinguishing feature of the proposed synthesis is the utilisation of a generalised DVS method. In contrast to previous techniques, which simply exploit available slack time, this generalised technique additionally considers the PE power profile during a refined voltage selection to further increase the energy savings. Extensive experiments are conducted to demonstrate the efficiency of the proposed approach. We report up to 43.2% higher energy reductions compared to previous DVS scheduling approaches based on constructive techniques and total energy savings of up to 82.9% for mapping and scheduling optimised DVS systems.

  • 220.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Iterative Schedule Optimisation for Voltage scalable Distributed Embedded Systems2004In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 3, no 1, 182-217 p.Article in journal (Refereed)
    Abstract [en]

    We present an iterative schedule optimisation for multi-rate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs).To achieve a high degree of energy reduction, we formulate a generalised DVS problem, taking into account the power variations among the executing tasks. An efficient heuristic is presented that identifies optimised supply voltages by not only "simply" exploiting slack time, but under the additional consideration of the power profiles. Thereby, this algorithm minimises the energy dissipation of heterogeneous architectures, including power managed processing elements, effectively. Further, we address the simultaneous schedule optimisation towards timing behaviour and DVS utilisation by integrating the proposed DVS heuristic into a genetic list scheduling approach. We investigate and analyse the possible energy reduction at both steps of the co-synthesis (voltage scaling and scheduling), including the power variations effects. Extensive experiments indicate that the presented work produces solutions with high quality.

  • 221.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Synthesizing Energy-Efficient Embedded Systems with LOPOCOS2002In: Design automation for embedded systems, ISSN 0929-5585, Vol. 6, no 4, 401-424 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that includedynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimization steps during design space exploration for DVS enable architectures. The optimization steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimization for scheduling and communication mapping based on genetic algorithm, optimizes simultaneously execution order and communication mapping towards the utilization of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimization steps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm.

  • 222.
    Schmitz, Marcus
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    System-Level Design Techniques for Energy-Efficient Embedded Systems2004Book (Other academic)
    Abstract [en]

    By shrinking feature sizes, deep-submicron technology is enabling the design of systems with increased complexity on a single chip, but it is also introducing a productivity design gap. Additionally, system designers have to cope with an ever-increasing application complexity and shrinking time-to-market windows. Design re-use and system-level co-synthesis are two approaches that are being employed to bridge the design gap and to aid system designers. Power consumption has become one of the main barriers in embedded computing systems design and therefore, methodologies and techniques that provide power-aware hardware/software co-design are necessary. System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the development and validation of co-synthesis techniques that allow an effective design of embedded systems with low energy dissipation. The book provides an overview of a system-level co-design flow, illustrating through examples how system performance is influenced at various steps of the flow including allocation, mapping, and scheduling. The book places special emphasis upon system-level co-synthesis techniques for architectures that contain voltage scalable processors, which can dynamically trade off between computational performance and power consumption. Throughout the book, the introduced co-synthesis techniques, which target both single-mode systems and emerging multi-mode applications, are applied to numerous benchmarks and real-life examples including a realistic smart phone. System-Level Design Techniques for Energy-Efficient Embedded Systems will be of interest to advanced undergraduates, graduate students, and designers, whom are interested in energy-efficient embedded systems design.

  • 223. Schmitz, M.T.
    et al.
    Al-Hashimi, B.M.
    Sch. of Electron. and Comp. Science, University of Southampton, Southampton SO17 1BJ, United Kingdom.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities2005In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 24, no 2, 153-169 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a novel co-design methodology for the synthesis of energy-efficient embedded systems. In particular, we concentrate on distributed embedded systems that accommodate several different applications within a single device, i.e., multimode embedded systems. Based on the key observation that operational modes are executed with different probabilities, that is, the system spends uneven amounts of time in the different modes, we develop a new co-design technique that exploits this property to significantly reduce energy dissipation. Energy and cost savings are achieved through a suitable synthesis process that yields better hardware-resource-sharing opportunities. We conduct several experiments, including a realistic smart phone example, that demonstrate the effectiveness of our approach. Reductions in power consumption of up to 64% are reported.

  • 224.
    Schneider, Reinhard
    et al.
    Technical University of Munich, Germany.
    Goswami, Dip
    Technical University of Munich, Germany.
    Chakraborty, Samarjit
    Technical University of Munich, Germany.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    On the Quantification of Sustainability and Extensibility of FlexRay Schedules2011In: Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, New York, USA: ACM , 2011, 375-380 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay has emerged as the de-facto next generation in-vehicle communication protocol. Messages are scheduled incrementally on FlexRay according to the automotive design paradigm where new applications are added iteratively. On this account, the schedules must be (i) sustainable, i.e., when messages are added in later iterations, they must preserve deadline guarantees of existing messages and (ii) extensible, i.e., they must accommodate future messages without changes to existing schedules. Unfortunately, traditionally used metrics of sustainability and extensibility for timing and schedulability analysis are generic and can not be trivially adapted to FlexRay schedules. This is because of platform-specific properties of FlexRay like being a hybrid paradigm, where both time-triggered and event-triggered segments are used for communication. In this paper, we first introduce new notions of sustainability and extensibility for FlexRay that capture protocol-specific properties and then present novel metrics to quantify sustainable and extensible schedules. We demonstrate the applicability of our results with industrial-size case studies and show that our proposed metrics may be visually represented allowing easy interpretation by system designers in the automotive industry.

  • 225.
    Schneider, Reinhard
    et al.
    Technical University of Munich, Germany .
    Goswami, Dip
    Eindhoven University of Technology, Netherlands .
    Chakraborty, Samarjit
    Technical University of Munich, Germany .
    Bordoloi, Unmesh
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Quantifying Notions of Extensibility in FlexRay Schedule Synthesis2014In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, Vol. 19, no 4, 32- p.Article in journal (Refereed)
    Abstract [en]

    FlexRay has now become a well-established in-vehicle communication bus at most original equipment manufacturers (OEMs) such as BMW, Audi, and GM. Given the increasing cost of verification and the high degree of crosslinking between components in automotive architectures, an incremental design process is commonly followed. In order to incorporate FlexRay-based designs in such a process, the resulting schedules must be extensible, that is: (i) when messages are added in later iterations, they must preserve deadline guarantees of already scheduled messages, and (ii) they must accommodate as many new messages as possible without changes to existing schedules. Apart from extensible scheduling having not received much attention so far, traditional metrics used for quantifying them cannot be trivially adapted to FlexRay schedules. This is because they do not exploit specific properties of the FlexRay protocol. In this article we, for the first time, introduce new notions of extensibility for FlexRay that capture all the protocol-specific properties. In particular, we focus on the dynamic segment of FlexRay and we present a number of metrics to quantify extensible schedules. Based on the introduced metrics, we propose strategies to synthesize extensible schedules and compare the results of different scheduling algorithms. We demonstrate the applicability of the results with industrial-size case studies and also show that the proposed metrics may also be visually represented, thereby allowing for easy interpretation.

  • 226.
    Suri, Bharath
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    A Scalable GPU-Based Approach to Accelerate the Multiple-Choice Knapsack Problem2012In: Design Automation and Test in Europe (DATE12) (short paper), Dresden, Germany, March 12-16, 2012., IEEE , 2012, 1126-1129 p.Conference paper (Refereed)
    Abstract [en]

    Variants of the 0-1 knapsack problem manifest themselves at the core of several system-level optimization problems. The running times of such system-level optimization techniques are adversely affected because the knapsack problem is NP-hard. In this paper, we propose a new GPU-based approach to accelerate the multiple-choice knapsack problem, which is a general version of the 0-1 knapsack problem. Apart from exploiting the parallelism offered by the GPUs, we also employ a variety of GPU-specific optimizations to further accelerate the running times of the knapsack problem. Moreover, our technique is scalable in the sense that even when running large instances of the multiple-choice knapsack problems, we can efficiently utilize the GPU compute resources and memory bandwidth to achieve significant speedups.

  • 227.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Correlation-Aware Probabilistic Timing Analysis for the Dynamic Segment of FlexRay2016In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 15, no 3, 54:1-54:31 p.Article in journal (Refereed)
    Abstract [en]

    We propose an analytical framework for probabilistic timing analysis of the event-triggered Dynamic segment of the FlexRay communication protocol. Specifically, our framework computes the Deadline Miss Ratio of each message. The core problem is formulated as a Mixed Integer Linear Program (MILP). Given the intractability of the problem, we also propose several techniques that help to mitigate the running times of our tool. This includes the re-engineering of the problem to run it on GPUs as well as reformulating the MILP itself.

    Most importantly, we also show how our framework can handle correlations between the queuing events of messages. This is challenging because one cannot apply the convolution operator in the same way as in the case of independent queuing events.

  • 228.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Bordoloi, Unmesh D
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Probabilistic Response Time and Joint Analysis of Periodic Tasks2015In: PROCEEDINGS OF THE 2015 27TH EUROMICRO CONFERENCE ON REAL-TIME SYSTEMS (ECRTS 2015), IEEE Communications Society, 2015, 235-246 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we address the problem of computing the probability response time distribution of periodic tasks scheduled on a uniprocessor systems. Our framework assumes an arbitrary non-idling preemptive scheduling policy that may be either a fixed-priority scheduler (such as Rate Monotonic - RM) or a dynamic-priority scheduler (such as Earliest Deadline First - EDF). At the same time, our framework can handle arbitrary execution time distributions arbitrary deadlines providing numerically accurate results. We also show how the framework can be extended to compute the correlation coefficients between the response times of different jobs by performing the joint analysis.

  • 229.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Reliability-Aware Frame Packing for the Static Segment of FlexRay2011In: EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software                         , Association for Computing Machinery (ACM), 2011, 175-184 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay is gaining wide acceptance as the next generation bus protocol for automotive networks. This has led to tremendous research interest in techniques for scheduling signals, which are generated by real-time applications, on the FlexRay bus. Signals are first packed together into frames at the application-level and the frames are then transmitted over the bus. To ensure reliability of frames in the presence of faults, frames must be retransmitted over the bus but this comes at the cost of higher bandwidth utilization. To address this issue, in this paper, we propose a novel frame packing method for FlexRay bus. Our method computes the required number of retransmissions of frames that ensures the specified reliability goal. The proposed frame packing method also ensures that none of the signals violates its deadline and that the desired reliability goal for guaranteeing fault-tolerance is met at the minimum bandwidth cost. Extensive experiments on synthetic as well as a industrial case study demonstrate the benefits of our method.

  • 230.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling for Fault-Tolerant Communication on the Static Segment of FlexRay2010In: 31st IEEE Real-Time Systems Symposium (RTSS10), San Diego, CA, USA, November 30-December 3, 2010., IEEE Computer Society , 2010, 385-394 p.Conference paper (Refereed)
    Abstract [en]

    FlexRay has been widely accepted as the next generation bus protocol for automotive networks. This has led to tremendous research interest in techniques for scheduling messages on the FlexRay bus, in order to meet the hard realtime deadlines of the automotive applications. However, these techniques do not generate reliable schedules in the sense that they do not provide any performance guarantees in the presence of faults. In this work, we will present a framework for generating fault-tolerant message schedules on the time-triggered (static) segment of the FlexRay bus. We provide formal guarantees that the generated fault-tolerant schedules achieve the reliability goal even in the presence of transient and intermittent faults. Moreover, our technique minimizes the required number of retransmissions of the messages in order to achieve such fault tolerant schedules, thereby, optimizing the bandwidth utilization. Towards this, we formulate the optimization problem in Constraint Logic Programming (CLP), which returns optimal results. However, this procedure is computationally intensive and hence, we also propose an efficient heuristic. The heuristic guarantees the reliability of the constructed schedules but might be sub-optimal with respect to bandwidth utilization. Extensive experiments run on synthetic test cases and real-life case studies illustrate that the heuristic performs extremely well. The experiments also establish that our heuristic scales significantly better than the CLP formulation.

  • 231.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Probabilistic Timing Analysis for the Dynamic Segment of FlexRay2013In: 25th Euromicro Conference on Real-Time Systems (ECRTS), IEEE , 2013, 135-144 p.Conference paper (Refereed)
    Abstract [en]

    We propose an analytical framework for probabilistic timing analysis of the event-triggered Dynamic segment of the FlexRay communication protocol. Specifically, our framework computes the Deadline Miss Ratios of each message. The core problem is formulated as a Mixed Integer Linear Program (MILP). Given the intractability of the problem, we also propose several techniques that help to mitigate the running times of our tool. This includes the re-engineering of the problem to run it on GPUs as well as re-formulating the MILP itself.

  • 232.
    Tanasa, Bogdan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Kosuch, Stefanie
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Schedulability Analysis for the Dynamic Segment of FlexRay: A Generalization to Slot Multiplexing2012Conference paper (Refereed)
    Abstract [en]

    FlexRay, developed by a consortium of over hundred automotive companies, is a real-time communication protocol for automotive networks. In this paper, we propose a new approach for timing analysis of the event-triggered component of FlexRay, known as the dynamic segment. Our technique accounts for the fact that the FlexRay standard allows slot multiplexing, i.e., the same priority can be assigned to more than one message. Existing techniques have either ignored slot multiplexing in their analysis or made simplifying assumptions that severely limit achieving high bandwidth utilization. Moreover, we show that our technique returns less pessimistic results compared to previously known techniques even in the case where slot multiplexing is ignored.

  • 233.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bao, Min
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Steady-State Dynamic Temperature Analysis and Reliability Optimization for Embedded Multiprocessor Systems2012In: 49th ACM/EDAC/IEEE Design Automation Conference (DAC), 3-7 June 2012, San Francisco, ACM/ IEEE , 2012, 197-204 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we propose an analytical technique for the steady-state dynamic temperature analysis (SSDTA) of multiprocessor systems with periodic applications. The approach is accurate and, moreover, fast, such that it can be included inside an optimization loop for embedded system design. Using the proposed solution, a temperature-aware reliability optimization, based on the thermal cycling failure mechanism, is presented. The experimental results con firm the quality and speed of our SSDTA technique, compared to the state of the art. They also show that the lifetime of an embedded system can significantly be improved, without sacrificing its energy efficiency, by taking into consideration, during the design stage, the steady-state dynamic temperature profile of the system.

  • 234.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Probabilistic Analysis of Electronic Systems via Adaptive Hierarchical Interpolation2017In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151Article in journal (Refereed)
    Abstract [en]

    We present a framework for system-level analysis of electronic systems whose runtime behaviors depend on uncertain parameters. The proposed approach thrives on hierarchical interpolation guided by an advanced adaptation strategy, which makes the framework general and suitable for studying various metrics that are of interest to the designer. Examples of such metrics include the end-to-end delay, total energy consumption, and maximum temperature of the system under consideration. The framework delivers a light generative representation that allows for a straightforward, computationally efficient calculation of the probability distribution and accompanying statistics of the metric at hand. Our technique is illustrated by considering a number of uncertainty-quantification problems and comparing the corresponding results with exhaustive simulations.

  • 235.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Probabilistic Analysis of Power and Temperature Under Process Variation for Electronic System Design2014In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 33, no 6, 931-944 p.Article in journal (Refereed)
    Abstract [en]

    Electronic system design based on deterministic techniques for power-temperature analysis is, in the context of current and future technologies, both unreliable and inefficient since the presence of uncertainty, in particular, due to process variation, is disregarded. In this paper, we propose a flexible probabilistic framework targeted at the quantification of the transient power and temperature variations of an electronic system. The framework is capable of modeling diverse probability laws of the underlying uncertain parameters and arbitrary dependencies of the system on such parameters. For the considered system, under a given workload, our technique delivers analytical representations of the corresponding stochastic power and temperature profiles. These representations allow for a computationally efficient estimation of the probability distributions and accompanying quantities of the power and temperature characteristics of the system. The approximation accuracy and computational time of our approach are assessed by a range of comparisons with Monte Carlo simulations, which confirm the efficiency of the proposed technique.

  • 236.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Temperature-Centric Reliability Analysis and Optimization of Electronic Systems under Process Variation2015In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 23, no 11, 2417-2430 p.Article in journal (Refereed)
    Abstract [en]

    Electronic system designs that ignore process variationare unreliable and inefficient. In this paper, we propose asystem-level framework for the analysis of temperature-inducedfailures that considers the uncertainty due to process variation.As an intermediate step, we also develop a probabilistic techniquefor dynamic steady-state temperature analysis. Given an electronicsystem under a certain workload, our framework deliversthe corresponding survival function, founded on the basis ofwell-established reliability models, with a closed-form stochasticparameterization in terms of the quantities that are uncertain atthe design stage. The proposed solution is exemplified consideringsystems with periodic workloads that suffer from the thermalcyclingfatigue. The analysis of this fatigue is a challengingproblem as it requires the availability of detailed temperatureprofiles, which are uncertain due to the variability of processparameters. To demonstrate the computational efficiency of ourframework, we undertake a design-space exploration procedureto minimize the expected energy consumption under a set oftiming, thermal, and reliability constraints.

  • 237.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Marculescu, Diana
    Department of Electrical and Computer Engineering, Carnegie Mellon University, USA.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Fast Synthesis of Power and Temperature Profiles for the Development of Data-Driven Resource Managers2017Report (Other academic)
    Abstract [en]

    The goal of this work is to facilitate the development of proactive power- and temperature-aware resource managers that leverage machine learning in order to attain their objectives. In this context, the availability of sufficiently large amounts of relevant data, which are essential for learning and, therefore, exploration of research ideas, is elusive. In order to fulfill the need, we present a toolchain for fast generation of realistic power and temperature profiles of computer systems. The toolchain provides profuse representative data to learn from during development stages. The overreaching objective is to help research by making it tractable to experiment with the highly promising but data-demanding state-of-the-art techniques for prediction.

  • 238.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Marculescu, Diana
    Department of Electrical and Computer Engineering, Carnegie Mellon University, USA.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Fine-Grained Long-Range Prediction of Resource Usage in Computer Clusters2017Report (Other academic)
    Abstract [en]

    In order to facilitate the development of intelligent resource managers of computer clusters, we investigate the utility of the state-of-the-art neural networks for the purpose of fine-grained long-range prediction of the resource usage in one such cluster. We consider a large data set of real-life traces and describe in detail our workflow, starting from making the data accessible for learning and finishing by predicting the resource usage of individual tasks multiple steps ahead. The experimental results indicate that such fine-grained traces as the ones considered possess a certain structure, and that this structure can be extracted by advanced machine-learning techniques and subsequently utilized for making informed predictions.

  • 239.
    Ukhov, Ivan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Villani, Mattias
    Linköping University, Department of Computer and Information Science, Statistics. Linköping University, Faculty of Arts and Sciences.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Statistical Analysis of Process Variation Based on Indirect Measurements for Electronic System Design2014In: 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), New York: IEEE conference proceedings, 2014, 436-442 p.Conference paper (Refereed)
    Abstract [en]

    We present a framework for the analysis of process variation across semiconductor wafers. The framework is capable of quantifying the primary parameters affected by process variation, e.g., the effective channel length, which is in contrast with the former techniques wherein only secondary parameters were considered, e.g., the leakage current. Instead of taking direct measurements of the quantity of interest, we employ Bayesian inference to draw conclusions based on indirect observations, e.g., on temperature. The proposed approach has low costs since no deployment of expensive test structures might be needed or only a small subset of the test equipments already deployed for other purposes might need to be activated. The experimental results present an assessment of our framework for a wide range of configurations.

  • 240.
    Varea, Mauricio
    et al.
    Dept. Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Cortes, Luis-Alejandro
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Symbolic Model Checking of Dual Transition Petri Nets2002In: 10th International Symposium on HardwareSoftware Codesign CODES 2002,2002, Estes Park, Colorado, USA: IEEE Computer Society Press , 2002, 43- p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the formal verification of the recently introduced Dual Transition Petri Net (DTPN) models, using model checking techniques. The methodology presented addresses the symbolic model checking of embedded systems behavioural properties, expressed in either computation tree logics (CTL) or linear temporal logics (LTL). The embedded system specification is given in terms of DTPN models, where elements of the model are captured in a four-module library which implements the behaviour of the model. Key issues in the development of the methodology are the heterogeneity and the nondeterministic nature of the model. This is handled by introducing some modifications in both structure and behaviour of the model, thus reducing the points of nondeterminism. Several features of the methodology are discussed and two examples are given in order to show the validity of the model.

  • 241.
    Varea, Mauricio
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al-Hashimi, Bashir
    Dept. of Electronics and Computer Science University of Southampton.
    Cortes, Luis-Alejandro
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Dual Flow Nets: Modelling the Control/Data-Flow Relation in Embedded Systems2006In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 5, no 1, 54-81 p.Article in journal (Refereed)
    Abstract [en]

    This paper addresses the interrelation between control and data flow in embedded system models through a new design representation, called Dual Flow Net (DFN). A modeling formalism with a very close-fitting control and data flow is achieved by this representation, as a consequence of enhancing its underlying Petri net structure. The work presented in this paper does not only tackle the modeling side in embedded systems design, but also the validation of embedded system models through formal methods. Various introductory examples illustrate the applicability of the DFN principles, whereas the capability of the model to with complex designs is demonstrated through the design and verification of a real-life Ethernet coprocessor.

  • 242.
    Wu, Dong
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems2003In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 150, no 5, 302-312 p.Article in journal (Refereed)
    Abstract [en]

    A dynamic voltage scaling (DVS) technique for embedded systems expressed as conditional task graphs (CTGs) is described. The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also the effect of combining a genetic algorithm based mapping with the DVS technique is examined and it is shown that further energy reduction can be achieved. The techniques are tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with an energy saving of up to 24%. Furthermore, it is shown that savings of up to 51% are achieved by considering during the mapping optimisation. Finally, the impact of communications and communication link selection on the scheduling and mapping technique is investigated and results are reported.

  • 243.
    Wu, Dong
    et al.
    Dept. of Electronics and Computer Science University of Southampton.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems2003In: Design Automation and Test in Europe DATE 2003 Conference,2003, Munich, Germany: IEEE Computer Society Press , 2003, 90- p.Conference paper (Refereed)
    Abstract [en]

    This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.

  • 244.
    Wu, Dong
    et al.
    School of Electronics and Computer Science University of Southampton.
    Al-Hashimi, Bashir M.
    School of Electronics and Computer Science University of Southampton.
    Schmitz, Marcus T.
    School of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction2005In: 8th Euromicro Conference on Digital System Design DSD2005,2005, Porto, Portugal: IEEE Computer Society Press , 2005, 34- p.Conference paper (Refereed)
    Abstract [en]

    Recent research has shown that the combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) yields high energy reductions in embedded systems. Nevertheless, the implementation of DVS and ABB requires a significant system cost, making it less attractive for many small systems. In this paper we demonstrate that it is possible to reduce this system cost and to achieve comparable energy saving to that obtained using combined DVS and ABB scheme through a co-synthesis methodology which is aware of the tasks' power-composition profile (the ratio of the dynamic power to the leakage power). In particular, the presented methodology performs a power management selection at the architectural level, i.e., it decides upon which processing elements to be equipped with which power management scheme (DVS, ABB, or combined DVS and ABB) - with the aim to achieve high energy savings at a reduced implementation cost. The proposed technique maps, schedules, and voltage scales applications specified as task graphs with timing constraints. Detailed experiments including a real-life benchmark are conducted to demonstrate the effectiveness of the proposed methodology.

  • 245.
    Zeng, Haibo
    et al.
    Department of Electrical and Computer Engineering, Virginia Tech.
    Joshi, Prachi
    Department of Electrical and Computer Engineering, Virginia Tech.
    Thiele, Daniel
    Elektrobit Automotive GmbH.
    Diemer, Jonas
    Symtavision.
    Axer, Philip
    NXP Semiconductors.
    Ernst, Rolf
    Institut für Datentechnik und Kommunikationsnetze, Technische Universität Braunschweig.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering.
    Networked Real-Time Embedded Systems2017In: Handbook of Hardware/Software Codesign, Springer Netherlands, 2017, 1-40 p.Chapter in book (Refereed)
    Abstract [en]

    This chapter gives an overview on various real-time communication protocols, from the Controller Area Network (CAN) that was standardized over twenty years ago but is still popular, to the FlexRay protocol that provides strong predictability and fault tolerance, to the more recent Ethernet-based networks. The design of these protocols including their messaging mechanisms was driven by diversified requirements on bandwidth, real-time predictability, reliability, cost, etc. The chapter provides three examples of real-time communication protocols: CAN as an example of event-triggered communication, FlexRay as a heterogeneous protocol supporting both time-triggered and event-triggered communications, and different incarnations of Ethernet that provide desired temporal guarantees.

  • 246.
    Zhang, Ying
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Rezine, Ahmed
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Automatic Test Program Generation for Out-of-Order Superscalar Processors2012In: 21st IEEE Asian Test Symposium (ATS12), Niigata, Japan, November 19-22, 2012., IEEE, 2012Conference paper (Refereed)
    Abstract [en]

    This paper presents a high-level automatic test instruction generation (HATIG) technical that allows, for the first time, to test the scheduling unit of an out-of-order super scalar processor. This technique leverages on existing bounded model checking tools in order to generate software-based self-testing programs from a global EFSM model of the processor under test. The experimental results have demonstrated the efficiency of the proposed technique.

  • 247.
    Zhiyuan, He
    et al.
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Rosinger, Paul
    University of Southampton.
    Al-Hashimi, Bashir
    University of Southampton.
    Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving2008In: Journal of electronic testing, ISSN 0923-8174, Vol. 24, no 1-3, 247-257 p.Article in journal (Refereed)
    Abstract [en]

    High temperature has become a major problem for system-on-chip testing. In order to reduce the test application time while keeping the temperatures of the cores under test within safe ranges, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test application time and, at the same time, prevent the temperatures of cores under test going beyond given limits. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling periods between test sequences so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, such that the cooling periods and the bandwidth of the test bus can be utilized for test data transportation, and hence the test application time can be reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use the constraint logic programming (CLP) to build the optimization model and find the optimal solution. As the optimization time of the CLP-based approach increases exponentially with the problem size, we also propose a heuristic which generates longer test schedules but requires substantially shorter optimization time. Experimental results have shown the efficiency of the proposed approach.

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