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  • 201.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Integrated Framework for the Design and Optimization of SOC Test Solutions2002In: Journal of electronic testing, ISSN 0923-8174, Vol. 18, no 4-5, 385-400 p.Article in journal (Refereed)
    Abstract [en]

    We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.

  • 202.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Integrated Framework for the Design and Optimization of SOC Test Solutions2002In: SOC (System-on-a-Chip) Testing for Plug and Play Test Automation. / [ed] Krishnendu Chakrabarty, Boston, USA: Kluwer Academic Publishers , 2002, 21-36 p.Chapter in book (Other academic)
    Abstract [en]

    We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.

  • 203.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Integrated System-on-Chip Test Framework2008In: Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE, Dordrecht, The Netherlands: Springer , 2008, 1, 439-454 p.Chapter in book (Other academic)
    Abstract [en]

    In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.

  • 204.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Integrated System-On-Chip Test Framework2001In: Design, Automation and Test in Europe DATE Conference,2001, Munich, Germany: IEEE Computer Society Press , 2001, 138-144 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.

  • 205.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process2006In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, Vol. 55, no 2, 227-239 p.Article in journal (Refereed)
    Abstract [en]

    Test application and test design, performed to ensure the production of fault-free chips, are becoming complicated and very expensive, especially in the case of SoCs (System-on-Chip), as the number of possible faults in a chip is increasing dramatically due to the technology development. It is therefore important to take test design into consideration as early as possible in the SoC design-flow in order to develop an efficient test solution. We propose a technique for modular core-based SoCs where test design is integrated in the early design exploration process. The technique can, in contrast to previous approaches, already be used in the core selection process to evaluate the impact on the system's final test solution imposed by different design decisions. The proposed technique considers the interdependent problems of core selection, test scheduling, TAM (test access mechanism) design, test set selection, and test resource floorplanning, and minimizes a weighted cost-function based on test time and TAM routing cost, while considering test conflicts and test power limitations. Concurrent scheduling of tests is used to minimize the test application time; however, concurrent test application leads to higher activity during the testing and, hence, higher power consumption. The power consumed during testing is, in general, higher than that during normal operation since it is desirable with hyperactivity in order to maximize the number of tested faults in a minimal time. A system under test can actually be damaged during testing and, therefore, power constraints must be considered. However, power consumption is complicated to model and, often, simplistic models that focus on the global system power limit only have been proposed and used. We therefore include a novel three-level power model: system, power-grid, and core. The advantage is that the system-level power budget is met and hot-spots can be avoided both at a specific core and at certain hot-spot areas in the chip. We have implemented and compared the proposed technique with a technique that assumes already fixed cores and tests, an estimation-based approach, and a computationally expensive pseudoexhaustive method. The results from the experiments show that, by exploring different design and test alternatives, the total test cost can be reduced, the pseudoexhaustive technique cannot produce results within reasonable computational time, and the estimation-based technique cannot produce solutions with high quality. The proposed technique produces results that are near the ones produced by the pseudoexhaustive technique at computational costs that are near the costs of the estimation-based technique, i.e., it produces high-quality solutions at low computational cost.

  • 206.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    System-on-Chip Test Bus Design and Test Scheduling2000In: International Test Synthesis Workshop,2000, 2000Conference paper (Refereed)
    Abstract [en]

    We propose a technique for test scheduling and test bus infrastructure design. In our approach, we consider constraints on the power consumption and on the design for test resources, while minimizing the test application time and the test bus length. The technique has a low computational cost which is important when it is used repeatedly in the design space exploration process. For the final design, we use Simulated annealing to optimize the solution. The proposed technique has been been implemented and experimental results show the efficiency of our approach.

  • 207.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    System-on-Chip Test Parallelization Under Power Constraints2001Other (Other (popular science, discussion, etc.))
    Abstract [en]

    This paper deals with test parallelization (scan-chain sub-division) which is used as a technique to reduce test application time for systems-on-chip. An approach for test parallelization taking into account test conflicts and test power limitations is described. The main features of the proposed approach are the combination of test parallelization with test scheduling as well as the development of an extremely fast algorithm which can be used repeatedly in the design space exploration process. The efficiency and usefulness of our approach have been demonstrated with an industrial design.

  • 208.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Infrastructure Design and Test Scheduling Optimization2000Other (Other (popular science, discussion, etc.))
    Abstract [en]

    We propose a technique for test scheduling and design of test bus infrastructure where test application time as well as test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. The proposed technique is implemented and experimental results show the efficiency of our approach.

  • 209.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Scheduling and Scan-Chain Division Under Power Constraint2001In: Tenth Asian Test Symposium ATS 2001,2001, Kyoto, Japan: IEEE Computer Society Press , 2001, 259- p.Conference paper (Refereed)
    Abstract [en]

    An integrated technique for test scheduling and scan-chain division under power constraints is proposed in this paper. We demonstrate that optimal test time can be achieved for systems tested by an arbitrary number of tests per core using scan-chain division and we define an algorithm for it. The design of wrappers to allow different lengths of scan-chains per core is also outlined. We investigate the practical limitations of such wrapper design and make a worst case analysis that motivates our integrated test scheduling and scan-chain division algorithm. The efficiency and usefulness of our approach have been demonstrated with an industrial design.

  • 210.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Carlsson, Gunnar
    CadLab Research Center Ericsson.
    The Design and Optimization of SOC Test Solutions2001In: ICCAD-2001,2001, San Jose, California: IEEE Computer Society Press , 2001, 523- p.Conference paper (Refereed)
    Abstract [en]

    We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.

  • 211.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Persson, Jon
    IDA Linköpings Universitet.
    An Architecture for Combined Test Data Compression and Abort-on-Fail Test2007In: Asia and South Pacific Design Automation Conference,2007, Yokohama: IEEE Computer Society Press , 2007, 726- p.Conference paper (Refereed)
    Abstract [en]

    The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (Multiple-Input Signature Register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X).

  • 212.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pouget, Julien
    LIRMM Montpellier 2 University, CNRS.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Abort-on-Fail Based Test Scheduling2005In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 21, no 6, 651-658 p.Article in journal (Refereed)
    Abstract [en]

    The long and increasing test application time for modular core-based system-on-chips is a major problem, and many approaches have been developed to deal with the problem. Different from previous approaches, where it is assumed that all tests will be performed until completion, we consider the cases where the test process is terminated as soon as a defect is detected. Such abort-on-fail testing is common practice in production test of chips. We define a model to compute the expected test time for a given test schedule in an abort-on-fail environment. We have implemented three scheduling techniques and the experimental results show a significant test time reduction (up to 90%) when making use of an efficient test scheduling technique that takes defect probabilities into account.

  • 213.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pouget, Julien
    ESLAB, IDA Linköpings Universitet.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Defect Probability-based System-On-Chip Test Scheduling2003In: 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems DDECS03,2003, 2003, 25-32 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we address the test scheduling problem for system-on-chip. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test set in order to schedule the test sets so that the expected total test time will be minimized. It supports different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). Several heuristic algorithms have been developed and experiments performed to demonstrate their efficiency.

  • 214.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pouget, Julien
    LIRMM Montpellier 2 University, CNRS.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Defect-Aware SOC Test Scheduling2004In: 2004 IEEE VLSI Test Symposium VTS04,2004, Napa Valley, USA: IEEE Computer Society Press , 2004, 359- p.Conference paper (Refereed)
    Abstract [en]

    In this paper we address the test scheduling problem for system-on-chip designs. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test in order to schedule the tests so that the expected total test time will be minimized. We investigate different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). We have also made experiments to illustrate the efficiency of taking defect probability into account during test scheduling.

  • 215.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pouget, Julien
    LIRMM Montpellier 2 University, CNRS.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Multiple Constraints Driven System-on-Chip Test Time Optimization2005In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 21, no 6, 599-611 p.Article in journal (Refereed)
    Abstract [en]

    The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC'02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.

  • 216.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pouget, Julien
    ESLAB, IDA Linköpings Universitet.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    System-on-Chip Test Scheduling based on Defect Probability2003Other (Other (popular science, discussion, etc.))
    Abstract [en]

    This paper addresses the test scheduling problem for system-on-chip. Different from previous approaches where it is assumed that all test sets will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test set in order to schedule the test sets so that the expected total test time will be minimized. It supports different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). Several heuristic algorithms have been developed and experiments performed to demonstrate their efficiency.

  • 217.
    Larsson, Erik
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ravikumar, C.P.
    Power-Aware System-Level DfT and Test Planning2009In: Power-Aware Testing and Test Strategies for Low Power Devices / [ed] Girard, Patrick; Nicolici, Nicola; Wen, Xiaoqing, Springer , 2009, 1Chapter in book (Other academic)
    Abstract [en]

    Ultra low-power devices are being developed for

    embedded applications in bio-medical electronics, wireless

    sensor networks, environment monitoring and protection,

    etc. The testing of these low-cost, low-power devices is a

    daunting task. Depending on the target application, there

    are stringent guidelines on the number of defective parts

    per million shipped devices. At the same time, since such

    devices are cost-sensitive, test cost is a major consideration.

    Since system-level power-management techniques are

    employed in these devices, test generation must be powermanagement-

    aware to avoid stressing the power

    distribution infrastructure in the test mode. Structural test

    techniques such as scan test, with or without compression,

    can result in excessive heat dissipation during testing and

    damage the package. False failures may result due to the

    electrical and thermal stressing of the device in the test

    mode of operation, leading to yield loss. This paper

    considers different aspects of testing low-power devices

    and some new techniques to address these problems.

  • 218.
    Larsson, Erik
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Vermeulen, Bart
    NXP Semiconductors, Netherlands.
    Goossens, Kees
    Eindhoven University of Technology, Netherlands.
    A Distributed Architecture to Check Global Properties for Post-Silicon Debug2010In: IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010., IEEE , 2010, 182-187 p.Conference paper (Refereed)
    Abstract [en]

    Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between intellectual property (IP) blocks, we demonstrate that these races can be detected and classified as timing violations or as FIFO protocol violations.

  • 219.
    Larsson, Erik
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Vermeulen, Bart
    NXP Semiconductors, Netherlands.
    Goossens, Kees
    Eindhoven University of Technology, Netherlands.
    Checking Pipelined Distributed and Global Properties at Post-silicon Debug2010In: DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10) , Anaheim, CA, USA, June 13-18, 2010., 2010Conference paper (Refereed)
    Abstract [en]

    Ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is difficult as it requires checking of global properties that are distributed on the chip. Different to our previous work where only one token was considered, we address in this paper pipelined tokens and we discuss the scalability of the debug architecture.

  • 220.
    Larsson, Erik
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Vermeulen, Bart
    NXP Semiconductors, Netherlands.
    Goossens, Kees
    Eindhoven University of Technology, Netherlands.
    Checking Pipelined Distributed Global Properties for Post-silicon Debug2010In: Workshop on RTL ATPG & DFT (WRTLT10), Shanghai, China, December 2010., 2010Conference paper (Refereed)
  • 221.
    Larsson, Erik
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Zadegan, Farrokh Ghani
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson, Linköping, Sweden.
    Test scheduling on IJTAG2010In: Nordic Test Forum (NTF 2010), Drammen, Norway., 2010Conference paper (Refereed)
  • 222.
    Lifa, Adrian Alin
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru lon
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Performance Optimization of Error Detection Based on Speculative Reconfiguration2011In: 48th Design Automation Conference (DAC 2011), San Diego, CA, USA, June 5-10, 2011., New York, USA: ACM , 2011, 369-374 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents an approach to minimize the average program execution time by optimizing the hardware/software implementation of error detection. We leverage the advantages of partial dynamic reconfiguration of FPGAs in order to speculatively place in hardware those error detection components that will provide the highest reduction of execution time. Our optimization algorithm uses frequency information from a counter-based execution profile of the program. Starting from a control flow graph representation, we build the interval structure and the control dependence graph, which we then use to guide our error detection optimization algorithm.

  • 223.
    Lifa, Adrian Alin
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Izosimov, Viacheslav
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Hardware/Software Optimization of Error Detection Implementation for Real-Time Embedded Systems2010In: Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP International Conference on, IEEE Operations Center , 2010, 41-50 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.

  • 224.
    Lindström, Birgitta
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Testability of Dynamic Real-Time Systems2009Doctoral thesis, monograph (Other academic)
    Abstract [en]

    This dissertation concerns testability of event-triggered real-time systems. Real-time systems are known to be hard to test because they are required to function correct both with respect to what the system does and when it does it. An event-triggered real-time system is directly controlled by the events that occur in the environment, as opposed to a time-triggered system, which behavior with respect to when the system does something is constrained, and therefore more predictable. The focus in this dissertation is the behavior in the time domain and it is shown how testability is affected by some factors when the system is tested for timeliness.

    This dissertation presents a survey of research that focuses on software testability and testability of real-time systems. The survey motivates both the view of testability taken in this dissertation and the metric that is chosen to measure testability in an experiment. We define a method to generate sets of traces from a model by using a meta algorithm on top of a model checker. Defining such a method is a necessary step to perform the experiment. However, the trace sets generated by this method can also be used by test strategies that are based on orderings, for example execution orders.

    An experimental study is presented in detail. The experiment investigates how testability of an event-triggered real-time system is affected by some constraining properties of the execution environment. The experiment investigates the effect on testability from three different constraints regarding preemptions, observations and process instances. All of these constraints were claimed in previous work to be significant factors for the level of testability. Our results support the claim for the first two of the constraints while the third constraint shows no impact on the level of testability.

    Finally, this dissertation discusses the effect on the event-triggered semantics when the constraints are applied on the execution environment. The result from this discussion is that the first two constraints do not change the semantics while the third one does. This result indicates that a constraint on the number of process instances might be less useful for some event-triggered real-time systems.

  • 225.
    Maghazeh, Arian
    et al.
    Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Bordoloi, Unmesh D.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    General Purpose Computing on Low-Power Embedded GPUs: Has It Come of Age?2013In: 13th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2013), Samos, Greece, July 15-18, 2013., IEEE Press, 2013Conference paper (Refereed)
    Abstract [en]

    In this paper we evaluate the promise held by low power GPUs for non-graphic workloads that arise in embedded systems. Towards this, we map and implement 5 benchmarks, that find utility in very different application domains, to an embedded GPU. Our results show that apart from accelerated performance, embedded GPUs are promising also because of their energy efficiency which is an important design goal for battery-driven mobile devices. We show that adopting the same optimization strategies as those used for programming high-end GPUs might lead to worse performance on embedded GPUs. This is due to restricted features of embedded GPUs, such as, limited or no user-defined memory, small instruction-set, limited number of registers, among others. We propose techniques to overcome such challenges, e.g., by distributing the workload between GPUs and multi-core CPUs, similar to the spirit of heterogeneous computation.

  • 226.
    Majeed, Mudassar
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ahlström, Daniel
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Ericsson AB BU Networks, Stockholm, Sweden.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Efficient Embedding of Deterministic Test Data2010In: 19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010., 2010, 159-162 p.Conference paper (Refereed)
    Abstract [en]

    Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor technologies require not only manufacturing test, but also in-field test. Preferably, the same test set is utilized both at manufacturing test and in-field test. While deterministic test patterns provide high fault coverage, storing complete test vectors leads to huge memory requirements and inflexibility in applying tests. In an IEEE 1149.1 (Boundary scan) environment, this paper presents an approach to efficiently embed deterministic test patterns in the system by taking structural information of the system into account. Instead of storing complete test vectors, the approach stores only commands and component-specific test sets per each unique component. Given a command, test vectors are created by a test controller during test application. The approach is validated on hardware and experiments on ITC’02 benchmarks and industrial circuits show that the memory requirement for storing the test data for a system is highly related to the number of unique components.

  • 227.
    Majeed, Mudassar
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ahlström, Daniel
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Carlsson, Gunnar
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Efficient Embedding of Deterministic Test Data2010In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper (Other academic)
  • 228.
    Manolache, Sorin
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Analysis and Optimisation of Real-Time Systems with Stochastic Behaviour2005Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Embedded systems have become indispensable in our life: household appliances, cars, airplanes, power plant control systems, medical equipment, telecommunication systems, space technology, they all contain digital computing systems with dedicated functionality. Most of them, if not all, are real-time systems, i.e. their responses to stimuli have timeliness constraints.

    The timeliness requirement has to be met despite some unpredictable, stochastic behaviour of the system. In this thesis, we address two causes of such stochastic behaviour: the application and platform-dependent stochastic task execution times, and the platform-dependent occurrence of transient faults on network links in networks-on-chip.

    We present three approaches to the analysis of the deadline miss ratio of applications with stochastic task execution times. Each of the three approaches fits best to a different context. The first approach is an exact one and is efficiently applicable to monoprocessor systems. The second approach is an approximate one, which allows for designer-controlled trade-off between analysis accuracy and analysis speed. It is efficiently applicable to multiprocessor systems. The third approach is less accurate but sufficiently fast in order to be placed inside optimisation loops. Based on the last approach, we propose a heuristic for task mapping and priority assignment for deadline miss ratio minimisation.

    Our contribution is manifold in the area of buffer and time constrained communication along unreliable on-chip links. First, we introduce the concept of communication supports, an intelligent combination between spatially and temporally redundant communication. We provide a method for constructing a sufficiently varied pool of alternative communication supports for each message. Second, we propose a heuristic for exploring the space of communication support candidates such that the task response times are minimised. The resulting time slack can be exploited by means of voltage and/or frequency scaling for communication energy reduction. Third, we introduce an algorithm for the worst-case analysis of the buffer space demand of applications implemented on networks-on-chip. Last, we propose an algorithm for communication mapping and packet timing

    for buffer space demand minimisation.

    All our contributions are supported by sets of experimental results obtained from both synthetic and real-world applications of industrial size.

  • 229.
    Manolache, Sorin
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Schedulability analysis of real-time systems with stochastic task execution times2002Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Systems controlled by embedded computers become indispensable in our lives and can be found in avionics, automotive industry, home appliances, medicine, telecommunication industry, mecatronics, space industry, etc. Fast, accurate and flexible performance estimation tools giving feedback to the designer in every design phase are a vital part of a design process capable to produce high quality designs of such embedded systems.

    In the past decade, the limitations of models considering fixed task execution times have been acknowledged for large application classes within soft real-time systems. A more realistic model considers the tasks having varying execution times with given probability distributions. No restriction has been imposed in this thesis on the particular type of these functions. Considering such a model, with specified task execution time probability distribution functions, an important performance indicator of the system is the expected deadline miss ratio of tasks or task graphs.

    This thesis proposes two approaches for obtaining this indicator in an analytic way. The first is an exact one while the second approach provides an approximate solution trading accuracy for analysis speed. While the first approach can efficiently be applied to monoprocessor systems, it can handle only very small multi-processor applications because of complexity reasons. The second approach, however, can successfully handle realistic multiprocessor applications. Experiments show the efficiency of the proposed techniques.

  • 230.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs2006In: Design Automation and Test in Europe Conference DATE 2006,2006, Munich, Germany: IEEE Computer Society Press , 2006, 718- p.Conference paper (Refereed)
    Abstract [en]

    This paper addresses communication optimisation for applications implemented on networks-on-chip. The mapping of data packets to network links and the timing of the release of the packets are critical for avoiding destination contention. This reduces the demand for communication buffers with obvious advantages in chip area and energy savings. We propose a buffer need analysis approach and a strategy for communication synthesis and packet release timing with minimum communication buffer demand that guarantees worst-case response times.

  • 231.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fault and EnergyAware Communication Mapping with Guaranteed Latency for Applications Implemented on NoC2005In: 42nd Design Automation Conference,2005, Anaheim, CA, USA: IEEE Computer Society Press , 2005, 266- p.Conference paper (Refereed)
    Abstract [en]

    As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on bo th message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmiss ion of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statica lly assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. Firstly, we reduce the total amount of transmitted messages, and, secondly, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arriva l probability and guaranteed worst case application response time.

  • 232.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fault-aware communication mapping for NoCs with guaranteed latency2007In: International journal of parallel programming, ISSN 0885-7458, Vol. 35, no 2, 125-156 p.Article in journal (Refereed)
    Abstract [en]

    As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. First, we reduce the total amount of transmitted messages, and, second, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time. © Springer Science+Business Media, LLC 2007.

  • 233.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Memory and Time-Efficient Schedulability Analysis of Task Sets with Stochastic Execution Time2001In: 13th Euromicro Conference on Real-Time Systems,2001, Delft, The Netherlands: IEEE Computer Society Press , 2001, 19- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents an efficient way to analyse the performance of task sets, where the task execution time is specified as a generalized continuous probability distribution. We consider fixed task sets of periodic, possibly dependent, non-pre-emptable tasks with deadlines less than or equal to the period. Our method is not restricted to any specific scheduling policy and supports policies with both dynamic and static priorities. An algorithm to construct the underlying stochastic process in a memory and time efficient way is presented. We discuss the impact of various parameters on complexity, in terms of analysis time and required memory. Experimental results show the efficiency of the proposed approach.

  • 234.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Optimization of Soft Real-Time Systems with Deadline Miss Ratio Constraints2004In: 10th IEEE Real-Time and Embedded Technology and Applications Symposium,2004, Toronto, Canada: IEEE Computer Society Press , 2004, 562- p.Conference paper (Refereed)
    Abstract [en]

    Both analysis and design optimization of real-time systems has predominantly concentrated on considering hard real-time constraints. For a large class of applications, however, this is both unrealistic and leads to unnecessarily expensive implementations. This paper addresses the problem of task priority assignment and task mapping in the context of multiprocessor applications with stochastic execution times and in the presence of constraints on the percentage of missed deadlines. We propose a design space exploration strategy based on Tabu Search together with a fast method for system performance analysis. Experiments emphasize the efficiency of the proposed analysis method and optimization heuristic in generating high quality implementations of soft real-time systems with stochastic task execution times and constraints on deadline miss ratios

  • 235.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Real-Time Applications with Stochastic Task Execution Times2007 (ed. 1)Book (Other academic)
    Abstract [sv]

    This book presents three approaches to the analysis of the deadline miss ratio of applications with stochastic task execution times. Each best fits a different context: an exact one efficiently applicable to monoprocessor systems; an approximate one, which allows for designer-controlled trade-off between analysis accuracy and analysis speed; and one less accurate but sufficiently fast in order to be placed inside optimization loops

  • 236.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis of Applications with Stochastic Task Execution Times2004In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 3, no 4, 706-735 p.Article in journal (Refereed)
    Abstract [en]

    In the past decade, the limitations of models considering fixed (worst-case) task execution times have been acknowledged for large application classes within soft real-time systems. A more realistic model considers the tasks having varying execution times with given probability distributions. Considering such a model with specified task execution time probability distribution functions, an important performance indicator of the system is the expected deadline miss ratio of the tasks and of the task graphs. This article presents an approach for obtaining this indicator in an analytic way. Our goal is to keep the analysis cost low, in terms of required analysis time and memory, while considering as general classes of target application models as possible. The following main assumptions have been made on the applications that are modeled as sets of task graphs: the tasks are periodic, the task execution times have given generalized probability distribution functions, the task execution deadlines are given and arbitrary, the scheduling policy can belong to practically any class of non-preemptive scheduling policies, and a designer supplied maximum number of concurrent instantiations of the same task graph is tolerated in the system. Experiments show the efficiency of the proposed technique for monoprocessor systems.

  • 237.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Schedulability Analysis of Multiprocessor Real-Time Applications with Stochastic Task Execution Times2002In: Intl Conference on Computer Aided Design, ICCAD 02,2002, San Jose, California, USA: IEEE Computer Society Press , 2002, 699- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents an approach to the analysis of task sets implemented on multiprocessor systems, when the task execution times are specified as generalized probability distributions. Because of the extreme complexity of the problem, an exact solution is practically impossible to be obtained even for toy examples. Therefore, our methodology is based on approximating the generalized probability distributions of execution times by Coxian distributions of exponentials. Thus, we transform the generalized semi-Markov process, corresponding to the initial problem, into a continuous Markov chain (CTMC) which, however, is extremely large and, hence, most often is impossible to be stored in memory. We have elaborated a solution which allows to generate and analyze the CTMC in an efficient way, such that only a small part has to be stored at a given time. Several experiments investigate the impact of various parameters on complexity, in terms of time and memory, as well as the trade-offs regarding the accuracy of generated results.

  • 238.
    Manolache, Sorin
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Schedulability Analysis of Real-Time Systems with Stochastic Task Execution Times2006In: ARTES: A network for Real-Time research and graduate Education in Sweden 1997-2006 / [ed] Hans Hansson, Uppsala: The Department of Information Technology , 2006, 123-159 p.Chapter in book (Other academic)
    Abstract [en]

    For soft real-time applications, a system is considered to function correctly even if some timeliness requirements are occasionally broken, since this leads only to a tolerable reduction of the service quality. Analysis of such a system should be focused on the degree to which the system meets its timeliness requirements rather than on a binary answer indicating whether the whole system is schedulable or not. In many soft real-time applications, the task execution times vary also widely since they are dependent on many parameters. In such a context, analysis techniques based on worst case execution time assumption will lead to very pessimistic results, and many techniques have been developed to consider a more realistic model that assumes tasks to have varying execution times with given probability distributions. The chapter presents one of such techniques. It describes an analytic method to produce the expected deadline miss ratio of the tasks and the task graphs that represent a software real-time application. The reported method improves the currently existing ones by providing exact solutions for larger and less restricted task sets. In particular, it allows continuous task execution time probability distributions, and supports different scheduling policy. Furthermore, task dependencies and arbitrary deadlines are supported by the proposed technique.

  • 239.
    Manolache, Sorin
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Task mapping and priority assignment for soft real-time applications under deadline miss ratio constraints2008In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, Vol. 7, no 2Article in journal (Refereed)
    Abstract [en]

    Both analysis and design optimisation of real-time systems has predominantly concentrated on considering hard real-time constraints. For a large class of applications, however, this is both unrealistic and leads to unnecessarily expensive implementations. This paper addresses the problem of task priority assignment and task mapping in the context of multiprocessor applications with stochastic execution times and in the presence of constraints on the percentage of missed deadlines. We propose a design space exploration strategy together with a fast method for system performance analysis. Experiments emphasize the efficiency of the proposed analysis method and optimisation heuristic in generating high-quality implementations of soft real-time systems with stochastic task execution times and constraints on deadline miss ratios.

  • 240.
    Marculescu, R.
    et al.
    Dept. of Elec./Computer Eng., Carnegie Mellon Univ., 5000 Forbes Ave., Pittburgh, PA 15213-3890, United States.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Designing real-time embedded multimedia systems2004In: IEEE Design & Test of Computers, ISSN 0740-7475, Vol. 21, no 5, 354-356 p.Other (Other academic)
    Abstract [en]

    [No abstract available]

  • 241. Marculescu, R
    et al.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Guest editors' introduction: Designing real-time embedded multimedia systems2004In: IEEE Design & Test of Computers, ISSN 0740-7475, Vol. 21, no 5, 354-356 p.Other (Other academic)
  • 242.
    Marinissen, Erik Jan
    et al.
    NXP Semiconductors Research, The Netherlands.
    Adolfsson, Dan
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Goel, Sandeep-Kumar
    Magma Design Automation, USA.
    Improved Scan Chain Diagnosis2007In: 15th NXP IC Test Symposium,2007, 2007Conference paper (Other academic)
  • 243.
    Mohamed, Abdil
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    High-Level Techniques for Built-In Self-Test Resources Optimization2005Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Design modifications to improve testability usually introduce large area overhead and performance degradation. One way to reduce the negative impact associated with improved testability is to take testability as one of the constraints during high- level design phases so that systems are not only optimized for area and performance, but also from the testability point of view. This thesis deals with the problem of optimizing testing-hardware resources by taking into account testability constraints at high-levels of abstraction during the design process. Firstly, we have provided an approach to solve the problem of optimizing built-in selftest (BIST) resources at the behavioral and register-transfer levels under testability and testing time constraints. Testing problem identification and BIST enhancement during the optimization process are assisted by symbolic testability analysis. Further, concurrent test sessions are generated, while signature analysis registers sharing conflicts as well as controllability and observability constraints are considered. Secondly, we have introduced the problem of BIST resources insertion and optimization while taking wiring area into account. Testability improvement transformations have been defined and deployed in a hardware overhead minimization technique used during a BIST synthesis process. The technique is guided by the results of symbolic testability analysis and inserts a minimal amount of BIST resources into the design to make it fully testable. It takes into consideration both BIST components cost and wiring overhead. Two design space exploration approaches have been proposed: a simulated annealing based algorithm and a greedy heuristic. Experimental results show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored. The greedy heuristic uses our behavioral and register-transfer levels BIST enhancement metrics to guide BIST synthesis in such a way that the number of testability improvement transformations performed on the design is reduced.

  • 244.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Heuristic for Wiring-Aware Built-In Self-Test Synthesis2004In: EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools,2004, Rennes, France: IEEE Computer Society Press , 2004, 408- p.Conference paper (Refereed)
    Abstract [en]

    This paper addresses the problem of BIST synthesis that takes into account wiring area. A technique for minimizing BIST hardware overhead is presented. The technique uses results of symbolic testability analysis to guarantee testability of all modules in the design. New behavioral-level BIST enhancement metrics are used to guide synthesis in such a way that the number of testability enhancements is minimized. The technique is not only fast but also adds low BIST overhead.

  • 245.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead2003Other (Other (popular science, discussion, etc.))
    Abstract [en]

    This paper describes a built-in self-test hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system tomake it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored. Keywords: BIST insertion, test synthesis, wiring area, and Simulated Annealing.

  • 246.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead2005In: Journal of Computer Science and Technology, ISSN 1000-9000, E-ISSN 1860-4749, Vol. 20, no 2, 216-223 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.

  • 247.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead2004In: The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004,2004, 2004, 413-415 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes a built-in self-test hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It considers both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.

  • 248.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    BIST Synthesis: An Approach to Resource Optimization under Test Time Constraints2001Other (Other (popular science, discussion, etc.))
    Abstract [en]

    This paper describes an approach to optimize BIST resource usage for system on chip under testing time constraints. A symbolic testability analysis technique is used to analyze testability of the design for pseudorandom BIST. The testability analysis results are used to guide high-level synthesis of system on chip blocks with BIST mechanisms. Finally, BIST resources are optimized to comply with test time constraints. Key words: BIST, testing time, symbolic testability analysis, and high-level BIST synthesis.

  • 249.
    Mohamed, Abdil
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    BIST Synthesis: An Approach to Resources Optimization under Test Time Constraints2002In: 5th Design and Diagnostic of Electronic Computer Systems DDECS2002,2002, 2002, 346-351 p.Conference paper (Refereed)
    Abstract [en]

    An Approach at optimizing the BIST resource usage under test-time constraints is introduced. The test problem identification and BIST enhancement strategy during the optimization process are assisted by symbolic testability analysis. Further, concurrent test sessions are generated, while MISRs sharing conflicts as well as controllability and observability constraints are considered.

  • 250.
    Muhammad Hassan, Syed
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Optimization Of Error Detection In Embedded Systems2011Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
    Abstract [en]

    This thesis deals with algorithms that optimize the implementation of the error detection technique for soft real-time and multimedia applications in order to minimize their average execution times. We aimed to design the algorithms such that with little hardware available we could achieve maximum time gain.

    In the context of electronic systems implemented with modern semiconductor technologies transient faults have become more and more frequent. Factors like high complexity, smaller transistor sizes, higher operational frequencies and lower voltage levels have contributed to the increase in the rate of transient faults in modern electronic systems.

    As error detection is needed, no matter what tolerance strategy is applied, the detection mechanisms are always present and active. Unfortunately, they are also a major source of time overhead. In order to reduce this overhead designers try to implement error detection in hardware, but this approach increases the overall cost of the system. In general there are three approaches to implement the error detection technique. One extreme implementation involves software only and another extreme implementation involves hardware only.  But we focus on the mixed one which involves both hardware as well as software, in order to generate the best system performance with minimal costs.

    To reduce the time overhead and to achieve maximum time gain, we place as much as possible of the checking expressions in hardware depending on the available resources. The decision is taken based on the frequency information obtained from an execution profile of the program.

    To achieve our goal we have formulated the problem as a knapsack problem, for which we proposed two algorithms.  The first one is a greedy approach and the second one finds the optimal solution using dynamic programming.

    To compare the result for these two algorithms and evaluate their efficiency we have run a series of experiments considering applications with different number of detectors and checking expressions. We have also run our optimization on a real-life application (GSM encoder) to see the how these algorithms perform under real-life scenarios. The experimental evaluation has proved the efficiency of our algorithms under different scenarios.

    Our optimization reduces the time overhead incurred by the error detection component in systems with tight resource constraints. The results presented in this thesis can be used as a foundation for future research in the area. For example, our algorithms could be extended to consider partially dynamically reconfigurable FPGAs or they could be extended so that they give probabilistic guarantees (and could be used in hard real-time systems).

2345678 201 - 250 of 399
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