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  • 151.
    Karlsson, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng , Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Model validation for embedded systems using formal method-aided simulation2008In: IET Computers and digital techniques, ISSN 1751-8601 , Vol. 2, no 6, 413-433 p.Article in journal (Refereed)
    Abstract [en]

    Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex. At the same time, the systems must fulfil strict requirements on reliability and correctness. Informal validation techniques, such as simulation, suffer from the fact that they only examine a small fraction of the state space. Therefore simulation results cannot be 100% guaranteed. Formal techniques, on the other hand, suffer from state-space explosion and might not be practical for huge, complex systems due to memory and time limitations. A validation approach, based on simulation, which addresses some of the above problems is proposed. Formal methods, in particular, model checking, are used to aid, or guide, the simulation process in certain situations in order to boost coverage. The invocation frequency of the model checker is dynamically controlled by estimating certain parameters related to the simulation speed of the particular system at hand. These estimations are based on statistical data collected during the validation session, in order to minimise veri. cation time, and at the same time, achieve reasonable coverage.

  • 152.
    Karlsson, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Formal Verification Approach for IP-based Designs2004In: Forum on Specification and Design Languages,2004, 2004, 556-567 p.Conference paper (Refereed)
    Abstract [en]

    This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already verified by their designers and which are considered correct under the assumption that the environment satisfies certain properties assumed by the component. What remains to be verified is the glue logic inserted between the components. Each such glue logic is verified one at a time using model checking techniques. A big difficulty with such an approach is the question how to handle the connected components and the rest of the system in the verification of the glue logic, which only constitutes a small part of the design. In this paper, algorithms for generating a model corresponding to the rest of the system are discussed together with guidelines on how and when to use them. The methodology is illustrated by a small case study on a mobile telephone.

  • 153.
    Karlsson, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Formal Verification Methodology for IP-based Designs2004In: EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools,2004, Rennes, France: IEEE Computer Society Press , 2004, 372- p.Conference paper (Refereed)
    Abstract [en]

    This paper proposes a formal verification methodology which smoothly integrates with component-based system-level design, using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already verified by their designers and which are considered correct under the assumption that the environment satisfies certain properties assumed by the component. What remains to be verified is the glue logic inserted between the components. Each such glue logic is verified one at a time using model checking techniques. Experiments, performed on a real-life example (mobile telephone), demonstrating the efficiency and intuitivity of the methodology, are moreover thoroughly presented. Three different properties have been verified on one part of the system.

  • 154.
    Karlsson, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Front End to a Java Based Environment for the Design of Embedded Systems2001In: 4th IEEE DDECS Workshop,2001, 2001, 71-78 p.Conference paper (Refereed)
    Abstract [en]

    During the design of embedded systems, at a certain point, the specification has to be transformed into an internal design representation. From that representation it should be possible to further perform system partitioning, mapping and scheduling. This report provides a framework to specify a system in Java and a way to automatically translate that specification into an internal design representation. That design representation is the Conditional Process Graph which captures both the data and the control flow at process level.

  • 155.
    Karlsson, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Formal Verification in a Component-based Reuse Methodology2002In: nternational Symposium on System Synthesis ISSS 2002,2002, Kyoto, Japan: IEEE Computer Society Press , 2002, 156- p.Conference paper (Refereed)
    Abstract [en]

    There is an important trend towards design processes based on the reuse of predesigned components. We propose a formal verification approach which smoothly integrates with a component based system-level design methodology. Once a timed Petri Net model corresponding to the interface logic has been produced the correctness of the system can be formally verified. The verification is based on the interface properties of the connected components and on abstract models of their functionality, without assuming any knowledge regarding their implementation. We have both developed the theoretical framework underlying the methodology and implemented an experimental environment using model checking techniques.

  • 156.
    Karlsson, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Formal verification of component-based designs2007In: Design automation for embedded systems, ISSN 0929-5585, Vol. 11, no 1, 49-90 p.Article in journal (Refereed)
    Abstract [en]

    Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex, and designers handle this increasing complexity by reusing existing components (Intellectual Property blocks). At the same time, the systems must fulfill strict requirements on reliability and correctness. This paper proposes a formal verification methodology which smoothly integrates with component-based system-level design using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already formally verified by their designers. The components are considered correct given that the environment satisfies certain properties imposed by the component. The methodology verifies the correctness of the glue logic inserted between the components and the interaction of the components through the glue logic. Each such glue logic is verified one at a time using model checking techniques. Experimental results have shown the efficiency of the proposed methodology and demonstrated that it is feasible to apply such a verification methodology on real-life examples. © Springer Science + Business Media, LLC 2006.

  • 157.
    Karlsson, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Formal Verification of SystemC Designs Using a Petri-Net based Representation2006In: Design Automation and Test in Europe Conference DATE 2006,2006, Munich, Germany: IEEE Computer Society Press , 2006, 1228- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is then used for model checking of properties expressed in a timed temporal logic. The approach is particularly suitable for, but not restricted to, models at a high level of abstraction, such as transaction-level. The efficiency of the approach is illustrated by experiments.

  • 158.
    Karlsson, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Transactor-based Formal Verification of Real-time Embedded Systems2008In: Embedded Systems Specification and Design Languages / [ed] D. Karlsson,Z. Peng ,P. Eles, Dordrecht, Netherlands: Springer , 2008, 1, 255-270 p.Chapter in book (Other academic)
    Abstract [en]

      With the increasing complexity of today-s embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some components are described at high levels of abstraction, whereas others are described at low levels. Components in single abstraction level designs communicate through channels, which capture essential features of the communication. If the connected components communicate at different abstraction levels, then these channels are replaced with transactors that translate requests back and forth between the abstraction levels. It is important that the transactor still preserves the external characteristics, e.g. timing, of the original channel. This chapter proposes a technique to generate such transactors. According to this technique, transactors are specified in a single formal language, which is capable of capturing timing aspects. The approach is especially targeted to formal verification.

  • 159.
    Karlsson, Daniel
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Validation of Embedded Systems using Formal Method aided Verification2005In: 8th Euromicro Conference on Digital System Design DSD2005,2005, Porto, Portugal: IEEE Computer Society Press , 2005, 196- p.Conference paper (Refereed)
    Abstract [en]

    Informal validation techniques, such as simulation, suffer from the fact that they only examine a small fraction of the state space. Formal techniques, on the other hand, suffer from state space explosion and are not practical to use for huge, complex systems. This paper proposes a validation approach, based on simulation, which addresses some of the above problems. Formal methods, in particular model checking, are used to aid the simulation process in certain situations in order to boost coverage. The invocation frequency of the model checker is dynamically controlled by estimating certain parameters, based on statistics collected previously during the same validation session, in order to minimise verification time and at the same time achieve reasonable coverage. The approach has been demonstrated feasible by numerous experimental results.

  • 160.
    Larsson, Anders
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    System-on-Chip Test Scheduling and Test Infrastructure Design2005Licentiate thesis, monograph (Other academic)
    Abstract [en]

    There are several challenges that have to be considered in order to reduce the cost of System-on-Chip (SoC) testing, such as test application time, chip area overhead due to hardware introduced to enhance the testing, and the price of the test equipment. In this thesis the test application time and the test infrastructure hardware overhead of multiple-core SoCs are considered and two different problems are addressed. First, a technique that makes use of the existing bus structure on the chip for transporting test data is proposed. Additional buffers are inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. A test controller is introduced, which is responsible for the invocation of test transportations on the bus. The hardware cost, introduced by the buffers and test controller, is minimized under a designer-specified test time constraint. This problem has been solved optimally by using a Constraint Logic Programming formulation, and a tabu search based heuristic has also been implemented to generate quickly near-optimal solutions. Second, a technique to broadcast tests to several cores is proposed, and the possibility to use overlapping test vectors from different tests in a SoC is explored. The overlapping tests serve as alternatives to the original, dedicated, tests for the individual cores and, if selected, they are broadcasted to the cores so that several cores are tested concurrently. This technique allows the existing bus structure to be reused; however, dedicated test buses can also be introduced in order to reduce the test time. Our objective is to minimize the test application time while a designer-specified hardware constraint is satisfied. Again Constraint Logic Programming has been used to solve the problem optimally. Experiments using benchmark designs have been carried out to demonstrate the usefulness and efficiency of the proposed techniques.

  • 161.
    Larsson, Anders
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Test Optimization for Core-based System-on-Chip2008Doctoral thesis, monograph (Other academic)
    Abstract [en]

    The semiconductor technology has enabled the fabrication of integrated circuits (ICs), which may include billions of transistors and can contain all necessary electronic circuitry for a complete system, so-called System-on-Chip (SOC). In order to handle design complexity and to meet short time-to-market requirements, it is increasingly common to make use of a modular design approach where an SOC is composed of pre-designed and pre-verified blocks of logic, called cores.

    Due to imperfections in the fabrication process, each IC must be individually tested. A major problem is that the cost of test is increasing and is becoming a dominating part of the overall manufacturing cost. The cost of test is strongly related to the increasing test-data volumes, which lead to longer test application times and larger tester memory requirement. For ICs designed in a modular fashion, the high test cost can be addressed by adequate test planning, which includes test-architecture design, test scheduling, test-data compression, and test sharing techniques.

    In this thesis, we analyze and explore several design and optimization problems related to core-based SOC test planning. We perform optimization of test sharing and test-data compression. We explore the impact of test compression techniques on test application time and compression ratio. We make use of analysis to explore the optimization of test sharing and test-data compression in conjunction with test-architecture design and test scheduling. Extensive experiments, based on benchmarks and industrial designs, have been performed to demonstrate the significance of our techniques.

  • 162.
    Larsson, Anders
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Chakrabarty, Krishnendu
    Duke University, USA.
    Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs2010In: Design and Test Technology for Dependable Systems-on-chip / [ed] Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, Information Science Publishing , 2010Chapter in book (Other academic)
    Abstract [en]

    Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.

    Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined "classical" design and test topics and solutions for IC test technology and fault-tolerant systems.

  • 163.
    Larsson, Anders
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ingmarsson, Magnus
    Linköping University, Department of Computer and Information Science, MDALAB - Human Computer Interfaces. Linköping University, The Institute of Technology.
    Sun, Bo
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    A Development Platform for Distributed User Interfaces2007In: Proceedings of the Nineteenth InternationalConference on Software Engineering & Knowledge Engineering (SEKE’2007), 2007, 704-704 p.Conference paper (Refereed)
    Abstract [en]

    Developing user interfaces for a heterogeneous environment is a difficult challenge. Partial distribution of the user interface is an event harder one. Specifically providing developers with means of describing and controlling how components move around as devices are included or removed We present an approach to overcome these challenges, by combining ontologies with reasoning engines. Our tool MaDoE uses Protégé in combination with Jess to exemplify this in a simulated home setting. Our approach allows system developers to take advantage of the formal knowledge in the ontologies as well harnessing the power of rules inside the expert system when they design distributed user interfaces.

  • 164.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Chakrabarty, Krishnendu
    Electrical and Computer Engineering Dept. Duke University, USA.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns2008In: Design, Automation, and Test in Europe DATE 2008,2008, Munich, Germany: IEEE Computer Society Press , 2008, 188- p.Conference paper (Refereed)
    Abstract [en]

    The ever-increasing test data volume for core-based system-on-chip (SOC) integrated circuits is resulting in high test times and excessive tester memory requirements. To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns. For each wrapped embedded core and its decompressor, we show that the test time does not decrease monotonically with the width of test access mechanism (TAM) at the decompressor input. We optimize the wrapper and decompressor designs for each core, as well as the TAM architecture and the test schedule at the SOC level. Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a method that does not rely on core-level decompression of patterns.

  • 165.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing2007In: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems,2007, Krakow, Poland: IEEE Computer Society Press , 2007, 61- p.Conference paper (Refereed)
    Abstract [en]

    The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipment (ATE) memory. Test compression and test sharing have been proposed to reduce the test data volume, while test infrastructure and concurrent test scheduling have been developed to reduce the test application time. In this work we propose an integrated test scheduling and test infrastructure design approach that utilizes both test compression and test sharing as basic mechanisms to reduce test data volumes. In particular, we have developed a heuristic to minimize the test application time, considering different alternatives of test compression and sharing, without violating a given ATE memory constraint. The results from the proposed Tabu Search based heuristic have been validated using benchmark designs and are compared with optimal solutions.

  • 166.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Technique for Optimization of System-on-Chip Test Data Transportation2004In: 9th IEEE European Test Symposium,2004, 2004, 179-180 p.Conference paper (Refereed)
    Abstract [en]

    We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.

  • 167.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip2003In: 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03,2003, Cambridge, MA, USA: IEEE Computer Society Press , 2003, 385- p.Conference paper (Refereed)
    Abstract [en]

    Test scheduling and Test Access Mechanism (TAM)design are two important tasks in the development of a System-on-Chip (SOC)test solution.Previous test scheduling techniques assume a dedicated designed TAM which have the advantage of high exibility in the scheduling process. However,hardware verhead for implementing the TAM and additional routing is required of the TAMs.In this paper we propose a technique that makes use of the existing functional buses for the test data transportation inside the SOC.We have dealt with the test scheduling problem with this new assumption and developed a technique to minimize the test-controller and buffer size for a bus- based multi-core SOC.We have solved the problem by using a constraint logic pr gramming (CLP) technique and demonstrated the ef ciency of our approach by running experiments on benchmark designs.

  • 168.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip2005In: 8th Euromicro Conference on Digital System Design DSD2005,2005, Porto, Portugal: IEEE Computer Society Press , 2005, 403- p.Conference paper (Refereed)
    Abstract [en]

    The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the chip. Having a powerful TAM will shorten the test time, but it costs large silicon area to implement it. Hence, it is important to have an efficient TAM with minimal required hardware overhead. We propose a technique that makes use of the existing bus structure with additional buffers inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. We have implemented a Tabu search based technique to optimize our test architecture, and the experimental results indicate that it produces high quality results at low computational cost.

  • 169.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Optimized Integration of Test Compression and Sharing for SOC Testing2007In: Design, Automation, and Test in Europe Conference DATE07,2007, Nice, France: IEEE Computer Society Press , 2007, 207- p.Conference paper (Refereed)
    Abstract [en]

    The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs.

  • 170.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    SOC Test Scheduling with Test Set Sharing and Broadcasting2005In: IEEE Asian Test Symposium,2005, Kolkata, India: IEEE Computer Society Press , 2005, 162- p.Conference paper (Refereed)
    Abstract [en]

    Due to the increasing test data volume needed to test core-based System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In contrast to approaches where a fixed test set for each core is assumed, we explore the possibility to use overlapping test patterns from the tests in the system. The overlapping tests serves as alternatives to the original dedicated test for the cores and, if selected, they are transported to the cores in a broadcasted manner so that several cores are tested concurrently. We have made use of a Constraint Logic Programming technique to select suitable tests for each core in the system and schedule the selected tests such that the test application time is minimized while designer-specified hardware constraints are satisfied. The experimental results indicate that we can on average reduce the test application time with 23%.

  • 171.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Zhang, Xin
    Masters Programme in Computer Science Linköpings Universitet.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Chakrabarty, Krishnendu
    Dept. of Electrical and Computer Engineering Duke University, USA.
    Core-Level Expansion of Compressed Test Patterns2008In: Proceedings of the Asian Test Symposium, Sapporo, JAPAN: IEEE Computer Society , 2008, 277-282 p.Conference paper (Refereed)
    Abstract [en]

     The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.

  • 172.
    Larsson, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Zhang, Xin
    Masters Programme in Computer Science Linköpings Universitet.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Chakrabarty, Krishnendu
    Dept. of Electrical and Computer Engineering Duke University, USA.
    SOC Test Optimization with Compression-Technique Selection2008In: Proceedings - International Test Conference, IEEE , 2008, 1- p.Conference paper (Other academic)
    Abstract [en]

    The increasing test-data volumes needed for the testing of system-on-chip (SOC) lead to long test times and high memory requirements. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. Therefore, we propose a technique where compression-technique selection is integrated with core wrapper design, test architecture design, and test scheduling to minimize the SOC test time and the test-data volume.

  • 173.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment2008In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, no 4, 275-284 p.Article in journal (Refereed)
    Abstract [en]

     The semiconductor technology development makes it possible to fabricate increasingly advanced integrated circuits (ICs). However, because of imperfections at manufacturing, each individual IC must be tested. A major problem at IC manufacturing test is the increasing test data volume as it leads to high automatic test equipment (ATE) memory requirement, long test application time and low throughput. In contrast with existing approaches, which address either test data compression for ATE memory reduction or abort-on-fail testing for test time minimisation, an architecture that supports both test data compression and abort-on-fail testing at clock-cycle granularity is proposed, and hence both ATE memory reduction and test application time minimisation are addressed. Further, the proposed architecture efficiently tackles low throughput as the architecture allows multi-site testing at a constant ATE memory requirement, which is independent of the number of tested ICs. Advantages of the architecture, compared with test compression architecture, are that diagnostic capabilities are not reduced and there is no need for special handling of unknowns (X) in the produced test responses (PR). Experiments on ISCAS benchmark circuits and an industrial circuit have been performed.

  • 174.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    An Integrated System-Level Design for Testability Methodology2000Doctoral thesis, monograph (Other academic)
    Abstract [en]

    HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems.

    The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design.

    The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources.

    Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system.

    Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level.

  • 175.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Combined Test Data Compression and Abort-on-Fail Test2006In: 24th IEEE Norchip Conference,2006, Linköping: IEEE Computer Society Press , 2006Conference paper (Refereed)
    Abstract [en]

    The increasing test data volume needed for the testing of System-on-Chips (SOCs) leads to high Automatic Test Equipment (ATE) memory requirement and long test application times. Scheduling techniques where testing can be terminated as soon as a fault appears (abort-on-fail) as well as efficient compression schemes to reduce the ATE memory requirement have been proposed separately. Previous test data compression architectures often make use of Multiple Input Signature Response Analyzers (MISRs) for response compression. Therefore, abort-on-fail testing and diagnostic capabilities are limited. In this paper, we propose an SOC test architecture that (1) allows test data compression, (2) where clock cycle based as well as patternbased abort-on-fail testing are allowed and (3) diagnostic capabilities are not reduced. We have performed experiments on ISCAS designs.

  • 176.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Conference Reports - RASDAT 2011: Workshop on Reliability Aware System Design and Test2011In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 28, no 3, S. 82-83 p.82-83 p.Article in journal (Other academic)
    Abstract [en]

    Conference Reports features the second IEEE International Workshop on Reliability Aware System Design and Test (RASDAT),which was held in conjunction with the 24th International Conference on VLSI Design.

  • 177.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Conference Reports: ETS 2011: European Test Symposium2011In: IEEE Design & Test of Computers, ISSN 0740-7475, E-ISSN 1558-1918, Vol. 28, no 5, 95-95 p.Article in journal (Other (popular science, discussion, etc.))
  • 178.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Core Selection Integrated in the SOC Test Solution Design-Flow2004Other (Other (popular science, discussion, etc.))
  • 179.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Integrating Core Selection in the SOC Test Solution Design-Flow2004In: International Test conference ITC04,2004, Charlotte, NC, USA: IEEE Computer Society Press , 2004, 1349- p.Conference paper (Refereed)
    Abstract [en]

    We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel three-level power model: system, power-grid, and core. We have implemented and compared the proposed technique, a fast estimation technique and a computational extensive pseudo-exhaustive method, and the results demonstrate that our technique produces high quality solutions at reasonable computational cost.

  • 180.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Introduction to Advanced System-on-Chip Test Design and Optimization2005Book (Other academic)
    Abstract [en]

    Testing of Integrated Circuits is important to ensure the production of fault-free chips. However, testing is becoming cumbersome and expensive due to the increasing complexity of these ICs. Technology development has made it possible to produce chips where a complete system, with an enormous transistor count, operating at a high clock frequency, is placed on a single die - SOC (System-on-Chip). The device size miniaturization leads to new fault types, the increasing clock frequencies enforces testing for timing faults, and the increasing transistor count results in a higher number of possible fault sites. Testing must handle all these new challenges in an efficient manner having a global system perspective. Test design is applied to make a system testable. In a modular core-based environment where blocks of reusable logic, the so called cores, are integrated to a system, test design for each core include: test method selection, test data (stimuli and responses) generation (ATPG), definition of test data storage and partitioning [off-chip as ATE (Automatic Test Equipment) and/or on-chip as BIST (Built-In Self-Test)], wrapper selection and design (IEEE std 1500), TAM (test access mechanism) design, and test scheduling minimizing a cost function whilst considering limitations and constraint. A system test design perspective that takes all the issues above into account is required in order to develop a globally optimized solution. SOC test design and its optimization is the topic of this book. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.

  • 181.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Power-Aware SOC Test Planning, (Keynote): Workshop on RTL and High Level Testing (WRTLT08), Sapporo, Japan, November 2008.2008Other (Other academic)
  • 182.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Preemptive system-on-chip test scheduling2004In: IEICE transactions on information and systems, ISSN 0916-8532, Vol. E87D, no 3, 620-629 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.

  • 183.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Testing advanced electronics systems (One-day Tutorial): IEEE Asia Pacific Conference on Circuits and Systems (APCCAS10), Malaysia, December 2010.2010Other (Other academic)
  • 184.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Amirijoo, Mehdi
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, RTSLAB - Real-Time Systems Laboratory.
    Karlsson, Daniel
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    What Impacts Course Evaluation?2007In: 12th SIGCSE Conf. on Innovation and Technology in Computer Science Education,2007, 2007, 333-333 p.Conference paper (Refereed)
    Abstract [en]

    Today most universities are using course evaluations. However, course evaluations are often discussed and questioned. This paper reports on a survey where we aim at finding out (1) if students have a preconceived notion of a course, (2) if course evaluation scores can be predicted early in a course, (3) if exam throughput impacts course evaluation, and (4) if web-based evaluation reflects the general opinion from students. The results from the study indicate that students do not let preconceived notion impact nor does exam throughput matter to course evaluation. Further, the final web-based results seem to correlate with opinion of students attending lectures. However, the evaluation grades tend to be defined early in the course; hence first impression lasts.

  • 185.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Arvidsson, Klas
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science.
    Fujiwara, H
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Efficient test solutions for core-based designs2004In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 23, no 5, 758-775 p.Article in journal (Refereed)
    Abstract [en]

    A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed TAM. An extensive TAM will lead to lower test-application time at the expense of higher routing costs, compared to a simple TAM with low routing cost but long testing time. It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test. However, such a test-time reduction often leads to higher power consumption, which must be kept under control since exceeding the power budget could damage the system under test. Furthermore, the execution of a test requires resources and concurrent execution of tests may not be possible due to resource or other conflicts. In this paper, we propose an integrated technique for test scheduling, test parallelization, and TAM design, where the test application time and the TAM routing are minimized, while considering test conflicts and power constraints. The main features of our technique are the efficiency in terms of computation time and the flexibility to model the system's test behavior, as well as the support for the testing of interconnections, unwrapped cores and user-defined logic. We have implemented our approach and made several experiments on benchmarks as well as industrial designs in order to demonstrate that our approach produces high-quality solution at low computational cost.

  • 186.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Arvidsson, Klas
    Embedded Systems Lab. Linköpings Universitet.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Integrated Test Scheduling, Test Parallelization and TAM Design2002In: IEEE Asian Test Symposium ATS02,2002, Tamuning, Guam, USA: IEEE Computer Society Press , 2002, 397- p.Conference paper (Refereed)
    Abstract [en]

    We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.

  • 187.
    Larsson, Erik
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Chakrabarty, Krishnendu
    Duke University, USA.
    Manufacturing Test Solutions for System-On-Chip Integrated Circuits(One-day Tutorial): VLSI Design and Test Symposium (VDAT07), Kolkata, India, August 20072007Other (Other academic)
  • 188.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Edbom, Stina
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint2007In: Vlsi-Soc: From Systems To Silicon / [ed] Ricardo Reis, Adam Osseiran, Hans-Joerg Pfleiderer, Boston, USA: Springer , 2007, 221-244 p.Chapter in book (Other academic)
    Abstract [en]

    Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (System-on-Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number of applied test vectors. The proposed test data truncation scheme selects the appropriate number of test vectors for each individual core based on the test quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system-s test quality is maximized and the test data fits the ATE-s memory. We have implemented the proposed technique and the experimental results, produced at reasonable CPU times, on several ITC-02 benchmarks show that high test quality can be achieved by a careful selection of test data. The results indicate that the test data volume (test application time) can be reduced to about 50% while keeping a high test quality.

  • 189.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Edbom, Stina
    Dept. Computer and Information Science Linköpings Universitet.
    Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint2005In: IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005},2005, 2005, 429-434 p.Conference paper (Refereed)
    Abstract [en]

    The increasing test data volume required to ensure high test quality when testing a System-on-Chip is becoming a problem since it (the test data volume) must fit the ATE (Automatic Test Equipment) memory. In this paper, we (1) define a test quality metric based on fault coverage, defect probability and number of applied test vectors, and (2) a test data truncation scheme. The truncation scheme combines (1) test data (vector) selection for each core based on our metric, and (2) scheduling of the execution of the selected test data, in such a way that the system test quality is maximized, while the selected test data is guaranteed to fit the ATEs memory. We have implemented the technique and the experimental results, produced at reasonable CPU times, on several ITC02 benchmarks show that high test quality can be achieved by a careful selection of test data.

  • 190.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Edbom, Stina
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint2007In: IET Computers and digital techniques, ISSN 1751-8601, Vol. 1, no 1, 27-37 p.Article in journal (Refereed)
    Abstract [en]

    Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.

  • 191.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, H
    System-on-chip test scheduling with reconfigurable core wrappers2006In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 14, no 3, 305-309 p.Article in journal (Refereed)
    Abstract [en]

    The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n), n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection testsre and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound.

  • 192.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Optimal System-on-Chip Test Scheduling2003In: 12th IEEE Asian Test Symposium ATS03,2003, Xian, China: IEEE Computer Society Press , 2003, 306- p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.

  • 193.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers2002Other (Other (popular science, discussion, etc.))
    Abstract [en]

    In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equal to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm producing an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations and also the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.

  • 194.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Power Constrained Preemptive TAM Scheduling2002In: 7th IEEE European Test Workshop,2002, Corfu, Greece: IEEE Computer Society Press , 2002, 119- p.Conference paper (Refereed)
    Abstract [en]

    We integrate scan-chain partitioning and preemptive test access mechanism (TAM) scheduling for core-based systems under power constraint. We also outline a flexible power conscious test wrapper to increase the flexibility in the scheduling process by (1) allowing several different bandwidths at cores and (2) controlling the cores test power consumption, which makes it possible to increase the test clock. We model the scheduling problem as a Bin-packing problem and we discuss the transformations: (1) TAM-time and (2) power-time and the possibilities to achieve an optimal solution and the limitations. We have implemented our proposed preemptive TAM scheduling algorithm and through experiments we demonstrate its efficiency.

  • 195.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Fujiwara, Hideo
    Computer Design and Test Lab. Nara Inst. of Science and Technology.
    Test Resource Partitioning and Optimization for SOC Designs2003In: 2003 IEEE VLSI Test Symposium VTS03,2003, Napa Valley, USA: IEEE Computer Society Press , 2003, 319- p.Conference paper (Refereed)
    Abstract [en]

    We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.

  • 196.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Gilani, Irtiyaz
    Dept. Information and Computer Science Linköpings Universitet.
    A Test Data Compression Architecture with Abort-on Fail Capability2005In: IEEE Workshop on RTL and High Level Testing WRTLT,2005, 2005Conference paper (Other academic)
  • 197.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Anders
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Student-oriented Examination in a Computer Architecture Course2004In: 9th Annual Conference on Innovation and Technology in Computer Science Education,2004, 2004, 245-245 p.Conference paper (Refereed)
    Abstract [en]

    Learning is a highly individual process. Some prefer learning by reading the course material, others learn best by listening to a lecture, while some like to learn in a trial-and-error way by themselves in a laboratory assignment. A good learning scheme is individual. A scheme that is good for some persons might not at all be good scheme for someone else. It is important to understand your own personal way to learn, but also when organizing a course individual learning alternatives should be acknowledged. Examination in a course can be seen as a test occasion or as a learning occasion. Traditionally, examination has been an occasion where knowledge is tested. Written exams can be used to test the theory and laboratory work to test practical aspects of the course material. For laboratory work the distinction between learning and test of learning is somewhat unclear. The learning and the test of learning are mixed. However, in general, examination can be seen as an occasion to learn and/or to test knowledge. We have, in a Computer Architecture course, taken the view that (1) learning is an individual process, and (2) that examination is a learning occasion. The consequence of our view (1)+(2) is basically that examination should be individual, or student-oriented. Alternatives to traditional examination is also supported when taking gender, cultural, and age perspectives. We therefore developed two examination tracks where the students in the beginning of the course decided what track to follow. Common for both tracks is that credits are given that can be counted for in the written exam

  • 198.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling2008In: Journal of electronic testing, ISSN 0923-8174, Vol. 24, no 5, 497-504 p.Article in journal (Refereed)
    Abstract [en]

    The increasing test application times required for testing system-on-chips (SOCs) is a problem that leads to higher costs. For modular core based SOCs it is possibly to employ a concurrent test scheme in order to lower the test application times. To allow each core to be tested as a separate unit, a wrapper is inserted for each core, the scan chains at each core are configured into a fixed number of wrapper chains, and the wrapper chains are connected to the test access mechanism. A problem with concurrent testing is that it leads to higher power consumption as several cores are active at a time. Power consumption above the specified limit of a core or above the limit of the system will cause damage and must be avoided. The power consumption must be controlled both at core level as well as on system level. In this paper, we propose a reconfigurable power conscious core wrapper that we include in a preemptive power constrained test scheduling algorithm. The advantages with the wrapper are that the number of wrapper chains at each core can dynamically be changed during test application and the possibility, through clock gating, to select the appropriate test power consumption for each core. The scheduling technique produces optimal solutions in respect to test time and selects wrapper configurations in a systematic manner while ensuring the power limits at core level and system level are not violated. The wrapper configurations are selected such that the number of wrapper configurations as well as the number of wrapper chains at each wrapper are minimized, which minimizes the wrapper logic as well as the total TAM routing. We have implemented the technique and the experimental results show the efficiency of our approach. © 2008 Springer Science+Business Media, LLC.

  • 199.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling2003In: International Test Conference ITC 2003,2003, Charlotte, NC, USA: IEEE , 2003, 1135- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a novel reconfigurable powerconscious core test wrapper and discusses its application to optimal power-constrained SOC (system-on-chip) test scheduling. The advantage with the proposed wrapper is that at each core it allows (1) a exible TAM (test access mechanism) bandwidths, and (2) a possibility to select the appropriate test power consumption. Our scheduling technique, an extension of a preemptive scheduling approach,produces optimal solutions in respect to test time, and selects wrapper configurations in a systematic way that implicitly minimizes the TAM routing and the wrapper logic. Experimental results show the efficiency of our approach.

  • 200.
    Larsson, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    A Technique for Test Infrastructure Design and Test Scheduling2000In: Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS 2000,2000, Smolenice Castle, Slovakia: IEEE Computer Society Press , 2000, 26- p.Conference paper (Refereed)
    Abstract [en]

    We propose a technique for test scheduling and design of test bus infrastructure where test application time and test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. Our technique has been implemented and experimental results show the efficiency of our approach.

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