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  • 101.
    He, Zhiyuan
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Ion Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Multi-temperature testing for core-based system-on-chip2010In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2010, 208-213 p.Conference paper (Refereed)
    Abstract [en]

    Recent research has shown that different defects can manifest themselves as failures at different temperature spectra. Therefore, we need multi-temperature testing which applies tests at different temperature levels. In this paper, we discuss the need and problems for testing core-based systems-on-chip at different temperatures. To address the long test time problem for multitemperature test, we propose a test scheduling technique that generates the shortest test schedules while keeping the cores under test within a temperature interval. Experimental results show the efficiency of the proposed technique.

  • 102. Holmqvist, Johan
    et al.
    Carlsson, Gunnar
    Digital Processing Platform Ericsson AB, Sweden.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Extended STAPL as SJTAG Engine2007In: IEEE European Test Symposium,2007, Freiburg, Germany: IEEE Computer Society Press , 2007, 119- p.Conference paper (Refereed)
    Abstract [en]

    Integrated Circuits (ICs) and multi-board systems are becoming increasingly complex to test. A key to successful testing is effective standards. Currently, at micro level the Internal JTAG (IJTAG) focuses on the development of a standard for embedded on-chip instruments while at macro level the System JTAG (SJTAG) works on defining a standard for system level test management; mainly connecting the IJTAG standard with the system test manager. In this paper we discuss language requirement for making and handling access between the test manager and embedded instruments. As a base-line we make use of the Standard Test and Programming Language (STAPL). We have identified a number of required extensions that we have implemented in an extended STAPL++ player (interpreter) and language. We have performed initial experiments where we simulated an embedded environment with a PC as test controller running the new player and an FPGA serving as device-under-test.

  • 103.
    Hung, Wei-Chen
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    On-line Thermal Aware Energy Optimization via Dynamic Voltage Selection for Multiprocessor System-On-Chip2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In recent decades, the use of electronic systems, especially embedded systems such as mobile phones has been expanding rapidly. Such products use minimal amount of materials, generate less waste and noise, save space, and are considered cost-effective and attractive. In such devices, consideration needs to be given to both high power density and high chip working temperature.  According to the advanced scaling technology, leakage power becomes a major issue in terms of power consumption and this in turn influences temperature. Consequently, energy optimization is an important issue in the design of such electronic products.

     

    Techniques for energy optimization have been proposed for circuit-level up to the system-level. This study is focused on a system-level model for a multiprocessor system, considering the inter-dependency between leakage power and temperature. The study applies an on-line temperature-aware dynamic voltage selection (DVS) approach to save energy. The method is evaluated and compared to the static approach, which assumes that tasks always execute their worst case number of clock cycles (WNC) allowing for the exploitation of only the static slack. On-line thermal aware DVS allows the exploitation of both the static and dynamic slacks, since the actual number of clock cycles is usually less than the WNC.

  • 104.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Equation-Based Vdd-Aware Model for Resistive Bridge Behavior2010In: IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010., 2010, 34-39 p.Conference paper (Refereed)
  • 105.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Vdd-Aware Bridge Defect Model2010In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)., 2010Conference paper (Other academic)
  • 106.
    Ingelsson, Urban
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Vdd-Aware Model for the Voltage on Bridged Nodes2010In: Workshop track of the IEEE European Test Symposium (ETS 2010), Prague, Czech Republic, May 24-28, 2010., 2010Conference paper (Refereed)
    Abstract [en]

    Resistive bridge defects have Vdd dependent behavior, a fact that is not yet considered in commercial DfT tools. So far, all Vdd-aware models have relied on computationally intensive SPICE simulation to calculate the voltage on the bridged nodes. The computation time limits the use of such models on large designs. Therefore, Vdd-aware models should employ a simplified set of equations that does not require computationally intensive simulation. The observation that enables such a set of simplified equations is that less variables need to be taken into account for modeling bridge behavior compared to SPICE simulations, which need to consider all available variables to model a wide set of circuits and behaviors. Previous approaches to define simplified equations to replace SPICE simulation for modeling resistive bridge behavior are either inaccurate for recent IC technologies or have not explicitly taken Vdd into account. Therefore, this paper proposes simplified equations to model the voltage on the bridged nodes in a computationally efficient manner. The approach is to find accurate equations for the drain-source currents of transistors that are involved in determining the bridge behavior. This paper describes an algorithm for applying the model by calculating the voltage on the bridged nodes given the drain-source currents of the involved transistors. The model is demonstrated by comparing the results from the proposed approach with simulation results for two gate libraries.

  • 107.
    Ingelsson, Urban
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Chang, Shih-Yen
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Cost Reduction of Wear-Out Monitoring by Measurement Point Selection2011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011, 2011Conference paper (Other academic)
    Abstract [en]

    Early failure rates have increased due to reduced feature dimensions and electromigration wear-out. Periodic delay measurements can be employed to estimate the state of wear-out. Including delay measurement sensors on-chip is costly. Therefore, a method is proposed to reduce the number of measurement points. The method identi?es wear-out sensitive interconnects and selects a small number of measurement points to target the identi?ed interconnects. The method is demonstrated on ISCAS85 benchmark ICs.

  • 108.
    Ingelsson, Urban
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Chang, Shih-Yen
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Faculty of Educational Sciences.
    Larsson, Erik
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Measurement Point Selection for In-Operation Wear-Out Monitoring2011In: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011., IEEE , 2011, 381-386 p.Conference paper (Refereed)
    Abstract [en]

    In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wearout monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. The proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. The method is demonstrated on ISCAS85 benchmark ICs with encouraging results.

  • 109.
    Ingelsson, Urban
    et al.
    IDA Linköpings Universitet.
    Goel, Sandeep Kumar
    IC Design Digital Design and Test Philips Research Labs.
    Larsson, Erik
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Marinissen, Erik Jan
    IC Design Digital Design and Test Philips Research Labs.
    Test Scheduling for Modular SOCs in an Abort-on-Fail Environment2005In: IEEE European Test Symposium ETS 05,2005, Tallinn, Estonia: IEEE Computer Society Press , 2005Conference paper (Refereed)
    Abstract [en]

    Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module s manufacturing test. We use it to exploit the abort-on-fail feature of ATEs, in order to reduce the expected test application time. We present a model for expected test application time, which obtains increasing accuracy due to decreasing granularity of the abortable test unit. For a given SOC, with a modular test architecture consisting of wrappers and disjunct TAMs, and for given pass probabilities per module test, we schedule the tests on each TAM such that the expected test application time is minimized. We describe two heuristic scheduling approaches, one without and one with preemption. Experimental results for the ITC 02 SOC Test Benchmarks demonstrate the effectiveness of our approach, as we achieve up to 97% reduction in the expected test application time, without any modification to the SOC or ATE.

  • 110.
    Izosimov, Viacheslav
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling and Optimization of Fault-Tolerant Distributed Embedded Systems2009Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Safety-critical applications have to function correctly and deliver high level of quality-ofservice even in the presence of faults. This thesis deals with techniques for tolerating effects of transient and intermittent faults. Re-execution, software replication, and rollback recovery with checkpointing are used to provide the required level of fault tolerance at the software level. Hardening is used to increase the reliability of hardware components. These techniques are considered in the context of distributed real-time systems with static and quasi-static scheduling.

    Many safety-critical applications have also strict time and cost constrains, which means that not only faults have to be tolerated but also the constraints should be satisfied. Hence, efficient system design approaches with careful consideration of fault tolerance are required. This thesis proposes several design optimization strategies and scheduling techniques that take fault tolerance into account. The design optimization tasks addressed include, among others, process mapping, fault tolerance policy assignment, checkpoint distribution, and trading-off between hardware hardening and software re-execution. Particular optimization approaches are also proposed to consider debugability requirements of fault-tolerant applications. Finally, quality-of-service aspects have been addressed in the thesis for fault-tolerant embedded systems with soft and hard timing constraints.

    The proposed scheduling and design optimization strategies have been thoroughly evaluated with extensive experiments. The experimental results show that considering fault tolerance during system-level design optimization is essential when designing cost-effective and high-quality fault-tolerant embedded systems.

  • 111.
    Izosimov, Viacheslav
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling and Optimization of Fault-Tolerant Embedded Systems2006Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Safety-critical applications have to function correctly even in presence of faults. This thesis deals with techniques for tolerating effects of transient and intermittent faults. Reexecution, software replication, and rollback recovery with checkpointing are used to provide the required level of fault tolerance. These techniques are considered in the context of distributed real-time systems with non-preemptive static cyclic scheduling.

    Safety-critical applications have strict time and cost constrains, which means that not only faults have to be tolerated but also the constraints should be satisfied. Hence, efficient system design approaches with consideration of fault tolerance are required.

    The thesis proposes several design optimization strategies and scheduling techniques that take fault tolerance into account. The design optimization tasks addressed include, among others, process mapping, fault tolerance policy assignment, and checkpoint distribution.

    Dedicated scheduling techniques and mapping optimization strategies are also proposed to handle customized transparency requirements associated with processes and messages. By providing fault containment, transparency can, potentially, improve testability and debugability of fault-tolerant applications.

    The efficiency of the proposed scheduling techniques and design optimization strategies is evaluated with extensive experiments conducted on a number of synthetic applications and a real-life example. The experimental results show that considering fault tolerance during system-level design optimization is essential when designing cost-effective fault-tolerant embedded systems.

  • 112.
    Izosimov, Viacheslav
    et al.
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Value-Based Scheduling of Distributed Fault-Tolerant Real-Time Systems with Soft and Hard Timing Constraints2010In: 8th IEEE Workshop on Embedded Systems for Real-TimeMultimedia, Scottsdale, AZ, USA, October 28-29, 2010., IEEE , 2010Conference paper (Refereed)
    Abstract [en]

    We present an approach for scheduling of fault tolerant embedded applications composed of soft and hard real time processes running on distributed embedded systems. The hard processes are critical and must always complete on time. A soft process can complete after its deadline and its completion time is associated with a value function that characterizes its contribution to the quality-of-service of the application. We propose a quasi-static scheduling algorithm to generate a tree of fault-tolerant distributed schedules that maximize the application's quality value and guarantee hard deadlines.

  • 113.
    Izosimov, Viacheslav
    et al.
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Lora, Michele
    Dept. of Computer Science, University of Verona, Italy.
    Pravadelli, Graziano
    Dept. of Computer Science, University of Verona, Italy.
    Fummi, Franco
    Dept. of Computer Science, University of Verona, Italy.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Di Guglielmo, Giuseppe
    VLSI Design and Education Center, University of Tokyo, Japan; CREST - Japan Science and Technology Agency, Japan.
    Fujita, Masahiro
    VLSI Design and Education Center, University of Tokyo, Japan; CREST - Japan Science and Technology Agency, Japan.
    Optimization of Assertion Placement in Time-Constrained Embedded Systems2011In: European Test Symposium (ETS2011), Trondheim, Norway, May 23-27, 2011., 2011Conference paper (Refereed)
    Abstract [en]

    We present an approach for optimization of assertion placement in time-constrained HW/SW modules for detection of errors due to transient and intermittent faults. During the design phases, these assertions have to be inserted into the executable code and, hence, will always be executed with the corresponding code branches. As the result, they can significantly increase execution time of a module, in particular, contributing to a much longer execution of the worst case, and cause deadline misses. Assertions have different characteristics such as tightness (or "local error coverage") and execution latency. Taking into account these properties can increase efficiency of assertion checks in time-constrained embedded HW/SW modules. We have developed a design optimization framework, which (1) identifies candidate locations for assertions, (2) associates a candidate assertion to each location, and (3) selects a set of assertions in terms of performance degradation and assertion tightness. Experimental results have shown the efficiency of the proposed techniques.

  • 114.
    Izosimov, Viacheslav
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Polian, I.
    Institute for Computer Science, Albert-Ludwigs-University of Freiburg, D-79110 Freiburg im Breisgau, Germany.
    Pop, P.
    Dept. of Informatics and Math. Modelling, Technical University of Denmark, DK-2800 Kongens Lyngby, Denmark.
    Ion Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Analysis and optimization of fault-tolerant embedded systems with hardened processors2009In: Proceedings -Design, Automation and Test in Europe, DATE, 2009, 682-687 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process re-execution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of re-executions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.

  • 115.
    Izosimov, Viacheslav
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Polian, Ilia
    Universität Freiburg.
    Pop, Paul
    Technische Universität Lyngby.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Analyse und Optimierung von fehlertoleranten Eingebetteten Systemen mit gehärteten Prozessoren2009In: Zuverlässigkeit und Entwurf (ZUE), Stuttgart, Germany, September 21-23, 2009., 2009Conference paper (Refereed)
    Abstract [de]

    Wir stellen einen Ansatz zur Entwurfsoptimierung von fehlertoleranten harten Echtzeitsystemen vor, der Hard-ware- und Software-Fehlertoleranztechniken kombiniert. Es wird zwischen selektiver Härtung in Hardware und Prozessneuausführungen in Software abgewogen, um benötigte Fehlertoleranz zu geringst möglichen Kosten zu erreichen. Die vorgestellten Entwurfsoptimierungsheuristiken legen die fehlertolerante Architektur und Prozess-zuordnung fest, so dass die Systemkosten minimiert, die Deadlines eingehalten und die Zuverlässigkeitsanforde-rungen erfüllt werden.

  • 116.
    Izosimov, Viacheslav
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems2005In: Design Automation and Test in Europe Conference DATE 2005,2005, Munich, Germany: IEEE Computer Society Press , 2005, 864- p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to the design optimization of fault-tolerant embedded systems for safety-critical applications. Processes are statically scheduled and communications are performed using the time-triggered protocol. We use process re-execution and replication for tolerating transient faults. Our design optimization approach decides the mapping of processes to processors and the assignment of fault-tolerant policies to processes such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several heuristics which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

  • 117.
    Izosimov, Viacheslav
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems2006In: 9th Euromicro Conference on Digital System Design,2006, Dubrovnik: IEEE Computer Society Press , 2006, 313- p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled. Process re-execution is used for recovering from multiple transient faults. We call process recovery transparent if it does not affect operation of other processes. Transparent recovery has the advantage of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules. However, it will introduce additional delays that can lead to violations of the timing constraints of the application. We propose an algorithm for the mapping of fault-tolerant applications with transparency. The algorithm decides a mapping of processes on computation nodes such that the application is schedulable and the transparency properties imposed by the designer are satisfied. The mapping algorithm is driven by a heuristic that is able to estimate the worst-case schedule length and indicate whether a certain mapping alternative is schedulable.

  • 118.
    Izosimov, Viacheslav
    et al.
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Pop, Paul
    Dept. of Informatics and Mathematical Modelling, Technical University of Denmark.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Scheduling and Optimization of Fault-Tolerant Embedded Systems with Transparency/Performance Trade-Offs2012In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 11, no 3, 61-95 p.Article in journal (Refereed)
    Abstract [en]

    In this paper, we propose a strategy for the synthesis of fault-tolerant schedules and for the mapping of fault tolerant applications. Our techniques handle transparency/performance trade-offs and use the fault-occurrence information to reduce the overhead due to fault tolerance. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. We propose a fine-grained transparent recovery, where the property of transparency can be selectively applied to processes and messages.Transparency hides the recovery actions in a selected part of the application so that they do not affect the schedule of other processes and messages. While leading to longer schedules, transparent recovery has the advantage of both improved debuggability and less memory needed to store the fault-tolerant schedules.

  • 119.
    Izosimov, Viacheslav
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Dept. of Informatics and Mathematical Modelling Technical University of Denmark.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints2008In: Design, Automation, and Test in Europe DATE 2008,2008, Munich, Germany: IEEE Computer Society Press , 2008, 915- p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to the synthesis of fault-tolerant schedules for embedded applications with soft and hard real-time constraints. We are interested to guarantee the deadlines for the hard processes even in the case of faults, while maximizing the overall utility. We use time/utility functions to capture the utility of soft processes. A single static schedule computed off-line is not fault tolerant and is pessimistic in terms of utility, while a purely online approach, which computes a new schedule every time a process fails or completes, incurs an unacceptable overhead. Thus, we use a quasi-static scheduling strategy, where a set of schedules is synthesized off-line and, at run time, the scheduler will select the right schedule based on the occurrence of faults and the actual execution times of processes. The proposed schedule synthesis heuristics have been evaluated using extensive experiments.

  • 120.
    Izosimov, Viacheslav
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication2006In: 3rd IEEE Intl. Workshop on Electronic Design, Test Applications DELTA,2006, Kuala Lumpur, Malaysia: IEEE Computer Society Press , 2006, 440- p.Conference paper (Refereed)
    Abstract [en]

    We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes are statically scheduled and communications are performed using the time-triggered protocol. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several synthesis algorithms which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.

  • 121.
    Izosimov, Viacheslav
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-offs for Distributed Embedded Systems2006In: Design Automation and Test in Europe Conference DATE 2006,2006, Munich, Germany: IEEE Computer Society Press , 2006, 706- p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach to the scheduling of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. If process recovery is performed such that the operation of other processes is not affected, we call it transparent recovery. Although transparent recovery has the advantages of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules, it will introduce delays that can violate the timing constraints of the application. We propose a novel algorithm for the synthesis of fault-tolerant schedules that can handle the transparency/performance trade-offs imposed by the designer, and makes use of the fault-occurrence information to reduce the overhead due to fault tolerance. We model the application as a conditional process graph, where the fault occurrence information is represented as conditional edges and the transparent recovery is captured using synchronization nodes.

  • 122.
    Izosimov, Viacheslav
    et al.
    Embedded Intelligent Solutions (EIS) By Semcon AB, Linköping, Sweden.
    Pop, Paul
    Dept. of Informatics and Mathematical Modelling, Technical University of Denmark.
    Eles, Petru Ion
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Synthesis of Flexible Fault-Tolerant Schedules for Embedded Systems with Soft and Hard Timing Constraints2010In: Design and Test Technology for Dependable Systems-on-chip / [ed] Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, Information Science Publishing , 2010, 1, 578- p.Chapter in book (Other academic)
    Abstract [en]

    Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.

    Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined "classical" design and test topics and solutions for IC test technology and fault-tolerant systems.

  • 123.
    Izosimov, Viacheslav
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Pop, Paul
    Dept. Informatics and Mathematical Modelling Technical University of Denmark.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems2008In: 11th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN DSD 2008,2008, Parma, Italy: IEEE Computer Society Press , 2008, 71- p.Conference paper (Refereed)
    Abstract [en]

    In this paper we present an approach for scheduling with preemption for fault-tolerant embedded systems composed of soft and hard real-time processes. We are interested to maximize the overall utility for average, most likely to happen, scenarios and to guarantee the deadlines for the hard processes in the worst case scenarios. In many applications, the worst-case execution times of processes can be much longer than their average execution times. Thus, designs for the worst-case can be overly pessimistic, i.e., result in low overall utility. We propose preemption of process executions as a method to generate flexible schedules that maximize the overall utility for the average case while guarantee timing constraints in the worst case. Our scheduling algorithms determine off-line when to preempt and when to resurrect processes. The experimental results show the superiority of our new scheduling approach compared to approaches without preemption.

  • 124.
    Jervan, Gert
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems2002Licentiate thesis, monograph (Other academic)
    Abstract [en]

    The technological development is enabling production of increasingly complex electronic systems. All those systems must be verified and tested to guarantee correct behavior. As the complexity grows, testing is becoming one of the most significant factors that contribute to the final product cost. The established low-level methods for hardware testing are not any more sufficient and more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. This thesis reports on one such work that deals in particular with high-level test generation and design for testability techniques.

    The contribution of this thesis is twofold. First, we investigate the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation architecture. We have developed for this purpose a novel hierarchical test generation algorithm and demonstrated the usefulness of the generated tests not only for manufacturing test but also for testability analysis.

    The second part of the thesis concentrates on design for testability. As testing of modern complex electronic systems is a very expensive procedure, special structures for simplifying this process can be inserted into the system during the design phase. We have proposed for this purpose a novel hybrid built-in self-test architecture, which makes use of both pseudorandom and deterministic test patterns, and is appropriate for modern system-on-chip designs. We have also developed methods for optimizing hybrid built-in self-test solutions and demonstrated the feasibility and efficiency of the proposed technique.

  • 125.
    Jervan, Gert
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems2005Doctoral thesis, monograph (Other academic)
    Abstract [en]

    The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing methods, most of which are based on low-level representations of the hardware circuits. Therefore, more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. At the same time, the automatic test equipment based solutions have failed to deliver the required test quality. As a result, alternative testing methods have been studied, which has led to the development of built-in self-test (BIST) techniques.

    In this thesis, we present a novel hybrid BIST technique that addresses several areas where classical BIST methods have shortcomings. The technique makes use of both pseudorandom and deterministic testing methods, and is devised in particular for testing modern systems-on-chip. One of the main contributions of this thesis is a set of optimization methods to reduce the hybrid test cost while not sacrificing test quality. We have devel oped several optimization algorithms for different hybrid BIST architectures and design constraints. In addition, we have developed hybrid BIST scheduling methods for an abort-on-first-fail strategy, and proposed a method for energy reduction for hybrid BIST.

    Devising an efficient BIST approach requires different design modifications, such as insertion of scan paths as well as test pattern generators and signature analyzers. These modifications require careful testability analysis of the original design. In the latter part of this thesis, we propose a novel hierarchical test generation algorithm that can be used not only for manufacturing tests but also for testability analysis. We have also investigated the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation.

    Experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodologies and techniques.

  • 126.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, R.
    Department of Computer Engineering, Tallinn University of Technology, Estonia.
    Jenihhin, M.
    Department of Computer Engineering, Tallinn University of Technology, Estonia.
    Test time minimization for hybrid BIST of core-based systems2006In: Journal of Computer Science and Technology, ISSN 1000-9000, Vol. 21, no 6, 907-912 p.Article in journal (Refereed)
    Abstract [en]

    This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions. © Springer Science + Business Media, Inc. 2006.

  • 127.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Jenihhin, Maksim
    Dept. Computer Engineering Tallinn University of Technology.
    Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture2003In: 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03,2003, Cambridge, MA, USA: IEEE Computer Society Press , 2003, 225- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. We propose a methodology to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.

  • 128.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Jenihhin, Maksim
    Dept. Computer Engineering Tallinn University of Technology.
    Test Time Minimization for Hybrid BIST of Core-Based Systems2003In: 12th IEEE Asian Test Symposium ATS03,2003, Xian, China: IEEE Computer Society Press , 2003, 318- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find a near optimal solutions.

  • 129.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Goloubeva, Olga
    Dipartimento di Automatica e Informatica Politecnico di Torino.
    Reorda, Matteo Sonza
    Dipartimento di Automatica e Informatica Politecnico di Torino.
    Violante, Massimo
    Dipartimento di Automatica e Informatica Politecnico di Torino.
    High-Level and Hierarchical Test Sequence Generation2002In: IEEE International Workshop on High Level Design Validation and Test,2002, Cannes, France: IEEE Computer Society Press , 2002, 169- p.Conference paper (Refereed)
    Abstract [en]

    Test generation at the gate-level produces high-quality tests but is computationally expensive in the case of large systems. Recently, several research efforts have investigated the possibility of devising test generation methods and tools to work on high-level descriptions. The goal of these methods is to provide the designers with testability information and test sequences in the early design stages. The cost for generating test sequences in the high abstraction levels is often lower than that for generating test sequences at the gate-level, with comparable or even higher fault coverage. This paper first analyses several high-level fault models in order to select the most suitable one for estimating the testability of circuits by reasoning on their behavioral descriptions and for guiding the test generation process at the behavioral level. We assess then the effectiveness of high-level test generation with a simple ATPG algorithm, and present a novel high-level hierarchical test generation approach to improve the results obtained by a pure high-level test generator.

  • 130.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Reorda, Matteo Sonza
    Dipartimento di Automatica e Informatica Politecnico di Torino.
    Violante, Massimo
    Dipartimento di Automatica e Informatica Politecnico di Torino.
    Report on benchmark identification and planning of experiments to be performed2002Report (Other academic)
    Abstract [en]

    The document describes the benchmarks we have identified as test cases to be used during the COTEST project. Being the project focused both on the high-level generation of suitable test/validation vectors and on the high-level insertion of design for testability structures, we identified benchmarks of different characteristics and complexity. The document also outlines the experiments that we intend to perform during the project.

  • 131.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Test Cost Minimization for Hybrid BIST2000In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT2000,2000, Yamanashi, Japan: IEEE Computer Society Press , 2000, 283-291 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored deterministic test patterns. A method is proposed to find the optimal balance between pseudorandom and stored test patterns to perform core test with minimum time and memory, without losing test quality. Two accurate algorithms are proposed for finding the optimal time-moment to stop pseudorandom test generation and to apply stored patterns. To speed up the optimization procedure, a method is proposed for fast estimation of the expected cost for different possible solutions with very low computational cost. Experimental results have demonstrated the feasibility of the proposed approach for cost optimization of hybrid BIST.

  • 132.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Korelina, Olga
    Dept. Computer Engineering Tallinn University of Technology.
    An Improved Estimation Methodology for Hybrid BIST Cost Calculation2004In: IEEE Norchip 2004,2004, 2004, 297-300 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents an improved estimation methodology for hybrid BIST cost calculation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is largely determined by the ratio of those test patterns in the final test set. Unfortunately exact algorithms for finding the test sets are computationally very expensive. Therefore in this paper we propose an improved estimation methodology for fast calculation of the hybrid test set. The methodology is based on real fault simulation results and experimental results have shown that the method is more accurate than the statistical method proposed earlier.

  • 133.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Korelina, Olga
    Dept. Computer Engineering Tallinn University of Technology.
    An Improved Estimation Technique for Hybrid BIST Test Set Generation2005In: IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems DDECS,2005, Sopron, Hungary: IEEE Computer Society Press , 2005, 182- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents an improved estimation technique for hybrid BIST test set generation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is determined by the ratio of those test patterns in the final test set. Unfortunately, exact algorithms for finding the optimal test sets are computationally very expensive. And several heuristics have been developed to address this problem based on estimation methods. In this paper we propose an improved estimation technique for fast generation of the hybrid test set. The technique is based on fault simulation results, and experiments have shown that the proposed technique is more accurate than the estimation methods proposed earlier.

  • 134.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Kruus, Helena
    Dept. Computer Engineering Tallinn University of Technology.
    A Hybrid BIST Architecture and its Optimization for SoC Testing2002In: IEEE 2002 3rd International Symposium on Quality Electronic Design ISQED02,2002, San Jose, California, USA: IEEE Computer Society Press , 2002, 273- p.Conference paper (Refereed)
    Abstract [en]

    This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns with stored deterministic test patterns to perform core test with minimum time and memory, without losing test quality. We propose two algorithms to calculate the cost of the test process. To speed up the optimization procedure, a Tabu search based method is employed for finding the global cost minimum. Experimental results have demonstrated the feasibility and efficiency of the approach and the significant decreases in overall test cost.

  • 135.
    Jervan, Gert
    et al.
    Dept. of Computer Engineering Tallinn University of Technology.
    Ubar, Raimund
    Dept. of Computer Engineering Tallinn University of Technology.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Hybrid BIST Methodology for Testing Core-Based Systems2006In: Proceedings of the Estonian Academy of Sciences. Engineering, ISSN 1406-0175, Vol. 12, no 3-2, 300-322 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes a hybrid BIST methodology for testing systems-on-chip. In our hybrid BIST approach a test set is assembled, for each core, from pseudorandom test patterns that are generated on-line, and deterministic test patterns that are generated off-line and stored in the system. The deterministic test set is specially designed to shorten the pseudorandom test cycle and to target random resistant faults. To support such a test strategy, we have developed several hybrid BIST architectures that target different test scenarios. As the test lengths of the two test sequences is one of the important parameters in the final test cost, we have to find the most efficient combination of those two test sets without sacrificing the test quality. We describe methods for finding the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed up the calculation process. Experimental results have shown the efficiency of the algorithms to find a near-optimal solutions.

  • 136.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, Raimund
    Dep. of Computer Engineering Tallinn University of Technology.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    An Approach to System-Level DFT2005In: System-level Test and Validation of Hardware/Software Systems / [ed] M. Sonza Reorda, Z. Peng, M. Violante, Berlin: Springer Berlin Heidelberg , 2005, 121-149 p.Chapter in book (Other academic)
    Abstract [en]

    New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.

    As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue.

    System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:

    • modeling of bugs and defects;

    • stimulus generation for validation and test purposes (including timing errors;

    • design for testability.

    For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.

  • 137.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, Raimund
    Dept. of Computer Engineering Tallinn University of Technology.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Test Generation: A Hierarchical Approach2005In: System-level Test and Validation of Hardware/Software Systems / [ed] M. Sonza Reorda, Z. Peng, M. Violante, Berlin: Springer Berlin Heidelberg , 2005, 67-81 p.Chapter in book (Other academic)
    Abstract [en]

    New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue. This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing errors; design for testability.

  • 138.
    Jervan, Gert
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Shchenova, Tatjana
    Dept. Computer Engineering Tallinn University of Technology.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment2005In: 10th IEEE European Test Symposium ETS´05,2005, Tallinn, Estonia: IEEE Computer Society Press , 2005Conference paper (Refereed)
    Abstract [en]

    This paper addresses the energy minimization problem for system-on-chip testing. We assume a hybrid BIST test architecture where a combination of deterministic and pseudorandom test sequences is used. The objective of our proposed technique is to find the best ratio of these sequences so that the total energy is minimized and the memory requirements for the deterministic test set are met without sacrificing test quality. We propose two different heuristic algorithms and a fast estimation method that enables considerable reduction of the computation time. Experimental results have shown the efficiency of the approach for finding reduced energy solutions with low computational overhead.

  • 139.
    Jervan, Gert
    et al.
    Dept. of Computer Engineering Tallinn University of Technology.
    Ubar, Raimund
    Dept. of Computer Engineering Tallinn University of Technology.
    Shchenova, Tatjana
    Dept. of Computer Engineering Tallinn University of Technology.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Hybrid BIST Energy Minimisation Technique for System-on-Chip Testing2006In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 153, no 4, 208-216 p.Article in journal (Refereed)
    Abstract [en]

    The energy minimisation problem for system-on-chip testing is addressed. A hybrid built-in self-test architecture is assumed where a combination of deterministic and pseudorandom test sequences are used. The objective of the proposed technique is to find the best ratio of these sequences so that the total energy is minimised and the memory requirements for the deterministic test set are met without sacrificing test quality. Unfortunately, exact algorithms for finding the best solutions to the above problem are computationally very expensive. Therefore, an estimation methodology for fast calculation of the hybrid test set and two different heuristic algorithms for energy minimisation were proposed. Experimental results have shown the efficiency of the proposed approach for finding reduced energy solutions with low computational overhead.

  • 140.
    Jiang, Ke
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Batina, Lejla
    Institute for Computing and Information Sciences, Radboud University Nijmegen, The Netherlands.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks2014In: IEEE Computer Society Annual Symposium on VLSI, IEEE Computer Society, 2014, 450-455 p.Conference paper (Refereed)
    Abstract [en]

    Embedded systems (ESs) have been a prominent solution for enhancing system performance and reliability in recent years. ESs that are required to ensure functional correctness under timing constraints are referred to as real-time embedded systems (RTESs). With the emerging trend of utilizing RTESs in safety and reliability critical areas, security of RTESs, especially confidentiality of the communication, becomes of great importance. More recently, side-channel attacks (SCAs) posed serious threats to confidentiality protection mechanisms, namely, cryptographic algorithms. In this work, we present the first analytical framework for quantifying the influence of real-time scheduling policies on the robustness of secret keys against differential power analysis (DPA) attacks, one of the most popular type of SCAs. We validated the proposed concept on two representative scheduling algorithms, earliest deadline first scheduling (EDF) and rate-monotonic scheduling (RMS), via extensive experiments.

  • 141.
    Jiang, Ke
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    A Design Framework for Dynamic Embedded Systems with Security Constraints2013In: The 12th Swedish System-on-Chip Conference (SSoCC 2013), Ystad, Sweden, May 6-7, 2013 (not reviewed, not printed)., 2013Conference paper (Other academic)
  • 142.
    Jiang, Ke
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints2012In: Design Automation and Test in Europe (DATE12), Dresden, Germany, March 12-16, 2012., IEEE , 2012, 947-952 p.Conference paper (Refereed)
    Abstract [en]

    In this paper we consider distributed real-time embedded systems in which confidentiality of the internal communication is critical. We present an approach to efficiently implement cryptographic algorithms by using hardware/software co-design techniques. The objective is to find the minimal hardware overhead and corresponding process mapping for encryption and decryption tasks of the system, so that the confidentiality requirements for the messages transmitted over the internal communication bus are fulfilled, and time constraints are satisfied. Towards this, we formulate the optimization problems using Constraint Logic Programming (CLP), which returns optimal solutions. However, CLP executions are computationally expensive and, hence, efficient heuristics are proposed as an alternative. Extensive experiments demonstrate the efficiency of the proposed heuristic approaches.

  • 143.
    Jiang, Ke
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Optimization of Message Encryption for Distributed Embedded Systems with Real-Time Constraints2011In: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011., IEEE, 2011Conference paper (Refereed)
    Abstract [en]

    In this paper we consider distributed embedded systems in which privacyor confidentiality of the internal communication is critical, andpresent an approach to optimizing cryptographic algorithms under stricttiming constraints. We have developed a technique to search for the bestsystem-affordable cryptographic protection for the messages transmittedover the internal communication bus. Towards this, we formulate theoptimization technique in Constraint Logic Programming (CLP), whichreturns optimal results. However, CLP executions are computationallyexpensive and hence, we propose an efficient heuristic as analternative. Extensive experiments demonstrate the efficiency of theproposed heuristic approach.

  • 144.
    Jiang, Ke
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Performance Comparison of Simulated Annealing and Tabu Search on Block Cipher Optimization in Distributed Embedded Systems2011In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011, 2011Conference paper (Other academic)
    Abstract [en]

    In this paper, we consider distributed embedded systems in which privacy or confidentiality of the internal communication is critical, and present an approach to optimize cryptographic algorithms under strict timing constraints. We have developed a technique searching for the best system-affordable cryptographic protection for the messages transmitted over the internal communication bus. On account of the complexity of the problem, finding the optimal solution is only feasible for very small systems. Therefore, we formulate the technique in two efficient metaheuristics, and study their performance from extensive experiments.

  • 145.
    Jiang, Ke
    et al.
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Lifa, Adrian Alin
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Eles, Petru
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Peng, Zebo
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Jiang, Wei
    University of Electronic Science and Technology of China, Chengdu.
    Energy-Aware Design of Secure Multi-Mode Real-Time Embedded Systems with FPGA Co-Processors2013In: Proceedings of the 21st International conference on Real-Time Networks and Systems / [ed] Michel Auguin, Robert de Simone, Robert Davis, Emmanuel Grolleau, New York: Association for Computing Machinery (ACM), 2013, 109-118 p.Conference paper (Refereed)
    Abstract [en]

    We approach the emerging area of energy efficient, secure real-time embedded systems design. Many modern embedded systems have to fulfill strict security constraints and are often required to meet stringent deadlines in different operation modes, where the number and nature of active tasks vary (dynamic task sets). In this context, the use of dynamic voltage/frequency scaling (DVFS) techniques and onboard field-programmable gate array (FPGA) co-processors offer new dimensions for energy savings and performance enhancement. We propose a novel design framework that provides the best security protection consuming the minimal energy for all operation modes of a system. Extensive experiments demonstrate the efficiency of our techniques.

  • 146.
    Jiang, Wei
    et al.
    School of Computer Science and Engineering, University of Electronic Science and Technology of China, China School of Information and Software Engineering, University of Electronic Science and Technology of China, China .
    Jiang, Ke
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
    Zhang, Xia
    School of Information and Software Engineering, University of Electronic Science and Technology of China, China .
    Ma, Yue
    Department of Computer Science and Engineering, University of Notre Dame, United States .
    Energy Aware Real-Time Scheduling Policy with Guaranteed Security Protection2014In: 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), IEEE conference proceedings, 2014, 317-322 p.Conference paper (Refereed)
    Abstract [en]

    In this work, we address the emerging scheduling problem existed in the design of secure and energy-efficient real-time embedded systems. The objective is to minimize the energy consumption subject to security and schedulability constraints. Due to the complexity of the problem, we propose a dynamic programming based approximation approach to find the near-optimal solutions with respect to predefined security constraint. The proposed technique has polynomial time complexity which is about half of traditional approximation approaches. The efficiency of our algorithm is validated by extensive experiments.

  • 147.
    Jigorea, Razvan
    et al.
    IDA Linköpings Universitet.
    Manolache, Sorin
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Eles, Petru Ion
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Modelling of Real-Time Embedded Systems in an Object-Oriented Design Environment with UML2000In: 3rd IEEE International Symposium on Object-oriented Real-time distributed Computing ISORC 2000,2000, Newport Beach, California: IEEE Computer Society Press , 2000, 210-213 p.Conference paper (Refereed)
    Abstract [en]

    This paper explores aspects concerning system-level specification, modelling and simulation of real-time embedded systems. By means of case studies, we investigate how object-oriented methodologies, and in particular UML, support the modelling of industrial scale real-time systems, and how different architectures can be explored by model simulation. We are mainly interested in the problem of system specification as it appears from the prospect of the whole design process. The discussion is illustrated by a large system model from the telecommunications area, the GSM base transceiver station.

  • 148.
    Jutman, Artur
    et al.
    Dept. Computer Engineering Tallinn University of Technology.
    Ubar, Raimund
    Dept. Computer Engineering Tallinn University of Technology.
    Peng, Zebo
    Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
    Improving the Efficiency of Timing Simulation of Digital Circuits2001In: Design, Automation and Test in Europe DATE Conference,2001, Munich, Germany: IEEE Computer Society Press , 2001, 460- p.Conference paper (Refereed)
    Abstract [en]

    Meeting timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, a new approach and the implementation of several algorithms to speed up gate-level timing simulation are proposed where, instead of gate delays, path delays for tree-like subcircuits (macros) are used. Therefore timing waveforms are calculated not for all internal nodes of the gate-level circuit but only for outputs of macros. The macros are represented by structurally synthesized binary decision diagrams (SSBDD) which enable a fast computation of delays for macros. The new approach to speed up the timing simulation is supported by encouraging experimental results.

  • 149.
    Karlsson, Daniel
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Towards Formal Verification in a Component-based Reuse Methodology2003Licentiate thesis, monograph (Other academic)
    Abstract [en]

    Embedded systems are becoming increasingly common in our everyday lives. As techonology progresses, these systems become more and more complex. Designers handle this increasing complexity by reusing existing components (Intellectual Property blocks). At the same time, the systems must still fulfill strict requirements on reliability and correctness.

    This thesis proposes a formal verification methodology which smoothly integrates with component-based system-level design using a divide and conquer approach. The methodology assumes that the system consists of several reusable components. Each of these components are already formally verified by their designers and are considered correct given that the environment satisfies certain properties imposed by the component. What remains to be verified is the glue logic inserted between the components. Each such glue logic is verified one at a time using model checking techniques.

    The verification methodology as well as the underlying theoretical framework and algorithms are presented in the thesis.

    Experimental results have shown the efficiency of the proposed methodology and demonstrated that it is feasible to apply it on real-life examples.

  • 150.
    Karlsson, Daniel
    Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
    Verification of Component-based Embedded System Designs2006Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex. Designers handle this increasing complexity by reusing existing components. At the same time, the systems must fulfill strict functional and non-functional requirements.

    This thesis presents novel and efficient techniques for the verification of component-based embedded system designs. As a common basis, these techniques have been developed using a Petri net based modelling approach, called PRES+.

    Two complementary problems are addressed: component verification and integration verification. With component verification the providers verify their components so that they function correctly if given inputs conforming to the assumptions imposed by the components on their environment.

    Two techniques for component verification are proposed in the thesis. The first technique enables formal verification of SystemC designs by translating them into the PRES+ representation. The second technique involves a simulation based approach into which formal methods are injected to boost verification efficiency.

    Provided that each individual component is verified and is guaranteed to function correctly, the components are interconnected to form a complete system. What remains to be verified is the interface logic, also called glue logic, and the interaction between components.

    Each glue logic and interface cannot be verified in isolation. It must be put into the context in which it is supposed to work. An appropriate environment must thus be derived from the components to which the glue logic is connected. This environment must capture the essential properties of the whole system with respect to the properties being verified. In this way, both the glue logic and the interaction of components through the glue logic are verified. The thesis presents algorithms for automatically creating such environments as well as the underlying theoretical framework and a step-by-step roadmap on how to apply these algorithms.

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