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  • 1.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zahedinejad, Mohammad
    Department of Physics, University of Gothenburg.
    Åkerman, Johan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics. Department of Physics, University of Gothenburg.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators2019In: IEEE transactions on magnetics, ISSN 0018-9464, E-ISSN 1941-0069, Vol. 55, no 10, article id 4003808Article in journal (Refereed)
    Abstract [en]

    Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

  • 2.
    Chaourani, Panagiotis
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Onet, Raul
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Enabling Area Efficient RF ICs through Monolithic 3D Integration2017In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 610-613, article id 7927059Conference paper (Refereed)
    Abstract [en]

    The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

  • 3.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines2019In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 2, p. 468-480Article in journal (Refereed)
    Abstract [en]

    Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

  • 4.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Stathis, Dimitrios
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors2018In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Conference paper (Refereed)
    Abstract [en]

    The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

  • 5.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dumas, R. K.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Muduli, P. K.
    Houshang, A.
    Awad, A. A.
    Dürrenfeld, P.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. Univ Gothenburg, Sweden.
    Spin-Torque and Spin-Hall Nano-Oscillators2016In: Proceedings of the IEEE, ISSN 0018-9219, E-ISSN 1558-2256, Vol. 104, no 10, p. 1919-1945, article id 7505988Article in journal (Refereed)
    Abstract [en]

    This paper reviews the state of the art in spin-torque and spin-Hall-effect-driven nano-oscillators. After a brief introduction to the underlying physics, the authors discuss different implementations of these oscillators, their functional properties in terms of frequency range, output power, phase noise, and modulation rates, and their inherent propensity for mutual synchronization. Finally, the potential for these oscillators in a wide range of applications, from microwave signal sources and detectors to neuromorphic computation elements, is discussed together with the specific electronic circuitry that has so far been designed to harness this potential.

  • 6.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dumas, Randy K.
    Department of Physics, University of Gothenburg.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Muduli, Pranaba K.
    Department of Physics, University of Gothenburg and Department of Physics, Indian Institute of Technology.
    Houshang, Afshin
    Department of Physics, University of Gothenburg.
    Awad, Ahmad A.
    Department of Physics, University of Gothenburg.
    Dürrenfeld, Philip
    Department of Physics, University of Gothenburg.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. Department of Physics, University of Gothenburg and Nanosc AB.
    Spin-Torque and Spin-Hall Nano-OscillatorsIn: Proceedings of the IEEE, ISSN 0018-9219, E-ISSN 1558-2256Article in journal (Refereed)
    Abstract [en]

    This paper reviews the state of the art in spin-torque and spin Hall effect driven nano-oscillators. After a brief introduction to the underlying physics, the authors discuss different implementations of these oscillators, their functional properties in terms of frequency range, output power, phase noise, and modulation rates, and their inherent propensity for mutual synchronization. Finally, the potential for these oscillators in a wide range of applications, from microwave signal sources and detectors to neuromorphic computation elements, is discussed together with the specific electronic circuitry that has so far been designed to harness this potential.

  • 7.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dürrenfeld, P.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. University of Gothenburg, Sweden.
    A highly tunable microwave oscillator based on MTJ STO technology2014In: Microwave and optical technology letters (Print), ISSN 0895-2477, E-ISSN 1098-2760, Vol. 56, no 9, p. 2092-2095Article in journal (Refereed)
    Abstract [en]

    This article presents a fully ESD-protected, highly tunable microwave oscillator based on magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology. The oscillator consists of a compact MTJ STO and a 65 nm CMOS wideband amplifier, which amplifies the RF signal of the MTJ STO to a level that can be used to drive a PLL. The (MTJ STO+amplifier IC) pair shows a measured quality factor (Q) of 170 and a wide tunability range from 3 to 7 GHz, which demonstrate its potential to be used as a microwave oscillator in multiband, multistandard radios.

  • 8.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I: Analytical Model of the MTJ STO2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1037-1044Article in journal (Refereed)
    Abstract [en]

    Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STO's characteristics, while enabling system-and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations.

  • 9.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part II: Verilog-A Model Implementation2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1045-1051Article in journal (Refereed)
    Abstract [en]

    The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various applications. In Part I of this paper, an analytical model based on the macrospin approximation has been introduced and verified by comparing it with the measurements of three different MTJ STOs. In Part II, the full Verilog-A implementation of the proposed model is presented. To achieve a reliable model, an approach to reproducing the phase noise generated by the MTJ STO has been proposed and successfully employed. The implemented model yields a time domain signal, which retains the characteristics of operating frequency, linewidth, oscillation amplitude, and DC operating point, with respect to the magnetic field and applied DC current. The Verilog-A implementation is verified against the analytical model, providing equivalent device characteristics for the full range of biasing conditions. Furthermore, a system that includes an MTJ STO and CMOS RF circuits is simulated to validate the proposed model for system-and circuit-level designs. The simulation results demonstrate that the proposed model opens the possibility to explore STO technology in a wide range of applications.

  • 10.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Redjai Sani, Sohrab
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of GMR-based spin torque oscillators and CMOS circuitry2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 111, p. 91-99Article in journal (Refereed)
    Abstract [en]

    This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm2. The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies.

  • 11.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Alarcon, Eduard
    UPC Universitat Politecnica de Catalunya Barcelona, Spain.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 2 GHz - 8.7 GHz Wideband Balun-LNA with Noise Cancellation and Gain Boosting2012In: PRIME 2012: Proceedings of the 8th Coference on Ph.D. Research in Microelectronics and Electronics, 2012, IEEE conference proceedings, 2012, p. 59-62Conference paper (Refereed)
    Abstract [en]

    A wideband Balun-LNA covering the operation frequency range of magnetic tunnel junction Spin Torque Oscillator is presented. The LNA is a combination of common-source and cross-coupled common-gate stages, which provides wideband matching and noise cancellation, as well as gain boosting. The internal feedback introduced by the cross-coupling allows an additional degree of freedom to select transistor sizes and bias by decoupling the impedance matching, noise, and gain imbalance trade-offs which are present in similar topologies. Two LNAs using the proposed technique are designed in 65nm CMOS. The LNAs have a simulated bandwidth of  2 GHz - 8.7 GHz, gain of 16 dB, IIP3 of -3.5 dBm,  and NF < 3.8 dB while consuming 3.72 mW from a 1.2 V power supply.

  • 12.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wideband Amplifier Design for Magnetic Tunnel JunctionBased Spin Torque Oscillators2012In: Proc. of GigaHertz Symposium 2012, 2012Conference paper (Refereed)
    Abstract [en]

    Spin torque oscillator (STO) is a novel current-control-oscillator (CCO), based on two spintronic effects: spin momentum transfer torque and magneto-resistance (MR). It features large tunability, miniature size, high integration level, high quality factor, high operation frequency, etc., which makes it a promising technology for microwave and radar applications. However, the STO is still an immature technology, which requires intensive research for improving the spectrum purity and the output power performance [1]. This paper proposes a wideband amplifier targeting magnetic tunnel junction (MTJ) type of STO device, which compensates the low output power of the STO.

        The MTJ STO devices can cover a large part of ultra-wideband (UWB) from 3 - 8 GHz and provide an output power from -60 dBm to -40 dBm by tuning the bias DC current and the magnetic field [2][3]. One important and potential application of STO device is a local oscillator (LO) in an RF transceiver. To achieve this task, the amplifier requires a gain of 45 - 65 dB. In addition, the source impedance of different MTJ STO devices varies from a dozen to several hundred Ohms, which makes the amplifier design challenging. An universal amplifier, which fulfills the extracted design requirements, is proposed. It is composed of two types of Balun-LNAs depending on the MR of STO devices as the input stages, a broadband limiting amplifier chain and an output buffer. A combination of a common source (CS) stage and a cross-coupled common gate (CG) stage is employed for the input Balun-LNA in the low impedance case while a cascoded CS stage is used in the high impedance case. The output of both LNAs is connected to a limiting amplifier chain, which provides enough voltage gain. An output buffer is used as the output stage to convert the balanced output to single-ended output and to match the output impedance to 50 Ohms.

        The proposed wideband amplifier for MTJ STO is implemented in a 65nm CMOS process with   1.2 V supply. In the band of interest, it exhibits 55 dB gain with a maximum noise figure (NF) of    4.5 dB in the small MR case, and a 59 dB gain with a maximum NF of 3 dB in the large MR case. Besides the low noise performance and the high gain, the simulation results of the proposed amplifier also show that it has low power consumption and moderate impedance matching in the frequency range of 3 - 8 GHz, which is suitable for MTJ STO applications.

  • 13.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    An Inductorless Wideband Balun-LNA for Spin Torque Oscillator-based Field Sensing2014In: Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on, IEEE conference proceedings, 2014, p. 36-39Conference paper (Refereed)
    Abstract [en]

    This paper presents a wideband inductorless Balun-LNA targeting spin torque oscillator-based magnetic field sensing applications. The LNA consistsof a CS stage combined with a cross-coupled CG stage, which offers wideband matching, noise/distortion cancellation and gain boosting, simultaneously. The Balun-LNA is implemented in a 65 nm CMOS technology, and it is fully ESD-protected and packaged. Measurement results show a bandwidth of 2 GHz - 7 GHz, a voltage gain of 20 dB, an IIP3 of +2 dBm, and a maximum NF of 5 dB. The LNA consumes 3.84 mW from a 1.2 V power supply and occupies a total silicon area of 0.0044 mm2. The measurement results demonstrate that the proposed Balun-LNA is highly suitable for the STO-based field sensing applications.

  • 14.
    Garcia, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Low-Power CT Incremental 3rd Order Sigma Delta ADC for Biosensor Applications2013In: IEEE Transactions on Circuits and Systems. Part 1: Regular Papers, ISSN 1549-8328, Vol. 60, no 1, p. 25-36Article in journal (Refereed)
    Abstract [en]

    This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15- mCMOStechnology,while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator’s power dissipation is 96 W from a 1.6 V power supply. This translates into the best figure-ofmerit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts.

  • 15.
    Garcia, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    On Continuous-Time Incremental Sigma Delta ADCs With Extended Range2013In: IEEE Transactions on Instrumentation and Measurement, ISSN 0018-9456, E-ISSN 1557-9662, Vol. 62, no 1, p. 60-70Article in journal (Refereed)
    Abstract [en]

    In this paper, the use of continuous-time implementation in extended-range (ER) incremental sigma-delta analog-to-digital converters is analyzed in order to explore a possible solution to low-power multichannel applications. The operation principle, possible loop filter topologies, and critical issues are considered using a general approach. It is demonstrated that, in order to fully benefit from ER, careful attention has to be paid to the analog-digital transfer function mismatches. A third-order single-bit topology validates the theoretical analysis. Its performance is evaluated while the impact of key circuit nonidealities is quantified through behavioral-level simulations. It is shown that, by applying analog-digital mismatch compensation in the digital domain, it is possible to relax the amplifiers' finite gain-bandwidth product and finite dc gain requirements, thus allowing a power-conscious alternative.

  • 16.
    Garcia, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    An Extended-Range Incremental CT Sigma Delta ADC with Optimized Digital Filter2012In: 2012 13th International Symposium On Quality Electronic Design (ISQED), IEEE , 2012, p. 179-184Conference paper (Refereed)
    Abstract [en]

    Extended range approach has been employed in discrete-time incremental sigma-delta analog-to-digital converters to reduce the number of cycles per conversion and therefore the power dissipation. In this work, extended range is combined with continuous-time filter implementation so as to reduce the integrators gain-bandwidth product requirement. The proposed architecture and mathematical analysis are presented using a 3rd order single-loop single-bit sigma-delta modulator as proof-of-concept. In order to overcome the analog-digital transfer functions mismatches, an appropriate digital filter is designed using optimization tools. Behavioral simulations show that the proposed architecture with an optimized filter achieves 13.8 bits resolution with a 4 kSamples/sec sampling rate to comply with a high-resolution biomedical application.

  • 17.
    Garcia, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Built-in self calibration for process variation in single-loop continuous-time sigma-delta modulators2010In: 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010, IEEE conference proceedings, 2010, p. 1136-1139Conference paper (Refereed)
    Abstract [en]

    A novel built-in self calibration technique for single-loop continuous-time sigma-delta modulators is proposed. Using out-of-band test signal injection and digital cancellation, this technique provides an area efficient, highly digital calibration structure to counteract gain variations in the loop filter. The calibration methodology and mathematical analysis are presented using a 2 nd order multibit sigma-delta modulator as a proof of concept. The effect of the finite gain-bandwidth of amplifiers is included when evaluating the calibration method. The proposed technique is validated through corner simulations using behavioral models and it shows that degradation in the signal-to-noise-plus-distortion ratio can be counteracted.

  • 18.
    García, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-order continuous-time incremental ΣΔ ADC for multi-channel applications2011In: IEEE International Symposium of Circuits and Systems, ISCAS 2011, IEEE conference proceedings, 2011, p. 1121-1124Conference paper (Refereed)
    Abstract [en]

    A novel high-order single-loop incremental sigma-delta ADC for multi-channel applications is proposed. High-order continuous-time architectures are explored using a 3rd order single-bit modulator as a test-case. The performance of the proposed architecture, taking into account critical non-idealities, is analyzed and its advantages and issues are discussed. Behavioral simulations show a key advantage regarding the integrators' gain-bandwidth requirement of the proposed ADC compared to discrete-time counterparts. This advantage leads to possible low power solutions for multi-channel applications.

  • 19.
    García, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Multibit continuous-time ΣΔ modulator with reduced number of feedback levels2010In: 6th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2010, IEEE conference proceedings, 2010, p. 1-4Conference paper (Refereed)
    Abstract [en]

    A multibit continuous-time sigma-delta modulator, where truncation error shaping and cancellation techniques are applied, is proposed. These techniques are proposed in order to reduce the number of levels in the feedback digital-to-analogue converters and then eliminate the use of linearization techniques. Mathematical analysis, advantages and obstacles are discussed when two different coding schemes are employed in the 1st feedback digital-to-analogue converter of the continuous-time sigma-delta modulator. The proposed architecture is designed and simulated considering a wireless mobile application.

  • 20.
    Gisdakis, Stylianos
    et al.
    KTH, School of Electrical Engineering (EES), Communication Networks.
    Manolopoulos, Vasileios
    KTH.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Papadimitratos, Panagiotis
    KTH, School of Electrical Engineering (EES), Communication Networks.
    Secure and Privacy-Preserving Smartphone based Traffic Information Systems2015In: IEEE transactions on intelligent transportation systems (Print), ISSN 1524-9050, E-ISSN 1558-0016, Vol. 16, no 3Article in journal (Refereed)
    Abstract [en]

    Increasing smartphone penetration, combined with the wide coverage of cellular infrastructures, renders smartphone-based traffic information systems (TISs) an attractive option. The main purpose of such systems is to alleviate traffic congestion that exists in every major city. Nevertheless, to reap the benefits of smartphone-based TISs, we need to ensure their security and privacy and their effectiveness (e.g., accuracy). This is the motivation of this paper: We leverage state-of-the-art cryptographic schemes and readily available telecommunication infrastructure. We present a comprehensive solution for smartphone-based traffic estimation that is proven to be secure and privacy preserving. We provide a full-blown implementation on actual smartphones, along with an extensive assessment of its accuracy and efficiency. Our results confirm that smartphone-based TISs can offer accurate traffic state estimation while being secure and privacy preserving.

  • 21.
    Grimaldi, Rocco
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 10-bit 5kHz level-crossing ADC2011In: 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011, 2011, p. 564-567Conference paper (Refereed)
  • 22.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Behavioral modeling of a programmable UWB/Bluetooth ADC2007In: 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007: Marrakech; 11 December 2007 through 14 December 2007, 2007, p. 1159-1162Conference paper (Other academic)
    Abstract [en]

    This paper presents the system level design of a programmable ADC that can cover the bandwidth-accuracy space of UWB and Bluetooth standards by employing a capacitive interpolation flash ADC and a sigma-delta ADC. The system level performance of the ADC architectures has been evaluated, and circuit level specifications have been established, considering the most critical circuit non-idealities. The behavioral simulation results show that the ADC can achieve 30 dB SINAD at 528 MSPS in UWB mode, and 86 dB SINAD at 1 MSPS in Bluetooth mode.

  • 23.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Design of a Reconfigurable ADC for UWB/Bluetooth Radios2008In: 2008 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA: Montreal, QC; 22 June 2008 through 25 June 2008, New York: IEEE , 2008, p. 205-208Conference paper (Refereed)
    Abstract [en]

    This paper presents the circuit implementation of a reconfigurable Analog to Digital Converter (ADC) for UWB and Bluetooth communication standards for mobile terminals. The bandwidth accuracy space is covered through smart configuration of a flexible capacitive interpolation ADC, used as stand-alone in UWB mode and as quantizer of a Sigma Delta ADC in Bluetooth mode. The ADC has been accurately modeled in Matlab/Simulink and then implemented at transistor level in a 180 nm CMOS process in the Cadence environment. The simulation results indicate that the ADC can achieve 30 dB SINAD at 528 MSPS in UWB mode, and 60 dB SINAD at 1 MSPS in Bluetooth mode.

  • 24.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Systematic design of a high-speed capacitive interpolative flash ADC2007Report (Other academic)
  • 25.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Neubauer, Harald
    Fraunhofer Institute for Integrated Circuits, Erlangen, Germany.
    Hauer, Johann
    Fraunhofer Institute for Integrated Circuits, Erlangen, Germany.
    A flexible algorithmic ADC for wireless sensor nodes2008In: Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008: St. Julian's; 31 August 2008 through 3 September 2008, 2008, p. 1213-1216Conference paper (Refereed)
  • 26.
    Gustafsson, E. Martin I.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Elnaggar, Mohammed Ismail
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Neubauer, Harald
    Fraunhofer Institute for Integrated Circuits, Erlangen, Germany.
    Hauer, Johann
    Fraunhofer Institute for Integrated Circuits, Erlangen, Germany.
    A programmable algorithmic ADC for low-power wireless applications2008Report (Other academic)
  • 27.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 500 degrees C 8-b Digital-to-Analog Converter in Silicon Carbide Bipolar Technology2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 9, p. 3445-3450Article in journal (Refereed)
    Abstract [en]

    High-temperature integrated circuits provide important sensing and controlling functionality in extreme environments. Silicon carbide bipolar technology can operate beyond 500 degrees C and has shown stable operation in both digital and analog circuit applications. This paper demonstrates an 8-b digital-to-analog converter (DAC). The DAC is realized in a current steering R-2R configuration. High-gain Darlington current switches are used to ensure ideal switching at 500 degrees C. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) at 25 degrees C are 0.79 and 1.01 LSB, respectively, while at 500 degrees C, the DNL and INL are 4.7 and 2.5 LSB, respectively. In addition, the DAC achieves 53.6 and 40.6 dBc of spurious free dynamic range at 25 degrees C and 500 degrees C, respectively.

  • 28.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Monolithic, 500 degrees C Operational Amplifier in 4H-SiC Bipolar Technology2014In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 35, no 7, p. 693-695Article in journal (Refereed)
    Abstract [en]

    A monolithic bipolar operational amplifier (opamp) fabricated in 4H-SiC technology is presented. The opamp has been used in an inverting negative feedback amplifier configuration. Wide temperature operation of the amplifier is demonstrated from 25 degrees C to 500 degrees C. The measured closed loop gain is around 40 dB for all temperatures whereas the 3 dB bandwidth increases from 270 kHz at 25 degrees C to 410 kHz at 500 degrees C. The opamp achieves 1.46 V/mu s slew rate and 0.25% total harmonic distortion. This is the first report on high temperature operation of a fully integrated SiC bipolar opamp which demonstrates the feasibility of this technology for high temperature analog integrated circuits.

  • 29.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wide Temperature Range Integrated Amplifier in Bipolar 4H-SiC Technology2016In: 2016 46TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), IEEE, 2016, p. 198-201Conference paper (Refereed)
    Abstract [en]

    This paper presents a high temperature integrated amplifier implemented in bipolar 4H-SiC technology. A 40 dB negative feedback voltage amplifier has been designed using the structured design method to overcome the temperature variation of device parameters. The amplifier performance degrades as the temperature increases from room temperature up to 500 degrees C. The measured gain is reduced from 39 dB at room temperature to 34 dB at 500 degrees C, and the 3-dB bandwidth decreases from 195 kHz to 100 kHz. The measured power-supply-rejection-ratio (PSRR) is reduced from -78 dB to -62 dB, while the output voltage swing decreases from 8 V to 7 V.

  • 30.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wide Temperature Range Integrated Bandgap Voltage References in 4H–SiC2016In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 37, no 2, p. 146-149Article in journal (Refereed)
    Abstract [en]

    Three fully integrated bandgap voltage references (BGVRs) have been demonstrated in a 4H-SiC bipolar technology. The circuits have been characterized over a wide temperature range from 25 degrees C to 500 degrees C. The three BGVRs are functional and exhibit 46 ppm/degrees C, 131 ppm/degrees C, and 120 ppm/degrees C output voltage variations from 25 degrees C up to 500 degrees C. This letter shows that SiC bipolar BGVRs are capable of providing stable voltage references over a wide temperature range.

  • 31.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Silicon Carbide BJT Oscillator Design Using S-Parameters2018In: European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018., 2018Conference paper (Refereed)
    Abstract [en]

    Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation isfurther aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, analternative small-signal, S-parameter based design method can be employed directly without goinginto complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 0C) was accessed by on-wafer probing and connectedby RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

  • 32.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH.
    Schröder, Stephan
    KTH.
    Rodriguez, Saul
    KTH.
    Malm, B. Gunnar
    KTH.
    Östling, Mikael
    KTH.
    Rusu, Ana
    KTH.
    An Intermediate Frequency Amplifier for High-Temperature Applications2018In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed)
    Abstract [en]

    This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

  • 33.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB.
    Zumbro, John E.
    University of Arkansas.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications2019In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed)
    Abstract [en]

    This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

  • 34.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zumbro, John E.
    University of Arkansas.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed)
    Abstract [en]

    This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

  • 35.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling Temperature Dependence of fT in 4H-SiC Bipolar Transistors2015Conference paper (Other academic)
    Abstract [en]

    This paper models the temperature dependence of fT in 4H-SiC bipolar devices. The proposed model describes variation of the constituent parameters of fT as a function of temperature. The model assumes complete ionization of dopants in 4H-SiC. However, this assumption hampers the model’s utilityat temperatures below 300◦C. The model was simulated attemperatures between 300◦C and 700◦C and a drop in fT wasobserved. However, measurements are required to prove thecorrectness of the model or lack thereof.

  • 36.
    Iannazzo, Mario
    et al.
    Technical University of Catalonia.
    Lo Muzzo, Valerio
    STMicroelectronics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Pandey, Himadri
    University of Siegen.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max
    University of Siegen.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Optimization of a Compact I–V Model forGraphene FETs: Extending Parameter Scalability for Circuit Design Exploration2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, p. 3870-3875Article in journal (Refereed)
    Abstract [en]

    An optimization of the current-to-voltage transfer characteristic of a graphene FET (GFET) compact model, based on drift-diffusion carrier transport, is presented. The improved accuracy at Dirac point extends the model usability for GFETs when scaling parameters, such as voltage supply, gate length, oxide thickness, and mobility, for circuit design exploration. The model's accuracy is demonstrated through fitting to GFETs processed in-house. The model has been written in a standard behavioral language, and extensively run in an analog circuit simulator for designing basic circuits, such as inverters and cascode cells, demonstrating its robustness.

  • 37.
    Iannazzo, Mario
    et al.
    Technical University of Catalonia.
    Lo Muzzo, Valerio
    STMicroelectronics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Department of Electrical Engineering and Computer Science Technology, University of Siegen, Siegen, Germany.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Design exploration of graphene-FET based ring-oscillator circuits: A test-bench for large-signal compact models2015In: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Communications Society, 2015, p. 2716-2719Conference paper (Refereed)
    Abstract [en]

    This paper presents a design-oriented characterization of ring-oscillator (RO) circuits based on complementary-inverters (INVs) implemented with graphene-FET (GFET) devices. A large-signal GFET compact model based on drift-diffusion transport is benchmarked at the circuit level against a second GFET compact model based on virtual source. Transient-based simulations of a 3-cell RO yield performance metrics in terms of operating frequency and voltage dynamic range. Against these metrics, a comprehensive design space exploration covering as input design variables parameters as GFET gate-oxide thickness tOX and channel-length L is presented. Methodologically, the work presents a general-purpose design framework, illustrated for ROs, which establishes a vertical circuit-device co-design environment. Its double-fold outcome is to provide guidelines both to bottom-up dimension and size the circuit, as well as top-down refine GFET device models and in turn GFET technology.

  • 38.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed)
    Abstract [en]

    This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

  • 39.
    Ivanisevic, Nikola
    et al.
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM2016In: 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), Vancouver, Canada: IEEE, 2016, article id 7604762Conference paper (Refereed)
    Abstract [en]

    This paper presents a switched-capacitor high-pass delta-sigma modulator that can directly convert a chopper modulated signal to the digital domain. Low power consumption is achieved by employing inverter-based amplifiers and dynamic biasing in the first amplifier with relaxed slew-rate requirements as a result of the multi-bit quantization. The mismatch errors in the switched-capacitor DAC are first-order noise shaped by a tree-structured dynamic element matching encoder. Schematic level simulations show that the high-pass modulator achieves a peak SNDR of 96.4 dB and a SFDR of 101 dBc over a bandwidth of 300 Hz. The total estimated power consumption of the modulator is 19.56 mu W leading to a figure-of-merit of 0.6 pJ/conv.

  • 40.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation2018Conference paper (Refereed)
    Abstract [en]

    A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

  • 41.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Impedance Spectroscopy Based on Linear System Identification2019In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990, Vol. 13, no 2, p. 396-402Article in journal (Refereed)
    Abstract [en]

    Impedance spectroscopy is a commonly used mea-surement technique for electrical characterization of a sample-under-test over a wide frequency range. Most measurementmethods employ a sine wave excitation generator, which implies apoint-by-point frequency sweep and a complex readout architec-ture. This paper presents a fast, wide-band, measurement methodfor impedance spectroscopy based on linear system identification.The main advantage of the proposed method is the low hardwarecomplexity, which consists of a 3-level pulse waveform, aninverting voltage amplifier and a general purpose ADC. A proof-of-concept prototype, which is implemented with off-the-shelfcomponents, achieves an estimation fit of approximately 96%.The prototype operation is validated electrically using knownRC component values and tested in real application conditions.

  • 42.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach2017In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017Conference paper (Refereed)
    Abstract [en]

    Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

  • 43.
    Kargarrazi, Saleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A monolithic SiC drive circuit for SiC Power BJTs2015In: 2015 IEEE 27TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S (ISPSD), IEEE , 2015, p. 285-288Conference paper (Refereed)
    Abstract [en]

    Silicon Carbide (SiC) is an excellent candidate for high temperature electronics applications, thanks to its wide bandgap. SiC power BJTs are commercially available nowadays, and it is demanding to drive them efficiently. This paper reports on the design, layout specifics, and measurements results of a SiC drive integrated circuit (IC) designed for driving SiC power BJTs. The circuit has been tested in different loading conditions (resistive and capacitive), at switching frequencies up to 500kHz, and together with a commercial power BJT. The SiC drive IC is shown to have a robust operation over the entire temperature range from 25 degrees C to 500 degrees C.

  • 44.
    Kargarrazi, Saleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Saggini, Stefano
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    500 degrees C Bipolar SiC Linear Voltage Regulator2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 6, p. 1953-1957Article in journal (Refereed)
    Abstract [en]

    In this paper, we demonstrate a fully integrated linear voltage regulator in silicon carbide NPN bipolar transistor technology, operational from 25 degrees C up to 500 degrees C. For 15-mA load current, this regulator provides a stable output voltage with <2% variation in the temperature range 25 degrees C-500 degrees C. For both line and load regulations, degradation of 50% from 25 degrees C to 300 degrees C and improvement of 50% from 300 degrees C to 500 degrees C are observed. The transient response measurements of the regulator show robust behavior in the temperature range 25 degrees C-500 degrees C.

  • 45.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Dual-Output Thermoelectric Energy Harvesting Interface with 86.6% Peak Efficiency at 30 μW and Total Control Power of 160 nW2016In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173XArticle in journal (Refereed)
    Abstract [en]

    A thermoelectric energy harvesting interface based on a single-inductor dual-output (SIDO) boost converter is presented. A system-level design methodology combined with ultra-low power circuit techniques reduce the power consumption and minimize the losses within the converter. Additionally, accurate zero-current switching (ZCS) and zero-voltage switching (ZVS) techniques are employed in the control circuit to ensure high conversion efficiency at μW input power levels. The proposed SIDO boost converter is implemented in a 0.18 μm CMOS process and can operate from input voltages as low as 15 mV. The measurement results show that the converter achieves a peak conversion efficiency of 86.6% at 30 μW input power.

  • 46.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT).
    A High-Efficiency Energy Harvesting Interface for Implanted Biofuel Cell and Thermal Harvesters2017In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 33, no 5, p. 4125-4134, article id 7940053Article in journal (Refereed)
    Abstract [en]

    A dual-source energy harvesting interface that combines energy from implanted glucose biofuel cell and thermoelectric generator is presented. A single-inductor dual-input dual-output boost converter topology is employed to efficiently transfer the extracted power to the output. A dual-input feature enables the simultaneous maximum power extraction from two harvesters, while a dual-output allows a control circuit to perform complex digital functions at nW power levels. The control circuit reconfigures the converter to improve the efficiency and achieve zero-current and zero-voltage switching. The measurement results of the proposed boost converter, implemented in a 0.18 μm CMOS process, show a peak efficiency of 89.5% when both sources provide a combined input power of 66 μW. In the single-source mode, the converter achieves a peak efficiency of 85.2% at 23 μW for the thermoelectric source and 90.4% at 29 μW for the glucose biofuel cell. The converter can operate from minimum input voltages of 10 mV for the thermoelectric source and 30 mV for the glucose biofuel cell. 

  • 47.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    An Adaptive FET Sizing Technique for HighEfficiency Thermoelectric Harvesters2016In: 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), Monte Carlo: IEEE, 2016, p. 504-507Conference paper (Refereed)
    Abstract [en]

    A theoretical analysis of losses in low power thermoelectric harvester interfaces is used to find expressions for properly sizing the power transistors according to the input voltage level. These expressions are used to propose an adaptive FET sizing technique that tracks the input voltage level and automatically reconfigures the converter in order to improve its conversion efficiency. The performance of a low-power thermoelectric energy harvesting interface with and without the proposed technique is evaluated by circuit simulations under different input voltage/power conditions. The simulation results show that the proposed technique improves the conversion efficiency of the energy harvesting interface up to 12% at the lowest input voltage/power levels.

  • 48.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    An Efficient Boost Converter Control for Thermoelectric Energy Harvesting2013In: Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on, IEEE conference proceedings, 2013, p. 385-388Conference paper (Refereed)
    Abstract [en]

    This paper presents an ultra-low power controlcircuit for a DC-DC boost converter targeting implantablethermoelectric energy harvesting applications. Efficiency of theinput converter is enhanced by utilizing zero-current switchingtechnique. Adaptive delay between ON states of switches assureszero-voltage switching of synchronous rectifier and reducesswitching losses. The control circuit employing both techniquesconsumes an average power of 620nW. This allows the converterto operate from harvested power below 5μW. For voltageconversion ratios above 20, the proposed circuits and techniquesdemonstrate efficiency improvement compared to the state-of-the-art solutions.

  • 49.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Analysis of Dead Time Losses in Energy Harvesting Boost Converters for Implantable Biosensors2014In: NORCHIP, 2014, IEEE conference proceedings, 2014, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Efficiency of an ultra-low power energy harvesting dc-dc converter depends on its losses and the power consumption of the control circuit. Unlike other loss mechanisms, losses related to dead times have not been thoroughly studied. Therefore, in most cases these losses are not adequately suppressed. This paper investigates dead time losses and their impact on the overall system efficiency. Simple expressions for fast estimation of dead time losses are derived. Analysis shows that in many applications where high voltage conversions are required, such as implantable biosensors, the efficiency reduction due to these losses can easily exceed 2%. The analysis is validated using an adaptive dead time circuit which minimizes the associated losses and improves the overall system efficiency according to the calculated values.

  • 50.
    Lemme, Max C.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Graphene for More Moore and More Than Moore applications2012In: IEEE Silicon Nanoelectronics Workshop, SNW, IEEE , 2012, p. 6243322-Conference paper (Refereed)
    Abstract [en]

    Graphene has caught the attention of the electronic device community as a potential future option for More Moore and More Than Moore devices and applications. This is owed to its remarkable material properties, which include ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm 2/Vs in pristine graphene. Furthermore, standard CMOS technology may be applied to graphene in order to make devices. Integrated graphene devices, however, are performance limited by scattering due to defects in the graphene and its dielectric environment [1, 2] and high contact resistance [3, 4]. In addition, graphene has no energy band gap (Figure 1) and hence graphene MOSFETs (GFETs) cannot be switched off, but instead show ambipolar behaviour [5]. This has steered interest away from logic to analog radio frequency (RF) applications [6, 7]. This talk will systematically compare the expected RF performance of realistic GFETs with current silicon CMOS technology [8]. GFETs slightly lag behind in maximum cut-off frequency F T,max (Figure 2) up to a carrier mobility of 3000 cm 2/Vs, where they can achieve similar RF performance as 65nm silicon FETs. While a strongly nonlinear voltage-dependent gate capacitance inherently limits performance, other parasitics such as contact resistance are expected to be optimized as GFET process technology improves.

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