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  • 1. Fakih, M.
    et al.
    Lenz, A.
    Azkarate-Askasua, M.
    Coronel, J.
    Crespo, A.
    Davidmann, S.
    Diaz Garcia, J. C.
    Romero, N. G.
    Grüttner, K.
    Schreiner, S.
    Seyyedi, R.
    Obermaisser, R.
    Maleki, A.
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Mohammadat, Mohamed Tagelsir
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Pérez-Cerrolaza, J.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Söderquist, I.
    SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems2017Ingår i: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 52, s. 89-105Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1.

  • 2.
    Ngo, Kalle
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Mohammadat, Tage
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Towards a Single Event Upset Detector Based on COTS FPGA2017Ingår i: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC) / [ed] Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR, IEEE , 2017Konferensbidrag (Refereegranskat)
    Abstract [en]

    The Single Event Upset Detector (SEUD) is 3U CubeSat payload experiment that aims to achieve radiation tolerant computing through detection and correction of SEU bit flips on COTS SRAM FPGAs. Our proposed self-healing architecture applies selective TMR, internal configuration memory scrubbing, and partial reconfiguration and intends to demonstrate a cost-effective alternative to Space-grade radiation hardened SRAM FPGAs. This paper presents an overview of the ongoing development of the SEUD architecture and when complete, the SEUD will be tested on board the KTH MIST student CubeSat that is targeting to be launched in late 2020.

  • 3.
    Rosvall, Kathrin
    et al.
    KTH, Skolan för elektroteknik och datavetenskap (EECS).
    Mohammadat, Tage
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Ungureanu, George
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Öberg, Johnny
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Elektronik och inbyggda system.
    Sander, Ingo
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors2018Konferensbidrag (Refereegranskat)
    Abstract [en]

    System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.

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  • 4.
    Seyyedi, R.
    et al.
    OFFIS Inst Informat Technol, Oldenburg, Germany..
    Mohammadat, M. Tage
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Fakih, M.
    OFFIS Inst Informat Technol, Oldenburg, Germany..
    Gruttner, K.
    OFFIS Inst Informat Technol, Oldenburg, Germany..
    Öberg, Johnny
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik.
    Graham, D.
    Imperas, London, England..
    Towards virtual prototyping of synchronous real-time systems on noc-based MPSoCs2017Ingår i: 2017 12th IEEE International Symposium on Industrial Embedded Systems, SIES 2017 - Proceedings, Institute of Electrical and Electronics Engineers (IEEE), 2017, s. 99-102, artikel-id 7993375Konferensbidrag (Refereegranskat)
    Abstract [en]

    NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a 2x2 NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work. NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work.

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