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  • 1.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Torikka, Tommi
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ismail, Muhammed
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tjukanoff, Esa
    A DC-13GHz LNA for UWB RFID applications2004Inngår i: 22ND NORCHIP CONFERENCE, PROCEEDINGS, 2004, s. 241-244Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we present a 4-stage traveling wave lownoise amplifier for UWB RFID (ultra-wideband radiofrequency identification). This LNA covers a frequencyrange of DC - 13 CHz. The circuit is implemented with0.I5pm GaAs PHEMT chips embedded in flexible LCP(liquid crystal polymer) substrate. In the frequency range,the gain of the LNA is better than IO dB, fluctuation of thegain is less than 3dB, its noise figure is less than 4dB, SI 1and S22 are around -10 dB.

  • 2.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ismail, Muhammad
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    On-chip versus Off-chip Passives Trade-offs in Radio and Mixed-Signal System-on- PackageManuskript (preprint) (Annet vitenskapelig)
  • 3.
    Duo, Xinzhong
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Ismail, Muhammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A concurrent multi-band LNA for multi-standard radios2005Inngår i: 2005 IEEE International Symposium On Circuits And Systems (ISCAS), Conference Proceedings, IEEE , 2005, s. 3982-3985Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A source-degenerated cascade LNA, which works at 2.4GHz and 5.8GHz simultaneously, is designed for Bluetooth and IEEE wireless LAN 802.11 a/b/g receivers. In this design, 0.15 mu m GaAs PHEMT technology and embedded passives in MCM-D substrate are implemented. At 2.4GHz and 5.8GHz, this LNA provides 12.2dB and 15.3dB gain, respectively. Noise figures of the LNA are 0.53dB and 1.43dB, respectively. Good input matching and output matching are also achieved-S11 and S22 at both frequencies are less than -10dB.

  • 4.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ismail, Muhammed
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Analysis of lossy packaging parasitics for common emitter LNA in system-on-package2004Inngår i: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, NEW YORK: IEEE , 2004, s. 75-78Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Advances of VLSI and packaging technologies enable condensed integration of an RF system in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP for RF systems and their sub-systems, it is needed to predict and estimate performance of each solution. In this paper, analytical equations for noise figure and gain of inductively degenerated common-emitter low-noise amplifiers in SoP/SoC are deduced as functions of passives and packaging parasitics. They hence enable designers to evaluate overall performance of each solution quantitatively. As well, influence of lossy packaging parasitics on LNA is also analyzed.

  • 5.
    Duo, Xinzhong
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Ismail, Muhammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Broadband CMOS LNAs for IR-UWB receiver2005Inngår i: Norchip 2005, Proceedings, New York: IEEE , 2005, s. 273-276Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Two single-ended wideband LNAs for Ultrawide-band receiver have been designed and implemented in 0.18 mu m CMOS technology. The first one, a feed-back LNA, is a two-stage amplifier with a improved feedback loop, which provides high gain and enables the input port to match with 500 in a wide frequency range from 500MHz to 8GHz. The second one, an LC low-pass-filter matched LNA, employs a third-order low pass filter in the input port to match a frequency range from 3GHz to 8GHz. In both of the LNAs, the input stage is a common source amplifier. Inductive shunt peaking is used for maximizing the bandwidth and flatting the gain. In the feed-back LNA, measurements show that the maximum gain is 11.5dB, the 3-dB; bandwidth is from 500MHz to 7GHz, IIP3 is -2.2dBm at 4GHz, the minimum noise figure is around 5.7dB, S11 is less than 8.2dB, and the power consumption is 14mW. In the LC filter matched LNA, the 3-dB bandwidth is from 3GHz to 7.3GHz. The maximum gain is 9.6dB, IIP3 is 0dBm at 4 GHz, the minimum noise figure is 7.6dB, S11 is less than -13.4dB and the power consumption is 23mW.

  • 6. El Ghany, M. A. A.
    et al.
    El-Moursy, M. A.
    Ismail, Muhammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT. Electrical Engineering Dept., Ohio State University, United States .
    High throughput high performance NoC switch2008Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Increasing the number of virtual channels can improve the throughput in an on-chip interconnection network. High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch.

  • 7.
    Rusu, Ana
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Borodenkov, Alexei
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Ismail, Mohammed
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Design of a power/performance efficient single-loop sigma-delta modulator for wireless receivers2004Inngår i: INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION / [ed] Macii, E; Paliouras, V; Koufopavlou, O, BERLIN: SPRINGER , 2004, Vol. 3254, s. 564-573Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In order to design high performance sigma-delta A/D converters, it is essential to estimate the Figure-Of-Merit in the design process. This paper describes the design of a power/performance efficient single-loop multibit sigma-delta modulator for wireless applications. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. A 3(rd) order 4-bit Sigma-Delta modulator with feedforward path is designed in 0.18um CMOS process operating from 1.8V supply voltage. The modulator dissipates 8.6 mW and achieves a dynamic range of 84/95 dB over a bandwidth of 2000/100 kHz.

  • 8. Zamzam, D. M.
    et al.
    Abd El Ghany, M. A.
    Hofmann, K.
    Ismail, Muhammad
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Highly reliable and power efficient NOC interconnects2011Inngår i: NORCHIP, 2011Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Network on chip (NOC) architecture interconnects consume significant amount of power, have a large propagation delay and are susceptible to error due to deep sub-micron (DSM) noise. Major challenge that NOC design expected to face is related to intrinsic reliability. By incorporating error control coding schemes along the NOC interconnects, NOC architectures are able to provide correct functionality in the presence of different transient noise source. In this paper we present a novel coding scheme that increase the reliability of the NOC where the area is reduced by 19% and the consumed power by NOC interconnects is decreased by 51%. Butterfly fat tree architecture consumes the minimum power as compared to other NOC architectures.

  • 9.
    Zheng, Li-Rong
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Duo, Xinzhong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Nejad, Majid B.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Rodriguez Duenas, Saul
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Ismail, Muhammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    On-chip versus off-chip passives in radio and mixed-signal system-on-package design2006Inngår i: ESTC 2006 - 1st Electronics Systemintegration Technology Conference, New York: IEEE , 2006, s. 221-232Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Optimal total solution for new radio architecture and implementation requires accurate trade-offs for off-chip versus off-chip passives. In this paper, a complete and systematic design methodology for RF blocks in SoP (system-on-package) versus SoC (system-on-chip) is presented. This methodology explores trade-offs between Performance and cost when different on-chip or off-chip passives are used. For a better presentation, the method and design techniques are demonstrated through four multi-band/multi-standard radio design examples with various technologies and different circuit topologies. Our study reveals that, in order to obtain cost benefits in RF-SoPs, small RF chips should be merged as larger chips and the integration density of each RF chip should be high enough. Our study also indicates that in a complex chip like a multi-band radio, moving passives off chip could achieve further cost savings and significant performance improvements. These are general conclusions but, our method offers a detailed analysis which can give quantitative measurements of cost savings and performance improvements in off-chip versus off-chip passives in RF SoP design.

1 - 9 of 9
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