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  • 1.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zahedinejad, Mohammad
    Department of Physics, University of Gothenburg.
    Åkerman, Johan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics. Department of Physics, University of Gothenburg.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators2019In: IEEE transactions on magnetics, ISSN 0018-9464, E-ISSN 1941-0069, Vol. 55, no 10, article id 4003808Article in journal (Refereed)
    Abstract [en]

    Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

  • 2.
    Chaourani, Panagiotis
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Onet, Raul
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Enabling Area Efficient RF ICs through Monolithic 3D Integration2017In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 610-613, article id 7927059Conference paper (Refereed)
    Abstract [en]

    The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

  • 3.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines2019In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 2, p. 468-480Article in journal (Refereed)
    Abstract [en]

    Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

  • 4.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Stathis, Dimitrios
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors2018In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Conference paper (Refereed)
    Abstract [en]

    The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

  • 5.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Silicon Carbide BJT Oscillator Design Using S-Parameters2018In: European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018., 2018Conference paper (Refereed)
    Abstract [en]

    Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation isfurther aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, analternative small-signal, S-parameter based design method can be employed directly without goinginto complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 0C) was accessed by on-wafer probing and connectedby RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

  • 6.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH.
    Schröder, Stephan
    KTH.
    Rodriguez, Saul
    KTH.
    Malm, B. Gunnar
    KTH.
    Östling, Mikael
    KTH.
    Rusu, Ana
    KTH.
    An Intermediate Frequency Amplifier for High-Temperature Applications2018In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed)
    Abstract [en]

    This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

  • 7.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB.
    Zumbro, John E.
    University of Arkansas.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications2019In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed)
    Abstract [en]

    This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

  • 8.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zumbro, John E.
    University of Arkansas.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed)
    Abstract [en]

    This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

  • 9.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed)
    Abstract [en]

    This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

  • 10.
    Ivanisevic, Nikola
    et al.
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM2016In: 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), Vancouver, Canada: IEEE, 2016, article id 7604762Conference paper (Refereed)
    Abstract [en]

    This paper presents a switched-capacitor high-pass delta-sigma modulator that can directly convert a chopper modulated signal to the digital domain. Low power consumption is achieved by employing inverter-based amplifiers and dynamic biasing in the first amplifier with relaxed slew-rate requirements as a result of the multi-bit quantization. The mismatch errors in the switched-capacitor DAC are first-order noise shaped by a tree-structured dynamic element matching encoder. Schematic level simulations show that the high-pass modulator achieves a peak SNDR of 96.4 dB and a SFDR of 101 dBc over a bandwidth of 300 Hz. The total estimated power consumption of the modulator is 19.56 mu W leading to a figure-of-merit of 0.6 pJ/conv.

  • 11.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation2018Conference paper (Refereed)
    Abstract [en]

    A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

  • 12.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Impedance Spectroscopy Based on Linear System Identification2019In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990, Vol. 13, no 2, p. 396-402Article in journal (Refereed)
    Abstract [en]

    Impedance spectroscopy is a commonly used mea-surement technique for electrical characterization of a sample-under-test over a wide frequency range. Most measurementmethods employ a sine wave excitation generator, which implies apoint-by-point frequency sweep and a complex readout architec-ture. This paper presents a fast, wide-band, measurement methodfor impedance spectroscopy based on linear system identification.The main advantage of the proposed method is the low hardwarecomplexity, which consists of a 3-level pulse waveform, aninverting voltage amplifier and a general purpose ADC. A proof-of-concept prototype, which is implemented with off-the-shelfcomponents, achieves an estimation fit of approximately 96%.The prototype operation is validated electrically using knownRC component values and tested in real application conditions.

  • 13.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach2017In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017Conference paper (Refereed)
    Abstract [en]

    Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

  • 14. Kargarrazi, S.
    et al.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT).
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT).
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT).
    500 °c, High Current Linear Voltage Regulator in 4H-SiC BJT Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 4, p. 548-551Article in journal (Refereed)
    Abstract [en]

    This letter reports on a fully integrated 2-linear voltage regulator operational in a wide temperature range from 25 °C up to 500 °C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 °C) and high-load driving capabilities (up to 2).

  • 15.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    An Adaptive FET Sizing Technique for HighEfficiency Thermoelectric Harvesters2016In: 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), Monte Carlo: IEEE, 2016, p. 504-507Conference paper (Refereed)
    Abstract [en]

    A theoretical analysis of losses in low power thermoelectric harvester interfaces is used to find expressions for properly sizing the power transistors according to the input voltage level. These expressions are used to propose an adaptive FET sizing technique that tracks the input voltage level and automatically reconfigures the converter in order to improve its conversion efficiency. The performance of a low-power thermoelectric energy harvesting interface with and without the proposed technique is evaluated by circuit simulations under different input voltage/power conditions. The simulation results show that the proposed technique improves the conversion efficiency of the energy harvesting interface up to 12% at the lowest input voltage/power levels.

  • 16.
    Onet, Raul
    et al.
    KTH, School of Information and Communication Technology (ICT). Tech Univ Cluj Napoca, Cluj Napoca 400027, Romania..
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT).
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT).
    High-Purity and Wide-Range Signal Generator for Bioimpedance Spectroscopy2018In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 65, no 12, p. 1884-1888Article in journal (Refereed)
    Abstract [en]

    This brief presents an integrated high-purity current signal generator (SG), part of a bioimpedance spectroscopy system that performs measurements in the frequency range from 1 kHz to 2 MHz, and it is able to measure bioimpedance values from 100 Omega to 1 M Omega. The SG is implemented in a 0.18-mu m CMOS process, it is powered by a single 1.8 V voltage source, and occupies a total area of 1.62 mm(2). It is able to generate single-frequency signals from 1 kHz to 2 MHz in 12 steps logarithmically spaced. High signal purity is achieved by using a second-order low-pass filter, with a bandwidth that can be programmed from 4 kHz to 8 MHz, in 12 points logarithmically spaced. The SG's power consumption varies from 750 mu W, at the lowest frequencies and gain, to 2.06 mW at the highest frequencies and gain. The output current levels can be modified from 130 nA up to 10 mu A in five programmable steps (9.5 dB per step). The SG achieves a spurious-free dynamic range larger than 40 dB while covering almost three decades in frequency. Such performance enables measurements with errors below 1%, as it is required for accurate bioimpedance measurements in many medical applications.

1 - 16 of 16
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