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  • 1.
    Attarzadeh Niaki, Seyed Hosein
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Managing the Complexity in Embedded and Cyber-Physical System Design: System Modeling and Design-Space Exploration2014Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    To cope with the increasing complexity of embedded and cyber-physical system design, different system-level design approaches are proposed which start from abstract models and implement them using design flows with high degrees of automation. However, creating models of such systems and also formulating the mathematical problems arising in these design flows are themselves challenging tasks. A promising approach is the composable construction of these models and problems from more basic entities. Unfortunately, it is non-trivial to propose such compositional formulations today because the current practice in the electronic design automation domain tends to be on using imperative languages and frameworks due to legacy and performance-oriented reasons.

    This thesis addresses the system design complexity by first promoting proper formalisms and frameworks for capturing models and formulating design-space exploration problems for electronic system-level design in a declarative style; and second, propose realizations based on the industrially accepted languages and frameworks which hold the interesting properties such as composability and parallelism.

    For modeling, ForSyDe, a denotational system-level modeling formalism for heterogeneous embedded systems is chosen, extended with timed domains to make it more appropriate for capturing cyber-physical systems, and mapped on top of the IEEE standard system design language SystemC. The realized modeling framework, called ForSyDe-SystemC, can be used for modeling systems of heterogeneous nature and their composition to form more sophisticated systems and also conducting parallel and distributed simulation for boosting the simulation speed. Another extension to ForSyDe, named wrapper processes, introduces the ability to compose formal ForSyDe models with legacy IP blocks running in external execution environments to perform a heterogeneous co-simulation.

    In platform-based design flows, the correct and optimal mapping of an application model onto a flexible platform involves solving a hard problem, named design space exploration. This work proposes Tahmuras, a constraint- based framework to construct generic design space exploration problems as the composition of three individual sub-problems: the application, the platform, and the mapping and scheduling problems. In this way, the model of the design space exploration problem in Tahmuras is automatically generated for each combination of application semantics, target platform, and mapping and scheduling policy simply by composing their respective problems. Using constraint programming, problems can be modeled in a declarative style, while they can be solved in a variety of different styles, including imperative solving heuristics commonly used to solve difficult problems. Efficient parallel solvers exists for constraint programming. 

  • 2.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Beserra, G. S.
    University of Brasilia.
    Andersen, N.
    Novelda AS.
    Verdon, M.
    DA-Design Oy.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Heterogeneous system-level modeling for small and medium enterprises2012In: Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on, IEEE conference proceedings, 2012, p. 1-6Conference paper (Refereed)
    Abstract [en]

    The design of today's electronic embedded systems is an increasingly complicated task. This is especially problematic for Small and Medium Enterprises (SMEs) which have limited resources. In this work, we identify a set of common design practices used in industry, with a special focus on problems faced by smaller companies, and formulate them as design scenarios. We show how SMEs can benefit from a system-level design approach by customizing a formal heterogeneous system modeling framework for each scenario. The applicability of this approach is demonstrated by two industrial use cases, an impulse-radio radar and a UART-based protocol.

  • 3.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Cevrero, Alessandro
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Brisk, Philip
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Nicopoulos, Chrysostomos
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Gurkaynak, Frank K.
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Leblebici, Yusuf
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Ienne, Paolo
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Design space exploration for field programmable compressor trees2008In: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, New York: ACM Press, 2008, p. 207-216Conference paper (Refereed)
    Abstract [en]

    The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device. This paper presents a design space exploration (DSE) method that can be used to identify the best FPCT architecture for a given set of arithmetic benchmark circuits; in practice, an FPGA vendor can use the design space exploration to tailor the FPCT to meet the needs of the most important benchmark circuits of the vendor’s largest-volume clients. One novel feature of the DSE is the introduction of a metric called I/O utilization; we found that I/O utilization has a strong correlation with both the critical path delay and area of the benchmark circuits under study. Pruning the search space using I/O utilization allowed us to reduce significantly the number of FPCTs that must be synthesized and evaluated during the DSE, while giving high confidence that the best architectures are still explored. The DSE was applied to seven small-to-medium range benchmark circuits; one FPCT architecture was found that was 30% faster than the second best in terms of critical path delay, and only 3.34% larger than the smallest.

  • 4.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jakobsen, M. K.
    Technical University of Denmark.
    Sulonen, T.
    DA-Design Oy.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Formal heterogeneous system modeling with SystemC2012In: Proceedings of Forum on Specification and Design Languages (FDL) 2012, 2012, p. 160-167Conference paper (Refereed)
    Abstract [en]

    Electronic System Level (ESL) design of embedded systems proposes raising the abstraction level of the design entry to cope with the increasing complexity of such systems. To exploit the benefits of ESL, design languages should allow specification of models which are a) heterogeneous, to describe different aspects of systems; b) formally defined, for application of analysis and synthesis methods; c) executable, to enable early detection of specification; and d) parallel, to exploit the multi- and many-core platforms for simulation and implementation. We present a modeling library on top of SystemC, targeting heterogeneous embedded system design, based on four models of computation. The library has a formal basis where all elements are well defined and lead in construction of analyzable models. The semantics of communication and computation are implemented by the library, which allows the designer to focus on specifying the pure functional aspects. A key advantage is that the formalism is used to export the structure and behavior of the models via introspection as an abstract representation for further analysis and synthesis.

  • 5.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mikulcak, Marcus
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A Framework for Characterizing Predictable Platform Templates2014Report (Other academic)
    Abstract [en]

    The design of real-time multiprocessor systems is a very costly and time-consuming process due to the need for extensive verification efforts. Genericcorrect-by-construction system-level design flows, targeting predictable plat-forms, would help to tackle this problem. Unfortunately, because system-level design problems are formulated monolithically, existing methods areeither not powerful enough to perform efficient design space exploration,over-customized to a specific class of platforms, or do not allow to be ex-tended with new heuristics and solving methods, which makes their reusedifficult. We present a formal framework to explicitly capture and character-ize predictable platform templates that can be used to formulate a genericdesign flow for real-time streaming applications in a composable manner. Aproof-of-concept implementation of such a flow is performed and used to mapa JPEG encoder application onto an FPGA-based time-predictable platform.

  • 6.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mikulcak, Marcus
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Automatic Generation of Virtual Prototypes from Platform Templates2015In: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2013 / [ed] Marie-Minerve Louërat, Torsten Maehne, Switzerland: Springer, 2015, p. 147-166Chapter in book (Refereed)
    Abstract [en]

    Virtual Prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM-2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.

  • 7.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mikulcak, Marcus
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Rapid virtual prototyping of real-time systems using predictable platform characterizations2013In: Forum on Specification Design Languages (FDL) 2013, 2013, p. 6646652-Conference paper (Refereed)
    Abstract [en]

    Virtual prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM 2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.

  • 8.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems2013In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, p. 27-30Conference paper (Refereed)
    Abstract [en]

    Simulation of complex embedded and cyber-physical systems requires exploitation of the computation power ofavailable parallel architectures. Current simulation environments either do not address this parallelism or use separate models for parallel simulation and for analysis and synthesis, which might lead to model mismatches. We extend a formal modeling framework targeting heterogeneous systems with elements that enable parallel simulations. An automated flow is then proposed that starting from a serial executable specification generates an efficient MPI-based parallel simulation model by using aconstraint-based method. The proposed flow generates parallel models with acceptable speedups for a representative example.

  • 9.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Co-simulation of embedded systems in a heterogeneous MoC-based modeling framework2011In: 2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES): Proceedings of a meeting held 15-17 June 2011, Vasteras, Sweden., IEEE Press, 2011, p. 238-247Conference paper (Refereed)
    Abstract [en]

    New design methodologies and modeling frameworks are required to provide a solution for integrating legacy code and IP models in order to be accepted in the industry. To tackle this problem, we introduce the concept of wrappers in the context of a formal heterogeneous embedded system modeling framework. The formalism is based on the language-independent concept of models of computation. Wrappers enable the framework to co-simulate/co-execute with external models which might be legacy code, an IP block, or an implementation of a partially refined system. They are defined formally in order to keep the analyzability of the original framework and also enable automations such as generation of model wrappers and co-simulation interfaces. As a proof of concept, three wrappers for models in different abstraction levels are introduced and implemented for two case studies.

  • 10.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Semi-formal refinement of heterogeneous embedded systems by foreign model integration2011In: 2011 Forum on Specification and Design Languages (FDL), IEEE conference proceedings, 2011, p. 179-186Conference paper (Refereed)
    Abstract [en]

    There is a need for integration of external models in high-level system design flows. We introduce a set of partial refinement operations to implement models of heterogeneous embedded systems. The models are in form of process networks where each process belongs to a single model of computation. A semi-formal design flow has been introduced based on these operations to incrementally refine system specifications to their implementation. Wrapper processes, which allow co-simulation of a system model in the framework with external models and implementations are used to keep the intermediate system models after each refinement step verifiable. Additionally, this design flow has the advantage of integrating legacy code and IP cores. Using a simple example as the case study, we have shown how we can apply this design methodology to a simple system.

  • 11.
    Attarzadeh-Niaki, Seyed Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Integrating Functional Mock-up units into a formal heterogeneous system modeling framework2015In: 18th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015Conference paper (Refereed)
    Abstract [en]

    The Functional Mock-up Interface (FMI) standard defines a method for tool- and platform-independent model exchange and co-simulation of dynamic system models. In FMI, the master algorithm, which executes the imported components, is a timed differential equation solver. This is a limitation for heterogeneous embedded and cyber-physical systems, where models with different time abstractions co-exist and interact. This work integrates FMI into a heterogeneous system modeling and simulation framework as process constructors and co-simulation wrappers. Consequently, each external model communicates with the framework without unnecessary semantic adaptation while the framework provides necessary mechanisms for handling heterogeneity. The presented methods are implemented in the ForSyDe-SystemC modeling framework and tested using a case study.

  • 12.
    Attarzadeh-Niaki, Seyed-Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Altinel, Ekrem
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Koedam, Martijn
    Eindhoven University of Technology.
    Molnos, Anca
    CEA-LETI.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Goossens, Kees
    Eindhoven University of Technology.
    A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications2015Conference paper (Refereed)
    Abstract [en]

    Design of real-time MPSoC systems including multiple appli-cations is challenging because temporal requirements of each applicationmust be respected throughout the entire design flow. Currently the de-sign of different applications is often interdependent, making converge toa solution for each application difficult. This paper proposes a composi-tional method to design applications independently, and then to executethem without interference. We define a formal modeling framework as asuitable entry point for application design. The models are executable,which enables early detection of specification errors, and include the for-mal properties of the applications based on well-defined models of com-putation. We combine this with a predictable MPSoC platform templatethat has a supporting design flow but lacks a simulation front-end. Thestructure and behavior of the application models are exported to an in-termediate format via introspection which is iteratively adapted for thebackend flow. We identify the problems arising in this adaptation andprovide appropriate solutions. The design flow is demonstrated by a sys-tem consisting of two streaming applications where less than half of thedesign time is dedicated to operating on the integrated system model.

  • 13.
    Attarzadeh-Niaki, Seyed-Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An extensible modeling methodology for embedded and CPS designManuscript (preprint) (Other academic)
    Abstract [en]

    Abstract models are important tools to manage the increasing complexity of system design. The choice of a modeling language for constructing models governs what types of systems can be modeled and which subsequent design activities can be performed. This is especially true for the area of embedded electronic and cyber-physical system design, which poses several challenging requirements on modeling and design methodologies. This article argues that the ForSyDe methodology with the necessary extensions can fulfill these requirements and thus qualifies for the design of tomorrow’s systems. Based on the theory of models of computation and the concept of process constructors, heterogeneous models are captured in ForSyDe with precise semantics. A refined layer of the formalism is introduced to make its denotational-style semantics easy to implement on top of the commonly used imperative languages and an open-source realization on top of the IEEE standard language SystemC is reported. The introspection mechanism is introduced to automatically export an intermediate representation of the constructed models for further analysis/synthesis by external tools. Flexibility and extensibility of ForSyDe is emphasized by integrating a new timed model of computation without central synchronization, and providing mechanisms for integrating foreign models, parallel and distributed simulation, modeling adaptive, data-parallel, and non-deterministic systems. A set of ForSyDe features are demonstrated in practice and compared to similar approaches using two relevant case studies. 

  • 14.
    Attarzadeh-Niaki, Seyed-Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An extensible modeling methodology for embedded and cyber-physical system design2016In: Simulation (San Diego, Calif.), ISSN 0037-5497, E-ISSN 1741-3133, Vol. 92, no 8, p. 771-794Article in journal (Refereed)
    Abstract [en]

    models are important tools to manage the increasing complexity of system design. The choice of a modeling language for constructing models governs what types of systems can be modeled, and which subsequent design activities can be performed. This is especially true for the area of embedded electronic and cyber-physical system design, which poses several challenging requirements of modeling and design methodologies. This article argues that the Formal System Design (ForSyDe) methodology with the necessary presented extensions fulfills these requirements, and thus qualifies for the design of tomorrow's systems. Based on the theory of models of computation and the concept of process constructors, heterogeneous models are captured in ForSyDe with formal semantics. A refined layer of the formalism is introduced to make its denotational-style semantics easy to implement on top of commonly used imperative languages, and an open-source realization on top of the IEEE standard language SystemC is presented. The introspection mechanism is introduced to automatically export an intermediate representation of the constructed models for further analysis/synthesis by external tools. Flexibility and extensibility of ForSyDe is emphasized by integrating a new timed model of computation without central synchronization, and by providing mechanisms for integrating foreign models, parallel and distributed simulation, modeling adaptive, data-parallel, and non-deterministic systems. A set of ForSyDe features is demonstrated in practice, and compared with similar approaches using a running example and two relevant case studies.

  • 15.
    Attarzadeh-Niaki, Seyed-Hosein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Automatic Construction of Models for Analytic Design Space Exploration ProblemsManuscript (preprint) (Other academic)
    Abstract [en]

    Due to the variety of application semantics and also the target platforms used in embedded electronic system design, it is challenging to propose a generic and extensible analytic design-space exploration (DSE) framework. Current approaches support a restricted class of application and platform models and are difficult to extend. This paper proposes a framework to capture the system functionality, a flexible target platform, and a binding policy explicitly using coherent constraint-based representations; together with a method for automatic construction of DSE problem models from them. Heterogeneous semantics is captured using constraints on logical clocks. The applicability of this method is demonstrated by constructing DSE problem models from various combinations of application and platforms models. Time-triggered and untimed models of the system functionality and heterogeneous target platforms are used for this purpose. The constructed models can be solved using different solvers and heuristics. 

  • 16.
    Beserra, G. S.
    et al.
    University of Brasilia.
    Attarzadeh Niaki, Seyed Hosein
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Integrating virtual platforms into a heterogeneous MoC-based modeling framework2012In: Proceedings of Forum on Specification and Design Languages (FDL) 2012, IEEE conference proceedings, 2012, p. 143-150Conference paper (Refereed)
    Abstract [en]

    In order to handle the increasing complexity of embedded systems, design methodologies must take into account important aspects, such as abstraction, IP-reuse and heterogeneity. System design often starts in a high abstraction level, by developing a virtual platform (VP), which is typically composed of TLM models. TLM has become very popular in the modeling of bus-based systems and currently there is an increasing availability of libraries that provide TLM IPs. Heterogeneity can be naturally captured in a framework supporting different Models of Computation (MoCs). We introduce a novel approach for integrating TLM IPs/VPs into a MoC-based modeling framework, allowing them to co-simulate heterogeneous systems. This approach allows to raise the abstraction level, enabling a more careful design space exploration before selecting a proper VP. We exemplify the potential of our approach with a case study in which a VP with a processor generated by ArchC communicates with a continuous-time model.

  • 17. Cevrero, Alessandro
    et al.
    Athanasopoulos, Panagiotis
    Parandeh-Afshar, Hadi
    Verma, Ajay K.
    Attarzadeh Niaki, Hosein Seyed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Nicopoulos, Chrysostomos
    Gurkaynak, Frank K.
    Brisk, Philip
    Leblebici, Yusuf
    Ienne, Paolo
    Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs2009In: ACM Trans. Reconfigurable Technol. Syst., ISSN 1936-7406, Vol. 2, no 2, p. 1-36Article in journal (Refereed)
    Abstract [en]

    Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The DSP blocks embedded in high-performance FPGAs perform fixed bitwidth parallel multiplication and Multiply-ACcumulate (MAC) operations. In theory, the compressor trees contained within the multipliers could implement multi-input addition; however, they are not exposed to the programmer. To improve FPGA performance for these applications, this article introduces the Field Programmable Compressor Tree (FPCT) as an alternative to the DSP blocks. By providing just a compressor tree, the FPCT can perform multi-input addition along with parallel multiplication and MAC in conjunction with a small amount of FPGA general logic. Furthermore, the user can configure the FPCT to precisely match the bitwidths of the operands being summed. Although an FPCT cannot beat the performance of a well-designed ASIC compressor tree of fixed bitwidth, for example, 9×9 and 18×18-bit multipliers/MACs in DSP blocks, its configurable bitwidth and ability to perform multi-input addition is ideal for reconfigurable devices that are used across a variety of applications.

  • 18. Diallo, P. I.
    et al.
    Attarzadeh-Niaki, Seyed Hosein
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Champeau, J.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    A formal, model-driven design flow for system simulation and multi-core implementation2015In: 2015 10th IEEE International Symposium on Industrial Embedded Systems, IEEE , 2015, p. 254-263Conference paper (Refereed)
    Abstract [en]

    With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.

  • 19.
    Herrera, Fernando
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Attarzadeh, Hosein
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems2013In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, IEEE conference proceedings, 2013, p. 989-996Conference paper (Refereed)
    Abstract [en]

    Mixed-criticality system (MCS) design is an emerging discipline, which has been identified as a core foundational concept in fields such as cyber-physical systems. The hard real-time design community has pioneered the contributions to MCS design, extending scheduling theory to consider mixed-criticalities and the impact of on-chip and off-chip communication infrastructures. However, the development of MCS design methodologies capable to provide safe and efficient solutions for complex applications and platforms in an acceptable design time demands a more interdisciplinary approach. This paper is a first step towards such an approach in the development of MCS design methodologies. The paper first identifies main design disciplines to be involved in MCS design, both at SoC and system-of-systems (SoS) scales. Then, the paper proposes a core ontology for modelling a mixed-criticality system at both SoC scale (MCSoC) and SoS scale (MCSoS). Finally, the paper introduces a set of aspects required for MCS design which have been identified as open and challenging attending the overviewed state-of-the-art.

  • 20.
    Jakobsen, M. K.
    et al.
    Technical University of Denmark.
    Madsen, J.
    Technical University of Denmark.
    Attarzadeh Niaki, Seyed Hosein
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hansen, J.
    System level modelling with open source tools2011In: Embedded World Conference 2011, 2011Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a system level designmethodology which allows designers to model andanalyze their systems from the early stages of thedesign process until nal implementation. The de-sign methodology targets heterogeneous embeddedsystems and is based on a formal modeling frame-work, called ForSyDe. ForSyDe is available underthe open Source approach, which allows small andmedium enterprises (SME) to get easy access toadvanced modeling capabilities and tools. We givean introduction to the design methodology throughthe system level modeling of a simple industrial usecase, and we outline the basics of the underlyingForSyDe model.

  • 21.
    Sander, Ingo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Attarzadeh Niaki, Seyed Hosein
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Towards a Formal Software Synthesis Methodology for Embedded Multiprocessor Systems2011In: Proceedings of First International Software Technology Exchange Workshop 2011, 2011Conference paper (Refereed)
    Abstract [en]

    This paper addresses the increasing complexity of software design for multiprocessor embedded systems by proposing a designmethodology that combines a formal foundation based on the theory of models of computation (MoCs) and the industrial systemdesign language SystemC. The ForSyDe methodology provides thedesigner with SystemC class libraries that lead to executable system models, from which abstract analyzable models can be extracted. Using these abstract models, the design exploration andsynthesis process can make use of existing MoC theory by for instance incorporating efficient scheduling and buffer optimizationtechniques. The choice of SystemC as modeling language allowsfor an efficient implementation, since system model functions canbe directly compiled to target processors.

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