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  • 1.
    Andrei, Alexandru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Energy Efficient and Predictable Design of Real-Time Embedded Systems2007Doktorsavhandling, monografi (Övrigt vetenskapligt)
    Abstract [en]

    This thesis addresses several issues related to the design and optimization of embedded systems. In particular, in the context of time-constrained embedded systems, the thesis investigates two problems: the minimization of the energy consumption and the implementation of predictable applications on multiprocessor system-on-chip platforms.

    Power consumption is one of the most limiting factors in electronic systems today. Two techniques that have been shown to reduce the power consumption effectively are dynamic voltage selection and adaptive body biasing. The reduction is achieved by dynamically adjusting the voltage and performance settings according to the application needs. Energy minimization is addressed using both offline and online optimization approaches. Offline, we solve optimally the combined supply voltage and body bias selection problem for multiprocessor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. The voltage selection technique is applied not only to processors, but also to buses with repeaters and fat wires. We investigate the continuous voltage selection as well as its discrete counterpart. While the above mentioned methods minimize the active energy, we propose an approach that combines voltage selection and processor shutdown in order to optimize the total energy.

    In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the voltage and performance settings during run-time, i.e., online. However, voltage scaling is computationally expensive, and, thus, performed at runtime, significantly hampers the possible energy savings. To overcome the online complexity, we propose a quasi-static voltage scaling scheme, with a constant online time complexity O(1). This allows to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the voltage settings.

    Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restrictive and particular contexts. One important aspect that makes the analysis difficult is the estimation of the system’s communication behavior. The traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. As opposed to the analysis performed for a single processor system, where the cache miss penalty is constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks’ WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this context, we propose, an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures.

  • 2.
    Andrei, Alexandru
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Eles, Petru Ion
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Jovanovic, Olivera
    University of Dortmund.
    Schmitz, Marcus
    Robert Bosch GmbH, Stuttgart.
    Ogniewski, Jens
    Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska högskolan.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints2011Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, ISSN 1063-8210, Vol. 19, nr 1, s. 10-23Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Supply voltage scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the voltage and performance settings according to the application needs. In order to take full advantage of slack that arises from variations in the execution time, it is important to recalculate the voltage (performance) settings during runtime, i.e., online. However, optimal voltage scaling algorithms are computationally expensive, and thus, if used online, significantly hamper the possible energy savings. To overcome the online complexity, we propose a quasi-static voltage scaling scheme, with a constant online time complexity O(1). This allows to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the voltage settings.

  • 3.
    Andrei, Alexandru
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Eles, Petru Ion
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Rosén, Jakob
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Predictable Implementation of Real-Time Applications on Multiprocessor Systems on Chip2008Ingår i: VLSI Design, 2008. VLSID 2008, IEEE Computer Society, 2008, s. 103-110Konferensbidrag (Refereegranskat)
    Abstract [en]

    Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restrictive and particular contexts. One important aspect that makes the analysis difficult is the estimation of the system-s communication behavior. The traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. As opposed to the analysis performed for a single processor system, where the cache miss penalty is constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks- WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this context, we propose, for the first time, an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures.

  • 4.
    Andrei, Alexandru
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Eles, Petru Ion
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Peng, Zebo
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Schmitz, Marcus
    Diesel Systems for Commercial Vehicles Robert Bosch GmbH, Germany.
    Al-Hashimi, Bashir
    Computer Engineering Dept. Southampton University, UK.
    Voltage Selection for Time-Constrained Multiprocessor Systems on Chip2007Ingår i: Designing Embedded Processors: A Low Power Perspective / [ed] Jörg Henkel, Sri Parameswaran, Dordrecht: Springer , 2007, s. 259-286Kapitel i bok, del av antologi (Övrigt vetenskapligt)
    Abstract [en]

    As we embrace the world of personal, portable, and perplexingly complex digital systems, it has befallen upon the bewildered designer to take advantage of the available transistors to produce a system which is small, fast, cheap and correct, yet possesses increased functionality. Increasingly, these systems have to consume little energy.

    Designers are increasingly turning towards small processors, which are low power, and customize these processors both in software and hardware to achieve their objectives of a low power system, which is verified, and has short design turnaround times. Designing Embedded Processors examines the many ways in which processor based systems are designed to allow low power devices.

    It looks at processor design methods, memory optimization, dynamic voltage scaling methods, compiler methods, and multi processor methods. Each section has an introductory chapter to give a breadth view, and have a few specialist chapters in the area to give a deeper perspective. The book provides a good starting point to engineers in the area, and to research students embarking upon the exciting area of embedded systems and architectures.

  • 5.
    Andrei, Alexandru
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Eles, Petru Ion
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Peng, Zebo
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Schmitz, M.T.
    Diesel Systems for Commercial Vehicles, Robert Bosch GmbH, Stuttgart 70469, Germany.
    Al, Hashimi B.M.
    Al Hashimi, B.M., IEEE, Computer Engineering Department, Southampton University, Southampton, SO 17 1BJ, United Kingdom.
    Energy optimization of multiprocessor systems on chip by voltage selection2007Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 15, nr 3, s. 262-275Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Dynamic voltage selection and adaptive body biasing have been shown to reduce dynamic and leakage power consumption effectively. In this paper, we optimally solve the combined supply voltage and body bias selection problem for multiprocessor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. Both energy and time overheads are considered. The voltage selection technique achieves energy efficiency by simultaneously scaling the supply and body bias voltages in the case of processors and buses with repeaters, while energy efficiency on fat wires is achieved through dynamic voltage swing scaling. We investigate the continuous voltage selection as well as its discrete counterpart, and we prove strong NP-hardness in the discrete case. Furthermore, the continuous voltage selection problem is solved using nonlinear programming with polynomial time complexity, while for the discrete problem, we use mixed integer linear programming and a polynomial time heuristic. We propose an approach that combines voltage selection and processor shutdown in order to optimize the total energy. © 2007 IEEE.

  • 6.
    Andrei, Alexandru
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Schmitz, Marcus
    IDA Linköpings Universitet.
    Eles, Petru Ion
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Peng, Zebo
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems2004Ingår i: Design, Automation and Test in Europe DATE 2004,2004, Paris, France: IEEE Computer Society Press , 2004, s. 518-Konferensbidrag (Refereegranskat)
    Abstract [en]

    Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage power consumption effectively. In this paper, we optimally solve the combined supply voltage and body bias selection problem for multi-processor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. Both energy and time overheads are considered. We investigate the continuous voltage scaling as well as its discrete counterpart, and we prove NP-hardness in the discrete case. Furthermore, the continuous voltage scaling problem is formulated and solved using nonlinear programming with polynomial time complexity, while for the discrete problem we use mixed integer linear programming. Extensive experiments, conducted on several benchmarks and a real-life example, are used to validate the approaches.

  • 7.
    Andrei, Alexandru
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Schmitz, Marcus
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Peng, Zebo
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems2005Ingår i: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 152, nr 01, s. 28-38Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage power consumption effectively. In this paper, we optimally solve the combined supply voltage and body bias selection problem for multi-processor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. Both energy and time overheads are considered. We investigate the continuous voltage scaling as well as its discrete counterpart, and we prove NP-hardness in the discrete case. Furthermore, the continuous voltage scaling problemis formulated and solved using nonlinear programming with polynomial time complexity, while for the discrete problem we use mixed integer linear programming. Extensive experiments, conducted on several benchmarks and a real-life example, are used to validate the approaches.

  • 8.
    Andrei, Alexandru
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Schmitz, Marcus
    Dept. of Electronics and Computer Science University of Southampton.
    Eles, Petru Ion
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Peng, Zebo
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints2005Ingår i: Design Automation and Test in Europe Conference DATE 2005,2005, Munich, Germany: IEEE Computer Society Press , 2005, s. 514-Konferensbidrag (Refereegranskat)
  • 9.
    Andrei, Alexandru
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Schmitz, Marcus
    IDA Linköpings Universitet.
    Eles, Petru Ion
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Peng, Zebo
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Al Hashimi, Bashir M.
    Dept. of Electronics and Computer Science University of Southampton.
    Simultaneous Communication and Processor Voltage Scaling for Dynamic and Leakage Energy Reduction in Time-Constrained Systems2004Ingår i: International Conference on Computer Aided Design ICCAD 2004,2004, San Jose, USA: IEEE Computer Society Press , 2004, s. 362-Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, we propose a new technique for the combined voltage scaling of processors and communication links, taking into account dynamic as well as leakage power consumption. The voltage scaling technique achieves energy efficiency by simultaneously scaling the supply and body bias voltages in the case of processors and buses with repeaters, while energy efficiency on fat wires is achieved through dynamic voltage swing scaling. We also introduce a set of accurate communication models for the energy estimation of voltage scalable embedded systems. In particular, we demonstrate that voltage scaling of bus repeaters and dynamic adaption of the voltage swing on fat wires can significantly influence the system's energy consumption. Experimental results, conducted on numerous generated benchmarks and a real-life example, demonstrate that substantial energy savings can be achieved with the proposed techniques.

  • 10.
    Bao, Min
    et al.
    Linköpings universitet, Institutionen för datavetenskap. Linköpings universitet, Tekniska högskolan.
    Andrei, Alexandru
    Ericsson, Linköping.
    Eles, Petru Ion
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    On-line Thermal Aware Dynamic Voltage Scaling for Energy Optimization with Frequency/Temperature Dependency Consideration2009Ingår i: DAC '09 Proceedings of the 46th Annual Design Automation Conference, IEEE Computer Society, 2009, s. 490-495Konferensbidrag (Refereegranskat)
    Abstract [en]

    With new technologies, temperature has become a major issue to be considered at system level design. Without taking temperature aspects into consideration, no approach to energy or/and performance optimization will be sufficiently accurate and efficient. In this paper we propose an on-line temperature aware dynamic voltage and frequency scaling (DVFS) technique which is able to exploit both static and dynamic slack. The approach implies an offline temperature aware optimization step and on-line voltage/frequency settings based on temperature sensor readings. Most importantly, the presented approach is aware of the frequency/temperature dependency, by which important additional energy savings are obtained.

  • 11.
    Bao, Min
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Andrei, Alexandru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Eles, Petru Ion
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling2008Ingår i: 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, IEEE Computer Society, 2008, s. 44-49Konferensbidrag (Refereegranskat)
    Abstract [en]

    Temperature has become an important issue in nowadays MPSoCs design due to the ever increasing power densities and huge energy consumption. This paper proposes a temperature-aware task mapping technique for energy optimization in systems with dynamic voltage selection capability. It evaluates the efficiency of this technique, based on the analysis of the factors that can influence the potential gains that can be expected from such a technique, compared to a task mapping approach that ignores temperature.

  • 12.
    Bao, Min
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Andrei, Alexandru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Eles, Petru Ion
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Temperature-Aware Voltage Selection for Energy Optimization2008Ingår i: Design, Automation and Test in Europe, 2008, IEEE , 2008, s. 1083-1086Konferensbidrag (Refereegranskat)
    Abstract [en]

    This paper proposes a temperature-aware dynamic voltage selection technique for energy minimization and presents a thorough analysis of the parameters that influence the potential gains that can be expected from such a technique, compared to a voltage selection approach that ignores temperature.

  • 13.
    Bao, Min
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Andrei, Alexandru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Eles, Petru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    An Energy Efficient Technique for Temperature-Aware Voltage Selection2009Rapport (Övrigt vetenskapligt)
    Abstract [en]

    High power densities in current SoCs result in both huge energy consumption and increased chip temperature. This paper proposes a temperature-aware dynamic voltage selection technique for energy minimization and presents a thorough analysis of the parameters that influence the potential gains that can be expected from such a technique, compared to a voltage selection approach that ignores temperature. In addition to demonstrating the actual percentages of energy that can be saved by being temperature aware, we explore some significant issues in this context, such as the relevance of taking into consideration transient temperature effects at optimization, the impact of the percentage of leakage power relative to the total power consumed and of the degree to which leakage depends on temperature.

  • 14.
    Bao, Min
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Andrei, Alexandru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ion Eles, Petru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling2010Ingår i: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2010, s. 21-26Konferensbidrag (Refereegranskat)
    Abstract [en]

    With new technologies, temperature has become a major issue to be considered at system level design. In this paper we propose a temperature aware idle time distribution technique for energy optimization with dynamic voltage scaling (DVS). A temperature analysis approach is also proposed which is accurate and, yet, sufficiently fast to be used inside the optimization loop for idle time distribution and voltage selection.

  • 15.
    Bao, Min
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Andrei, Alexandru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Ion Eles, Petru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Temperature-Aware Idle Time Distribution for Leakage Energy Optimization2012Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 20, nr 7, s. 1187-1200Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Large-scale integration with deep sub-micron technologies has led to high power densities and high chip working temperatures. At the same time, leakage energy has become the dominant energy consumption source of circuits due to reduced threshold voltages. Given the close interdependence between temperature and leakage current, temperature has become a major issue to be considered for power-aware system level design techniques. In this paper, we address the issue of leakage energy optimization through temperature aware idle time distribution (ITD). We first propose an offline ITD technique to optimize leakage energy consumption, where only static idle time is distributed. To account for the dynamic slack, we then propose an online ITD technique where both static and dynamic idle time are considered. To improve the efficiency of our ITD techniques, we also propose an analytical temperature analysis approach which is accurate and, yet, sufficiently fast to be used inside the energy optimization loop.

  • 16.
    Pop, Traian
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Pop, Paul
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Eles, Petru Ion
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Peng, Zebo
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Andrei, Alexandru
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Timing analysis of the FlexRay communication protocol2008Ingår i: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 39, nr 1-3, s. 205-235Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    FlexRay is a communication protocol heavily promoted on the market by a large group of car manufacturers and automotive electronics suppliers. However, before it can be successfully used for safety-critical applications that require predictability, timing analysis techniques are necessary for providing bounds for the message communication times. In this paper, we propose techniques for determining the timing properties of messages transmitted in both the static and the dynamic segments of a FlexRay communication cycle. The analysis techniques for messages are integrated in the context of a holistic schedulability analysis that computes the worst-case response times of all the tasks and messages in the system. We have evaluated the proposed analysis techniques using extensive experiments. We also present and evaluate three optimisation algorithms that can be used to improve the schedulability of a system that uses FlexRay. © 2007 Springer Science+Business Media, LLC.

  • 17.
    Pop, Traian
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Pop, Paul
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Eles, Petru Ion
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Peng, Zebo
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Andrei, Alexandru
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Timing Analysis of the FlexRay Communication Protocol2006Ingår i: 18th Euromicro Conference on Real-Time Systems ECRTS 06,2006, Dresden, Germany: IEEE Computer Society Press , 2006, s. 203-Konferensbidrag (Refereegranskat)
    Abstract [en]

    FlexRay will very likely become the de-facto standard for in-vehicle communications. However, before it can be successfully used for safety-critical applications that require predictability, timing analysis techniques are necessary for providing bounds for the message communication times. In this paper, we propose techniques for determining the timing properties of messages transmitted in both the static (ST) and the dynamic (DYN) segments of a FlexRay communication cycle. The analysis techniques for messages are integrated in the context of a holistic schedulability analysis that computes the worst-case response times of all the tasks and messages in the system. We have evaluated the proposed analysis techniques using extensive experiments.

  • 18.
    Rosén, Jakob
    et al.
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Andrei, Alexandru
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Eles, Petru Ion
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Peng, Zebo
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip2007Ingår i: 28th IEEE Real-Time Systems Symposium RTSS07,2007, Tucson, Arizona, USA: IEEE Computer Society Press , 2007, s. 49-Konferensbidrag (Refereegranskat)
    Abstract [en]

    In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. This has a huge impact on worst-case execution time (WCET) analysis and, in general, on the predictability of real-time applications implemented on such systems. As opposed to the WCET analysis performed for a single processor system, where the cache miss penalty is considered constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks' WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this paper we present an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures. The emphasis of this paper is on the bus scheduling policy and its optimization, which is of huge importance for the performance of such a predictable multiprocessor application.

  • 19.
    Rosén, Jakob
    et al.
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Andrei, Alexandru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Eles, Petru Ion
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Peng, Zebo
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Predictable Multiprocessor Systems2010Ingår i: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Konferensbidrag (Övrigt vetenskapligt)
  • 20.
    Ruggiero, Martino
    et al.
    University of Bologna.
    Bertozzi, Davide
    University of Ferrara.
    Benini, Luca
    University of Bologna.
    Milano, Michela
    University of Bologna.
    Andrei, Alexandru
    Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
    Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms2009Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 28, nr 3, s. 378-391Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper proposes a novel approach to solve the allocation and scheduling problems for variable voltage/frequency multiprocessor systems-on-chip, which minimizes overall system energy dissipation. The optimality of derived system configurations is guaranteed, while the computation efficiency of the optimizer allows for solving problem instances that were traditionally considered beyond reach for exact solvers (optimality gap). Furthermore, this paper illustrates the development- and run-time software infrastructures that assist the user in developing applications and implementing optimizer solutions. The proposed approach guarantees a high level of power, performance, and constraint satisfaction predictability as from validation on the target platform, thus bridging the abstraction gap.

  • 21.
    Ruggiero, Martino
    et al.
    DEIS University of Bologna, Italy.
    Gioia, Pari
    DEIS University of Bologna, Italy.
    Alessio, Guerri
    DEIS University of Bologna, Italy.
    Benini, Luca
    DEIS University of Bologna, Italy.
    Michela, Milano
    DEIS University of Bologna, Italy.
    Bertozzi, Davide
    ENDIF University of Ferrara, Italy.
    Andrei, Alexandru
    Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
    A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs2006Ingår i: Intl. Symposium on System-on-Chip SOC06,2006, 2006Konferensbidrag (Refereegranskat)
    Abstract [en]

    Most problems addressed by the software optimization flow for multi-processor systems-on-chip (MPSoCs) are NP-complete, and have been traditionally tackled by means of heuristics and highlevel approximations. Complete approaches have been effectively deployed only under unrealistic simplifying assumptions. We propose a novel methodology to formulate and solve to optimality the allocation, scheduling and discrete voltage selection problem for variable voltage/frequency MPSoCs, minimizing the system energy dissipation and the overhead for frequency switching. We integrate the optimization and validation steps to increase the accuracy of cost models and the confidence in quality of results. Two demonstrators are used to show the viability of the proposed methodology.

1 - 21 av 21
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