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  • 1.
    Abbas, Haider
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Options-Based Security-Oriented Framework for Addressing Uncerainty Issues in IT Security2010Doktorsavhandling, monografi (Övrigt vetenskapligt)
    Abstract [en]

    Continuous development and innovation in Information Technology introduces novel configuration methods, software development tools and hardware components. This steady state of flux is very desirable as it improves productivity and the overall quality of life in societies. However, the same phenomenon also gives rise to unseen threats, vulnerabilities and security concerns that are becoming more critical with the passage of time. As an implication, technological progress strongly impacts organizations’ existing information security methods, policies and techniques, making obsolete existing security measures and mandating reevaluation, which results in an uncertain IT infrastructure. In order to address these critical concerns, an options-based reasoning borrowed from corporate finance is proposed and adapted for evaluation of security architecture and decision- making to handle them at organizational level. Options theory has provided significant guidance for uncertainty management in several domains, such as Oil & Gas, government R&D and IT security investment projects. We have applied options valuation technique in a different context to formalize optimal solutions in uncertain situations for three specific and identified uncertainty issues in IT security. In the research process, we formulated an adaptation model for expressing options theory in terms useful for IT security which provided knowledge to formulate and propose a framework for addressing uncertainty issues in information security. To validate the efficacy of this proposed framework, we have applied this approach to the SHS (Spridnings- och Hämtningssystem) and ESAM (E-Society) systems used in Sweden. As an ultimate objective of this research, we intend to develop a solution that is amenable to automation for the three main problem areas caused by technological uncertainty in information security: i) dynamically changing security requirements, ii) externalities caused by a security system, iii) obsoleteness of evaluation. The framework is general and capable of dealing with other uncertainty management issues and their solutions, but in this work we primarily deal with the three aforementioned uncertainty problems. The thesis presents an in-depth background and analysis study for a proposed options-based security-oriented framework with case studies for SHS and ESAM systems. It has also been assured that the framework formulation follows the guidelines from industry best practices criteria/metrics. We have also proposed how the whole process can be automated as the next step in development.

  • 2.
    Abbas, Haider
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Magnusson, Christer
    Department of Computer and System Sciences, Stockholm University, Sweden.
    Yngström, Louise
    Department of Computer and System Sciences, Stockholm University, Sweden.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Addressing Dynamic Issues in Information Security Management2011Ingår i: Information Management & Computer Security, ISSN 0968-5227, Vol. 19, nr 1, 5-24 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Purpose – The paper addresses three main problems resulting from uncertainty in information securitymanagement: i) dynamically changing security requirements of an organization ii) externalities caused by a securitysystem and iii) obsolete evaluation of security concerns.

    Design/methodology/approach – In order to address these critical concerns, a framework based on optionsreasoning borrowed from corporate finance is proposed and adapted to evaluation of security architecture anddecision-making for handling these issues at organizational level. The adaptation as a methodology is demonstrated by a large case study validating its efficacy.

    Findings – The paper shows through three examples that it is possible to have a coherent methodology, buildingon options theory to deal with uncertainty issues in information security at an organizational level.

    Practical implications – To validate the efficacy of the methodology proposed in this paper, it was applied tothe SHS (Spridnings- och Hämtningssystem: Dissemination and Retrieval System) system. The paper introduces themethodology, presents its application to the SHS system in detail and compares it to the current practice.

    Originality/value – This research is relevant to information security management in organizations, particularlyissues on changing requirements and evaluation in uncertain circumstances created by progress in technology.

  • 3.
    Abbas, Haider
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Magnusson, Christer
    Department of Computer and System Sciences, Stockholm University, Sweden.
    Yngström, Louise
    Department of Computer and System Sciences, Stockholm University, Sweden.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Architectural Description of an Automated System for Uncertainty Issues Management in Information Security2010Ingår i: International Journal of Computer Science and Information Security, ISSN 1947-5500, Vol. 8, nr 3, 89-67 s.Artikel i tidskrift (Refereegranskat)
  • 4.
    Abbas, Haider
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Yngström, Louise
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Empowering Security Evaluation of IT Products with Options Theory2009Ingår i: 30th IEEE Symposium on Security & Privacy, Oakland, USA, 2009Konferensbidrag (Refereegranskat)
  • 5. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    High throughput architecture for CLICHÉ network on chip2009Ingår i: Proceedings - IEEE International SOC Conference, SOCC 2009, 2009, 155-158 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    High Throughput Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of High Throughput CLICHÉ switch is decreased by 18% as compared to CLICHÉ switch. The total metal resources required to implement High Throughput CLICHÉ design is increased by 7% as compared to the total metal resources required to implement CLICHÉ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHÉ architecture.

  • 6. Abd El Ghany, M. A.
    et al.
    El-Moursy, M. A.
    Ismail, Mohammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. Ohio State University, Columbus, United States .
    High throughput architecture for high performance NoC2009Ingår i: ISCAS: 2009 IEEE International Symposium on Circuits and Systems, IEEE , 2009, 2241-2244 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.

  • 7.
    Ahmad, Waqar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Core Switching Noise for On-Chip 3D Power Distribution Networks2012Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    Reducing the interconnect size with each technology node and increasing speed with each generation increases IR-drop and Ldi/dt noise. In addition to this, the drive for more integration increases the average current requirement for modern ULSI design. Simultaneous switching of core logic blocks and I/O drivers produces large current transients due to power distribution network parasitics at high clock frequency. The current transients are injected into the power distribution planes thereby inducing noise in the supply voltage. The part of the noise that is caused by switching of the internal logic load is core switching noise. The core logic switches at much higher speed than driver speed whereas the package inductance is less than the on-chip inductance in modern BGA packages. The core switching noise is currently gaining more attention for three-dimensional integrated circuits where on-chip inductance is much higher than the board and package inductance due to smaller board, and package. The switching noise of the driver is smaller than the core switching noise due to small driver size and reduced capacitance associated with short on-board wires for three-dimensional integrated circuits. The load increases with the addition of each die. The power distribution TSV pairs to supply each extra die also introduce additional parasitic. The core switching noise may propagate through substrate and consequently through interconnecting TSVs to different dies in heterogeneous integrated system. Core switching noise may lead to decreased device drive capability, increased gate delays, logic errors, and reduced noise margins. The actual behavior of the on-chip load is not well known in the beginning of the design cycle whereas altering the design during later stages is not cost effective. The size of a three-dimensional power distribution network may reach billions of nodes with the addition of dies in a vertical stack. The traditional tools may run out of time and memory during simulation of a three-dimensional power distribution network whereas, the CAD tools for the analysis of 3D power distribution network are in the process of evolution. Compact mathematical models for the estimation of core switching noise are necessary in order to overcome the power integrity challenges associated with the 3D power distribution network design. This thesis presents three different mathematical models to estimate core switching noise for 3D stacked power distribution networks. A time-domain-based mathematical model for the estimation of design parameters of a power distribution TSV pair is also proposed. Design guidelines for the estimation of optimum decoupling capacitance based on flat output impedance are also proposed for each stage of the vertical chain of power distribution TSV pairs. A mathematical model for tradeoff between TSV resistance and amount of decoupling capacitance on each DRAM die is proposed for a 3D-DRAM-Over-Logic system. The models are developed by following a three step approach: 1) design physical model, 2) convert it to equivalent electrical model, and 3) formulate the mathematical model based on the electrical model. The accuracy, speed and memory requirement of the proposed mathematical model is compared with equivalent Ansoft Nexxim models.

  • 8.
    Ahmad, Waqar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Decoupling capacitance for the power integrity of 3D-DRAM-over-logic system2012Ingår i: IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011, IEEE conference proceedings, 2012, 590-594 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    The 3D-DRAM stacked over the processor is a vibrant technique in order to overcome the memory wall as well as the bandwidth wall problems. We considered a system with two DRAM dies over a single processor die. We assumed the decoupling capacitors to be placed on each DRAM die and connected to the power distribution TSV pairs, where the TSVs pass through the DRAM stack. In this paper we proposed a mathematical model for the optimum value of the decoupling capacitance on each DRAM die along with the optimum values of the effective resistance of the interconnecting power distribution TSV pairs in order to ensure the power integrity of the logic load during switching. The proposed model has a maximum of 1.1% error as compared to the Ansoft Nexxim4.1.

  • 9.
    Ahmad, Waqar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Modeling of peak-to-peak core switching noise, output impedance, and decoupling capacitance along a vertical chain of power distribution TSV pairs2012Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 73, nr 1, 311-328 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this article we propose an efficient and accurate model to estimate peak-to-peak core switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of dies interconnected through TSVs. The proposed model is accurate with only a 2–3% difference in peak-to-peak core switching noise as compared to the Ansoft Nexxim4.1 equivalent model. The proposed model is 3–4 times faster than Ansoft Nexxim4.1 and uses two times less memory as compared to the Ansoft Nexxim4.1 equivalent model. In this article we also thoroughly establish design guidelines for almost flat output impedance magnitude at each stage of a vertical chain of power distribution TSV pairs to realize a resonance free scenario over a wide operating frequency range. We also establish decoupling capacitance design guidelines based on the optimum output impedance and critically damped supply voltage for the core logic for each stage of a vertical chain of power distribution TSV pairs.

  • 10.
    Ahmad, Waqar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs2010Ingår i: 28th Norchip Conference, NORCHIP 2010, 2010, 5669473Konferensbidrag (Refereegranskat)
    Abstract [en]

    On-chip power supply noise has become a bottleneck in 3D ICs as scaling of the supply network impedance has not been kept up with increasing device densities and operating currents with each technology node due to limited wire resources. In this paper we proposed an efficient and accurate model to estimate peak-to-peak switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of ICs. The proposed model is quite accurate with only 2-3% difference from Ansoft Nexxim4.1 equivalent model. The proposed model is 3-4 times faster than Nexxim4.1 as well as consumes two times less memory as compared to Nexxim4.1equivalent model. We analyzed peak-to-peak switching noise along a vertical chain of power distribution TSV pairs by varying physical dimensions of TSVs and value of decoupling capacitance. We also thoroughly investigated the peak-to-peak noise sensitivity to TSV effective inductance and decoupling capacitance.

  • 11.
    Ahmad, Waqar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Peak-to-peak Switching Noise and LC Resonance on a Power Distribution TSV Pair2010Ingår i: 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, Institute of Electrical and Electronics Engineers (IEEE), 2010, 173-176 s., 5642574Konferensbidrag (Refereegranskat)
    Abstract [en]

    How peak-to-peak switching noise as well as the LC resonance term varies by varying different circuit parameters of a power distribution TSV pair (having decoupling capacitance and logic load), within a 3D stack of ICs interconnected through TSVs.

  • 12.
    Ahmad, Waqar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Kanth, Rajeev Kumar
    Turku Centre for Computer Science .
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Fast Transient Simulation Algorithm for a 3D Power distribution Bus2010Ingår i: Proceedings of IEEE Asia Symposium on Quality Electronic Design, 2010, 343-350 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    Extensive transient simulations for on-chip power delivery networks are required to analyze power delivery fluctuations caused by dynamic IR and Ldi/dt drops. Speed and memory has become a bottleneck for simulation of power distribution networks in modern VLSI design where clock frequency is of the order of GHz. The traditional SPICE based tools are very slow and consume a lot of memory during simulation. The problem is further aggravated for huge networks like power distribution network within a stack of ICs inter-connected through TSVs. This type of 3D power distribution network may contain billions of nodes at a time. In this paper we proposed a faster transient simulation algorithm using visual C++. First we reduce 3D power distribution bus containing n nodes to a two terminal 7 network. Then we solve this two terminal reduced network for voltages and currents. After this, we apply back solving algorithm to the network to solve it for each of the intermediate nodes using visual C++. The proposed algorithm is quite accurate with 1-2% error when compared with Ansoft Nexxim4.1. The proposed algorithm is several times faster than Ansoft Nexxim as well as consumes significantly less memory as compared to Nexxim.

  • 13.
    Ahmad, Waqar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Kanth, Rajeev Kumar
    Turku Centre for Computer Science .
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Power distribution TSVs induced core switching noise2011Ingår i: Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE, IEEE conference proceedings, 2011Konferensbidrag (Refereegranskat)
    Abstract [en]

    Size of on-chip interconnects as well as the supply voltage is reducing with each technology node whereas the operating speed is increasing in modern VLSI design. Today, the package inductance and resistance has been reduced to such an extent that core switching noise caused by on-chip inductance and on-chip resistance is gaining importance as compared to I/O drivers switching noise. Both on-chip inductance and skin effect are prime players at frequencies of the order of GHz. The problem is further aggravated when chips are interconnected through TSVs to form a 3D integrated stack in order to achieve low form factor and high integration density. In this paper we analysed peak core switching noise in a 3D stack of integrated chips interconnected through power distribution TSV pairs, through our comprehensive mathematical model which has been proved to be quite accurate as compared to SPICE. We analysed the effect of number of chips in a 3D stack, rise time, decoupling capacitance, and skin effect on power distribution TSVs induced core switching noise in this paper.

  • 14.
    Ahmad, Waqar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Switching Noise in 3D Power Distribution Networks: an Overview2012Ingår i: VLSI  design / [ed] Esteban Tlelo-Cuautle, Sheldon Tan, Intech , 2012, 209-224 s.Kapitel i bok, del av antologi (Refereegranskat)
  • 15.
    Ahmad, Waqar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Peak-to-Peak Ground Noise on a Power Distribution TSV Pair as a Function of Rise Time in 3-D Stack of Dies Interconnected Through TSVs2011Ingår i: IEEE Transactions on Components Packaging and Manufacturing Technology, ISSN 2156-3950, Vol. 1, nr 2, 196-207 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Supply grids of integrated chips are interconnected through through-silicon vias (TSVs) in modern design techniques to form a 3-D stack in vertical direction. The load on each chip is supplied through (power/ground) TSV pairs. Accurate estimation of power/ground noise on each TSV pair of a 3-D power distribution network is necessary for a robust power supply design. The worst case noise obtained with fast switching characteristics may not be significantly accurate. The behavior of power/ground noise as a function of rise time for an inductive power distribution TSV pair with decoupling capacitance, is investigated in this paper. An equivalent rise time corresponding to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. In addition noise sensitivity to decoupling capacitance and TSV inductance is evaluated as a function of rise time. We also discuss noise accumulation as a result of worst case damping factor in this paper.

  • 16. Aktas, Adem
    et al.
    Jonsson, Fredrik
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Ahola, Rami
    Ismail, Mohammed
    A 4 Ghz 0.18um CMOS PLL Frequency Synthesizer withWide-Band VCO for Multi-Standard Wireless Applications2003Ingår i: Proc. 22nd Norchip Conference, 2003, 248-251 s.Konferensbidrag (Refereegranskat)
  • 17.
    Al-Khatib, Iyad
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Bertozzi, Davide
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Benini, Luca
    Performance Analysis and Design Space Exploration for High-End Biomedical Applications: Challenges and Solutions2007Ingår i: Proceedings of the International Conference on Hardware - Software Codesign and System Synthesis, 2007, 217-226 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    High-end biomedical applications are a good target for specific-purpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring andanalysis is an immediate example with a large potential market. Today, the lack of scalable hardware platforms limits real-time analysis capabilities of most portable ECG analyzers, and prevents the upgrade of analysis algorithms for better accuracy. Multiprocessor system-on-chip (MPSoC) technology, which is becoming main-stream in the domain of high-performance microprocessors, is becoming attractive even for power-constrained portable applications, due to the capability to provide scalable computation horsepower at an affordable power cost. This paper illustrates one of the first comprehensive HW/SW exploration frameworks to fully exploit MPSoC technology to improve the quality of real-time ECG analysis.

  • 18.
    Amin, Yasar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Printable Green RFID Antennas for Embedded Sensors2013Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    In the recent years, radio-frequency identification (RFID) technology has been widely integrated into modern society applications, ranging from barcode successor to retail supply chain, remote monitoring, detection and healthcare, for instance. In general, an RFID tag or transponder is composed of an antenna and an application-specific integrated circuit chip. In a passive UHF RFID system (which is the focus of presented research), the communication between the transponder tag and the reader is established by modulating the radar cross section (RCS) of the transponder tag. The need for flexible RFID tags has recently been increased enormously; particularly the RFID tags for the UHF band ensure the widest use but in the meantime face considerable challenges of cost, reliability and environmental friendliness.

    The multidimensional focus of the aforementioned research encompasses the production of low-cost and reliable RFID tags. The state-of-the-art fabrication methods and materials for proposed antennas are evaluated in order to surmount the hurdles for realization of flexible green electronics. Moreover, this work addresses the new rising issues interrelated to the field of economic and eco-friendly tags comprising of paper substrate. Paper substrates offer numerous advantages for manufacturing RFID tags, not only is paper extensively available, and inexpensive; it is lightweight, recyclable and can be rolled or folded into 3D configurations.

    The most important aspect of an RFID system's performance is the reading range. In this research several pivotal challenges for item-level tagging, are resolved by evolving novel structures of progressive meander line, quadrate bowtie and rounded corner bowtie antennas in order to maximize the reading distance with a prior selected microchip under the various constraints (such as limited antenna size, specific antenna impedance, radiation pattern requirements). This approach is rigorously evolved for the realization of innovative RFID tag antenna which has incorporated humidity sensor functionality along with calibration mechanism due to distinctiveness of its structural behavior which will be an optimal choice for future ubiquitous wireless sensor network (WSN) modules.

    The RFID market has grown in a two-dimensional trend, one side constitutes standalone RFID systems. On the other side, more ultramodern approach is paving its way, in which RFID needs to be integrated with broad operational array of distinct applications for performing different functions including sensors, navigation, broadcasting, and personal communication, to mention a few. Using different antennas to include all communication bands is a straightforward approach, but at the same time, it leads to increase cost, weight, more surface area for installation, and above all electromagnetic compatibility issues. The indicated predicament is solved by realization of proposed single wideband planar spirals and sinuous antennas which covers several bands from 0.8-3.0GHz. These antennas exhibit exceptional performance throughout the operational range of significance, thus paving the way for developing eco-friendly multi-module RF industrial solutions.

  • 19.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Evolutionary Versatile Printable RFID Antennas For "Green" Electronics2012Ingår i: Journal Electromagnetic Waves and Applications, ISSN 0920-5071, E-ISSN 1569-3937, Vol. 26, nr 2-3, 264-273 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The development of low cost directly printable RFID tag antennas is essential for item level tracking. We present evolutionary design approach to achieve robust extremely versatile RFID antennas on paper/flexible substrates which allow a simple integration directly on, e.g., paperboard in a roll-to-roll production line. Fully integrated printed tags for "green" electronics are designed for operability in frequencies 866-868 MHz & 902-928 MHz. We present benchmarking results for various challenges of antennas in terms of ruggedness, reliability and flexing performance.

  • 20.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Performance-Optimized Quadrate Bowtie RFID Antennas For Cost-Effective and Eco-Friendly Industrial Applications2012Ingår i: Progress in Electromagnetics Research-PIER, ISSN 1559-8985, Vol. 126, 49-64 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Fully integrated printed RFID antennas show potential solution for item level labeling applications. In order to accommodate the antenna during the package printing process, it is vastly preferred that antenna structures are printed on paper substrates. However, the electromagnetic properties and thickness of paper substrates are susceptible to change due to various environmental effects. Thus, adequately consistent in performance and material insensitive printed Quadrate Bowtie RFID antennas are proposed. This paper presents an in-depth efficient optimization for high performance tag antenna designs for operability in frequencies 866-868MHz & 902-928MHz. It is demonstrated that the proposed antennas can tolerate a considerable variation in the permittivity on thin paper substrates, and present benchmarking results when n across metal and water containing objects.

  • 21.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Design and Fabrication of Wideband Archimedean Spiral Antenna Based Ultra-Low Cost "Green" Modules for RFID Sensing and Wireless Applications2012Ingår i: Progress In Electromagnetics Research-PIER, ISSN 1559-8985, Vol. 130, 241-256 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    A parametric analysis is performed for a wideband Archimedean spiral antenna in recognition of an emerging concept to integrate RFID along with several applications by using a single antenna. The antenna is fabricated using state-of-the-art inkjet printing technology on various commercially available paper substrates to provide the low-cost, flexible RF modules for the next generation of "green" electronics. The effects on electromagnetic characteristics of the planar Archimedean spiral antenna, due to the use of paper are investigated besides other parameters. The proposed antenna is evaluated and optimized for operational range from 0.8-3.0GHz. It exhibits exceptional coverage throughout numerous RFID ISM bands so do for other wireless applications.

  • 22.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Development and Analysis of Flexible UHF RFID Antennas For "Green" Electronics2012Ingår i: Progress In Electromagnetics Research-PIER, ISSN 1070-4698, Vol. 130, 1-15 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper, novel Bowtie antennas which cover complete UHF RFID band (860-960MHz), fabricated on various ultra-low-cost substrates using state-of-the-art printing technologies are investigated as an approach that aims to accommodate the antenna during the package printing process whilst faster production on commercially available paper. The proposed antenna structures are evaluated in reference to circuit and field concepts, to exhibit extreme degree of functional versatility. These antennas are developed to cater the variations which appear in electromagnetic properties and thickness of paper substrate due to various environmental effects. Computed (simulated) and well-agreed measurement results confirm a superior performance of the tag modules while stepping towards next generation of "green" tags.

  • 23.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    "Green" Wideband Log-Spiral Antenna for RFID Sensing and Wireless Applications2012Ingår i: Journal of Electromagnetic Waves and Applications, ISSN 0920-5071, Vol. 26, nr 14-15, 2043-2050 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The novel idea of integrating RFID with sensors along with other wireless applications by using single tag antenna is implemented, by fabricating proposed antenna using state-of-the-art inkjet printing technology on commercially available paper substrates. For the first time, a parametric analysis is performed for realization of planar log-spiral antenna on paper for operational range from 0.8-3.0GHz, which also exhibits excellent coverage throughout numerous RFID ISM bands, and for other wireless applications. The ANSYS HFSS tool is used to design and predict the performance of the proposed antenna in terms of radiation pattern and input impedance.

  • 24.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Two-arm Sinuous Antenna for RFID Ubiquitous Sensors and Wireless Applications2012Ingår i: Journal Electromagnetic Waves and Applications, ISSN 0920-5071, E-ISSN 1569-3937, Vol. 26, nr 17-18, 2365-2371 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    For the first time, two-arm planar sinuous antenna is demonstrated to realize the emerging concept of integrating RFID functionalities along with sensors and other wireless applications for "green" electronics. In-depth, parametric analysis is performed for the proposed antenna which is fabricated on a paper substrate using revolutionary inkjet printing technology to develop a system-level solution for ultra-low-cost mass production of multipurpose wireless tags in an approach that could be easily expanded to other microwave and wireless "cognition" applications. The proposed antenna exhibits excellent performance throughout several RFID ISM bands and for other wireless applications in its operational range from 0.8 to 3.0 GHz.

  • 25.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Feng, Yi
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    RFID antenna humidity sensor co-design for USN applications2013Ingår i: IEICE Electronics Express, ISSN 1349-2543, Vol. 10, nr 4, 20130003- s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    We demonstrate for the first time an RFID tag antenna which itself is humidity sensor and also provides calibration functionality. The antenna is comprised of T-matching network and horizontally meandered lines for impedance matching and reliable near-field communication. The novel contour design provides humidity sensing, and calibration functions whilst concurrently acts as a radiating element along with quadrangular capacitive tip-loading with covered middle portion for far-field communication. The inkjet printed prototypes of the antenna provide effective ambient humidity sensing while demonstrating stable RFID communication. The antenna has a compact size of 1.1 x 10.2 cm for 902-928MHz band.

  • 26.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hållstedt, Julius
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Design of Novel Paper-based Inkjet Printed Rounded Corner Bowtie Antenna for RFID Applications2010Ingår i: Sensors & Transducers Journal, ISSN 1726-5479, Vol. 115, nr 4, 160-167 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents a novel inkjet printed rounded corner bowtie antenna with T-matching stubs on paper substrate which is the cheapest and widest available substrate. The antenna exhibits compact size with outstanding read range and complete coverage of UHF RFID band (860-960 MHz). The results show extreme immunity of proposed antenna against paper dielectric constant variation.

  • 27.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Kanth, R. K.
    Liljeberg, P.
    Akram, A.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Printable RFID antenna with embedded sensor and calibration functions2013Ingår i: Progress In Electromagnetics Research Symposium Proceedings, Stockholm, Sweden, Aug. 12-15, 2013, Electromagnetics Academy , 2013, 567-570 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    An RFID antenna with integrated humidity sensor and calibration functionality for wireless sensor network is proposed. The antenna is composed of series and shunt stubs for impedance matching and reliability for near-field communication. The innovative ladder contour structure plays the key role for humidity sensing, and sensor calibration. The quadrangular end-tip loading is employed to offer capacitance and stability for far-field communication. The prototypes of the antenna are fabricated and tested: antenna effectively senses the ambient humidity levels while demonstrating stable behavior for RFID communication. The antenna has a compact size of 1 × 10cm for 902-928 MHz RFID band.

  • 28.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Kanth, Rajeev Kumar
    Turku Centre for Computer Science (TUCS).
    Liljeberg, Pasi
    Turku Centre for Computer Science (TUCS).
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Green wideband RFID tag antenna for supply chain applications2012Ingår i: IEICE Electronics Express, ISSN 1349-2543, Vol. 9, nr 24, 1861-1866 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper, we demonstrate an RFID tag antenna manufactured by advanced inkjet printing technology on paper substrate using novel hole-matching technique for reducing the consumption of substrate material and conductive ink while attaining green RFID tags. In-depth electromagnetic analysis is performed methodologically for optimizing the parameters that effectuate the antenna dimensions. The antenna design is optimized for consistent wideband performance and extended read range throughout the complete UHF RFID band (860-960MHz), while exhibiting benchmarking results when n across cardboard cartons filled with metal or water containing objects.

  • 29.
    Amin, Yasar
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Kumar Kanth, Rajeev
    University of Turku, Finland.
    Liljeberg, Pasi
    University of Turku, Finland.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Performance-optimized Printed Wideband RFID Antenna and Environmental Impact AnalysisIngår i: ETRI Journal, ISSN 1225-6463, E-ISSN 2233-7326Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents performance optimized RFID tag antenna, developed by using commercially accessible paper substrates and advanced inkjet printing process to guarantee mechanical flexibility and ultra-low production costs. The proposed antenna structure can endure the variations which emerge in electromagnetic properties of paper substrate due to varying environmental effects. Hole-matching technique is implemented to eliminate the matching network for reducing the consumption of conductive ink. The proposed structure is uniquely evaluated by demonstrating, sustainability and environmental impact analysis that validate the potential for ultra-low cost mass production of RFID tags for future generation of organic electronics. The antenna performance is assessed for cardboard cartons exclusively containing metal cans and water bottles. The experimental characterization of the proposed antenna endorses the wider bandwidth to cover UHF RFID ISM band (860-960MHz), which empowers its usage throughout the globe for supply chain applications. The improved design effectuates return loss of better than -15dB over a wide frequency range while exhibiting outstanding readability from 10.1 meters.

  • 30.
    Amin, Yasar
    et al.
    University of Engineering and Technology, Taxila, Punjab, Pakistan.
    Shao, Botao
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Electromagnetic Analysis of Radio Frequency Identification Antennas for Green Electronics2013Ingår i: Electromagnetics, ISSN 0272-6343, E-ISSN 1532-527X, Vol. 33, nr 4, 319-331 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This article demonstrates in-depth electromagnetic analysis of a radio frequency identification tag antenna manufactured by inkjet printing technology on different paper substrates to achieve ultra-low cost flexible radio frequency identification tags using a novel hole-matching technique for reducing the consumption of substrate material, and conductive ink. Nevertheless, the electromagnetic properties of the paper substrate are vulnerable to various environmental effects. Thus, the proposed antenna design is optimized for consistent wideband performance throughout the complete UHF radio frequency identification band (860960 MHz) while presenting a greater degree of material insensitivity. An advanced antenna design methodological analysis is performed to accomplish an extended read range, while exhibiting benchmarking results when across cardboard cartons filled with metal or water containing objects.

  • 31. Anagnostopoulos, I.
    et al.
    Chabloz, Jean-Michel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Koutras, I.
    Bartzas, A.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Soudris, D.
    Power-Aware Dynamic Memory Management on Many-Core Platforms Utilizing DVFS2013Ingår i: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 13, nr 1, 40- s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Today multicore platforms are already prevalent solutions for modern embedded systems. In the future, embedded platforms will have an even more increased processor core count, composing many-core platforms. In addition, applications are becoming more complex and dynamic and try to efficiently utilize the amount of available resources on the embedded platforms. Efficient memory utilization is a key challenge for application developers, especially since memory is a scarce resource and often becomes the system's bottleneck. To cope with this dynamism and achieve better memory footprint utilization (lowmemory fragmentation) application developers resort to the usage of dynamic memory (heap) management techniques, by allocating and deallocating data at runtime. Moreover, overall power consumption is another key challenge that needs to be taken into consideration. Towards this, designers employ the usage of Dynamic Voltage and Frequency Scaling (DVFS) mechanisms, adapting to the application's computational demands at runtime. In this article, we propose the combination of dynamic memory management techniques with DVFS ones. This is performed by integrating, within thememorymanager, runtimemonitoringmechanisms that steer the DVFSmechanisms to adjust clock frequency and voltage supply based on heap performance. The proposed approach has been evaluated on a distributed shared-memory many-core platform composed of multiple LEON3 processors interconnected by a Network-on-Chip infrastructure, supporting DVFS. Experimental results show that by using the proposed method for monitoring and applying DVFS mechanisms the power consumption concerning dynamic memory management was reduced by approximately 37%. In addition we present the trade-offs the proposed approach. Last, by combining the developed method with heap fragmentation-aware dynamic memory managers, we achieve low heap fragmentation values combined with low power consumption.

  • 32. Anagnostopoulos, Iraklis
    et al.
    Xydis, Sotirios
    Bartzas, Alexandros
    Lu, Zhonghai
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Soudris, Dimitrios
    Jantsch, Axel
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations2011Ingår i: IEEE Embedded Systems Letters, ISSN 1943-0663, Vol. 3, nr 2, 66-69 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Multiprocessor system-on-chip (MPSoCs) have attracted significant attention since they are recognized as a scalable paradigm to interconnect and organize a high number of cores. Current multicore embedded systems exhibit increased levels of dynamicbehavior, leading to unexpected memory footprint variations unknown at design time.Dynamic memory management (DMM) is a promising solution for such types of dynamicsystems. Although some efficient dynamic memory managers have been proposed for conventional bus-based MPSoC platforms, there are no DMM solutions regarding the constraints and the opportunities delivered by the physical distribution of multiple memorynodes of the platform. In this work, we address the problem of providing customizedmicrocoded DMM on MPSoC platforms with distributed memory organization. Customization is enabled at application-and platform-level. Results show that customizedmicrocoded DMM can serve approximately 7× more allocation requests compared to puredistributed memory platforms and perform 25% faster than the corresponding high-level implementation in C language. 

  • 33.
    Ansari, Muhammad Adeel
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT).
    Ahmad, Waqar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Chen, Qiang
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Diode based charge pump design using 0.35μm technology2010Ingår i: 28th Norchip Conference, NORCHIP 2010, IEEE , 2010, 5669437- s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    A high voltage charge pump design is being presented in this paper. The design is based on Dickson charge pump, constructed with diodes by using AMS 0.35μm technology. The innovation is made in Dickson charge pump i.e. charge control PMOS transistor is used in each stage of charge pump. PMOS transistor is used in series with charging capacitor which reduces the power consumption during the clock transition by controlling the time constant of each stage. The resistance between drain to source of PMOS transistor increases the time constant during the charging of the capacitor placed in each stage of charge pump. The output voltage of about 5.693V is achieved by the six stages of Dickson charge pump at no-load which reduces to 5.537V with the six stages of proposed charge pump but the power during the input clock transition is reduced from 340.5μw (consumed by Dickson charge pump) to 28.85 μW (consumed by the proposed modified charge pump). Some other results are also discussed in this paper, which are achieved on different load resistances.

  • 34.
    Ansari, Muhammad Adeel
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Kommunikation: Infrastruktur och tjänster (Stängd 20120101), Kommunikationssystem, CoS (stängd 2012-01-01).
    Ahmad, Waqar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Signell, Svante R.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Kommunikation: Infrastruktur och tjänster (Stängd 20120101), Kommunikationssystem, CoS (stängd 2012-01-01).
    Single clock charge pump designed in 0.35μm technology2011Ingår i: Proceedings of the 18th International Conference - Mixed Design of Integrated Circuits and Systems, MIXDES 2011, 2011, 552-556 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    An on-chip novel design of a single clock charge pump for high voltage applications is being presented in this paper. The proposed charge pump is designed using AMS 0.35μm technology. Three stages of the proposed charge pump are being used for the results verification and comparing them with the six stages of Dickson charge pump designed with diode connected PMOS. The proposed charge pump gives an output voltage of 5.34V at no-load. The proposed charge pump gives maximum efficiencies of 89% on 1MHz frequency and 87.4% on 5MHz frequency using 1Mohm load resistance. The efficiency and the output voltage including voltage gain per stage of the proposed charge pump are higher than the Dickson charge pump measured under similar conditions mediating that the performance of proposed charge pump is better than the Dickson charge pump.

  • 35. Anwar, Hassan
    et al.
    Jafri, Syed Mohammad Asad Hassan
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sergei, Dytckov
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures2014Ingår i: ACM International Conference Proceeding Series, 2014, 64-67 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    Today, reconfigurable architectures are becoming increas- ingly popular as the candidate platforms for neural net- works. Existing works, that map neural networks on re- configurable architectures, only address either FPGAs or Networks-on-chip, without any reference to the Coarse-Grain Reconfigurable Architectures (CGRAs). In this paper we investigate the overheads imposed by implementing spiking neural networks on a Coarse Grained Reconfigurable Ar- chitecture (CGRAs). Experimental results (using point to point connectivity) reveal that up to 1000 neurons can be connected, with an average response time of 4.4 msec.

  • 36.
    Attarzadeh Niaki, Seyed Hosein
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Managing the Complexity in Embedded and Cyber-Physical System Design: System Modeling and Design-Space Exploration2014Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [sv]

    Den ökande komplexiteten är en stor utmaning för konstruktionen av framtida inbyggda system. För att möta utmaningen utvecklas nu konstruktionsmetoder som har som mål att starta från en abstrakt modell och att generera en implementering genom ett konstruktionsflöde med hög automatiseringsgrad. Dessvärre är dock skapandet av abstrakta systemmodeller och formaliseringen av de relaterade matematiska problemen i sig ett mycket utmanande problem. Konstruktion genom komposition av basenheter är en lovande idé, men tyvärr är det väldigt svårt att introducera metoden i dagens industriella konstruktionsflöden på grund av imperativa programmeringsspråk och ett gammalt arv i form av existerande kodbas och äldre konstruktioner.

    Avhandlingen adresserar komplexiten inom systemkonstruktion genom att föreslå passande formalismer för att uttrycka modeller i en deklarativ stil och angripa problemet att hitta en passande implementering. Dessutom visar avhandlingen hur dessa formalismer kan realiseras i en form som kan användas i ett industriellt sammanhang utan att förlora formalismens viktiga grundläggande egenskaper som komposition och parallelism.

    Modelleringen använder och utökar ForSyDe, en konstruktionsmetod för heterogena inbyggda system. Tilläggen består av en modelleringsmodell som kan fånga specifika egenskaper hos heterogena inbyggda system, samt en implementering av ForSyDe i SystemC, ett industriellt modelleringsspråk som är standardiserat av IEEE. Den nya utvecklingsmiljön, ForSyDe-SystemC, kan användas för att modellera inbyggda system, komponera systemmodeller till större system, samt möjliggör genomförandet av parallella och distribuerade simuleringar med medföljande hög simuleringshastighet. Avhandlingen introducerar också “wrapper”-konceptet i ForSyDe som möjliggör integrationen av existerande modeller och system som en del av en formell ForSyDe-modell och deras co-simulering. ForSyDe-SystemC har använts inom EU-projekt av industriella partner för modellering av egna system.

    Att hitta en korrekt och effektiv implementering av en abstrakt systemmodell är målet inom aktiviteten “design space exploration” (DSE) som är ett svårt problem för parametriserbara och flexibla plattformar. Avhandlingen presenterar två generationer av Tahmuras, som är baserade på villkorsprogrammering och har som mål att konstruera DSE-problemet som en komposition av tre olika delproblem: applikation, plattform, och bindning. Ett integrerat DSE-problem kan sedan automatiskt genereras genom en kombination av dessa delproblem. Olika metoder, från heuristisk till komplett sökning, kan användas inom villkorsprogrammering för att lösa DSE-problemet. För att visa Tahmuras potential har DSE-metoden validerats med hjälp av olika systemapplikationer av skilda tidsegenskaper och olika plattformar. 

  • 37.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Beserra, G. S.
    University of Brasilia.
    Andersen, N.
    Novelda AS.
    Verdon, M.
    DA-Design Oy.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Heterogeneous system-level modeling for small and medium enterprises2012Ingår i: Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on, IEEE conference proceedings, 2012, 1-6 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    The design of today's electronic embedded systems is an increasingly complicated task. This is especially problematic for Small and Medium Enterprises (SMEs) which have limited resources. In this work, we identify a set of common design practices used in industry, with a special focus on problems faced by smaller companies, and formulate them as design scenarios. We show how SMEs can benefit from a system-level design approach by customizing a formal heterogeneous system modeling framework for each scenario. The applicability of this approach is demonstrated by two industrial use cases, an impulse-radio radar and a UART-based protocol.

  • 38.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Cevrero, Alessandro
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Brisk, Philip
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Nicopoulos, Chrysostomos
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Gurkaynak, Frank K.
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Leblebici, Yusuf
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Ienne, Paolo
    Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland.
    Design space exploration for field programmable compressor trees2008Ingår i: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, New York: ACM Press, 2008, 207-216 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device. This paper presents a design space exploration (DSE) method that can be used to identify the best FPCT architecture for a given set of arithmetic benchmark circuits; in practice, an FPGA vendor can use the design space exploration to tailor the FPCT to meet the needs of the most important benchmark circuits of the vendor’s largest-volume clients. One novel feature of the DSE is the introduction of a metric called I/O utilization; we found that I/O utilization has a strong correlation with both the critical path delay and area of the benchmark circuits under study. Pruning the search space using I/O utilization allowed us to reduce significantly the number of FPCTs that must be synthesized and evaluated during the DSE, while giving high confidence that the best architectures are still explored. The DSE was applied to seven small-to-medium range benchmark circuits; one FPCT architecture was found that was 30% faster than the second best in terms of critical path delay, and only 3.34% larger than the smallest.

  • 39.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Jakobsen, M. K.
    Technical University of Denmark.
    Sulonen, T.
    DA-Design Oy.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Formal heterogeneous system modeling with SystemC2012Ingår i: Proceedings of Forum on Specification and Design Languages (FDL) 2012, 2012, 160-167 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    Electronic System Level (ESL) design of embedded systems proposes raising the abstraction level of the design entry to cope with the increasing complexity of such systems. To exploit the benefits of ESL, design languages should allow specification of models which are a) heterogeneous, to describe different aspects of systems; b) formally defined, for application of analysis and synthesis methods; c) executable, to enable early detection of specification; and d) parallel, to exploit the multi- and many-core platforms for simulation and implementation. We present a modeling library on top of SystemC, targeting heterogeneous embedded system design, based on four models of computation. The library has a formal basis where all elements are well defined and lead in construction of analyzable models. The semantics of communication and computation are implemented by the library, which allows the designer to focus on specifying the pure functional aspects. A key advantage is that the formalism is used to export the structure and behavior of the models via introspection as an abstract representation for further analysis and synthesis.

  • 40.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Mikulcak, Marcus
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Robino, Francesco
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    A Framework for Characterizing Predictable Platform Templates2014Rapport (Övrigt vetenskapligt)
    Abstract [en]

    The design of real-time multiprocessor systems is a very costly and time-consuming process due to the need for extensive verification efforts. Genericcorrect-by-construction system-level design flows, targeting predictable plat-forms, would help to tackle this problem. Unfortunately, because system-level design problems are formulated monolithically, existing methods areeither not powerful enough to perform efficient design space exploration,over-customized to a specific class of platforms, or do not allow to be ex-tended with new heuristics and solving methods, which makes their reusedifficult. We present a formal framework to explicitly capture and character-ize predictable platform templates that can be used to formulate a genericdesign flow for real-time streaming applications in a composable manner. Aproof-of-concept implementation of such a flow is performed and used to mapa JPEG encoder application onto an FPGA-based time-predictable platform.

  • 41.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Mikulcak, Marcus
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Automatic Generation of Virtual Prototypes from Platform Templates2015Ingår i: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2013 / [ed] Marie-Minerve Louërat, Torsten Maehne, Switzerland: Springer, 2015, 147-166 s.Kapitel i bok, del av antologi (Refereegranskat)
    Abstract [en]

    Virtual Prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM-2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.

  • 42.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Mikulcak, Marcus
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Rapid virtual prototyping of real-time systems using predictable platform characterizations2013Ingår i: Forum on Specification Design Languages (FDL) 2013, 2013, 6646652- s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    Virtual prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM 2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.

  • 43.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems2013Ingår i: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, 27-30 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    Simulation of complex embedded and cyber-physical systems requires exploitation of the computation power ofavailable parallel architectures. Current simulation environments either do not address this parallelism or use separate models for parallel simulation and for analysis and synthesis, which might lead to model mismatches. We extend a formal modeling framework targeting heterogeneous systems with elements that enable parallel simulations. An automated flow is then proposed that starting from a serial executable specification generates an efficient MPI-based parallel simulation model by using aconstraint-based method. The proposed flow generates parallel models with acceptable speedups for a representative example.

  • 44.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Co-simulation of embedded systems in a heterogeneous MoC-based modeling framework2011Ingår i: 2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES): Proceedings of a meeting held 15-17 June 2011, Vasteras, Sweden., IEEE Press, 2011, 238-247 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    New design methodologies and modeling frameworks are required to provide a solution for integrating legacy code and IP models in order to be accepted in the industry. To tackle this problem, we introduce the concept of wrappers in the context of a formal heterogeneous embedded system modeling framework. The formalism is based on the language-independent concept of models of computation. Wrappers enable the framework to co-simulate/co-execute with external models which might be legacy code, an IP block, or an implementation of a partially refined system. They are defined formally in order to keep the analyzability of the original framework and also enable automations such as generation of model wrappers and co-simulation interfaces. As a proof of concept, three wrappers for models in different abstraction levels are introduced and implemented for two case studies.

  • 45.
    Attarzadeh Niaki, Seyed Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Semi-formal refinement of heterogeneous embedded systems by foreign model integration2011Ingår i: 2011 Forum on Specification and Design Languages (FDL), IEEE conference proceedings, 2011, 179-186 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    There is a need for integration of external models in high-level system design flows. We introduce a set of partial refinement operations to implement models of heterogeneous embedded systems. The models are in form of process networks where each process belongs to a single model of computation. A semi-formal design flow has been introduced based on these operations to incrementally refine system specifications to their implementation. Wrapper processes, which allow co-simulation of a system model in the framework with external models and implementations are used to keep the intermediate system models after each refinement step verifiable. Additionally, this design flow has the advantage of integrating legacy code and IP cores. Using a simple example as the case study, we have shown how we can apply this design methodology to a simple system.

  • 46.
    Attarzadeh-Niaki, Seyed-Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    An extensible modeling methodology for embedded and CPS designManuskript (preprint) (Övrigt vetenskapligt)
    Abstract [en]

    Abstract models are important tools to manage the increasing complexity of system design. The choice of a modeling language for constructing models governs what types of systems can be modeled and which subsequent design activities can be performed. This is especially true for the area of embedded electronic and cyber-physical system design, which poses several challenging requirements on modeling and design methodologies. This article argues that the ForSyDe methodology with the necessary extensions can fulfill these requirements and thus qualifies for the design of tomorrow’s systems. Based on the theory of models of computation and the concept of process constructors, heterogeneous models are captured in ForSyDe with precise semantics. A refined layer of the formalism is introduced to make its denotational-style semantics easy to implement on top of the commonly used imperative languages and an open-source realization on top of the IEEE standard language SystemC is reported. The introspection mechanism is introduced to automatically export an intermediate representation of the constructed models for further analysis/synthesis by external tools. Flexibility and extensibility of ForSyDe is emphasized by integrating a new timed model of computation without central synchronization, and providing mechanisms for integrating foreign models, parallel and distributed simulation, modeling adaptive, data-parallel, and non-deterministic systems. A set of ForSyDe features are demonstrated in practice and compared to similar approaches using two relevant case studies. 

  • 47.
    Attarzadeh-Niaki, Seyed-Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    An extensible modeling methodology for embedded and cyber-physical system design2016Ingår i: Simulation (San Diego, Calif.), ISSN 0037-5497, E-ISSN 1741-3133, Vol. 92, nr 8, 771-794 s.Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    models are important tools to manage the increasing complexity of system design. The choice of a modeling language for constructing models governs what types of systems can be modeled, and which subsequent design activities can be performed. This is especially true for the area of embedded electronic and cyber-physical system design, which poses several challenging requirements of modeling and design methodologies. This article argues that the Formal System Design (ForSyDe) methodology with the necessary presented extensions fulfills these requirements, and thus qualifies for the design of tomorrow's systems. Based on the theory of models of computation and the concept of process constructors, heterogeneous models are captured in ForSyDe with formal semantics. A refined layer of the formalism is introduced to make its denotational-style semantics easy to implement on top of commonly used imperative languages, and an open-source realization on top of the IEEE standard language SystemC is presented. The introspection mechanism is introduced to automatically export an intermediate representation of the constructed models for further analysis/synthesis by external tools. Flexibility and extensibility of ForSyDe is emphasized by integrating a new timed model of computation without central synchronization, and by providing mechanisms for integrating foreign models, parallel and distributed simulation, modeling adaptive, data-parallel, and non-deterministic systems. A set of ForSyDe features is demonstrated in practice, and compared with similar approaches using a running example and two relevant case studies.

  • 48.
    Attarzadeh-Niaki, Seyed-Hosein
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Sander, Ingo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Automatic Construction of Models for Analytic Design Space Exploration ProblemsManuskript (preprint) (Övrigt vetenskapligt)
    Abstract [en]

    Due to the variety of application semantics and also the target platforms used in embedded electronic system design, it is challenging to propose a generic and extensible analytic design-space exploration (DSE) framework. Current approaches support a restricted class of application and platform models and are difficult to extend. This paper proposes a framework to capture the system functionality, a flexible target platform, and a binding policy explicitly using coherent constraint-based representations; together with a method for automatic construction of DSE problem models from them. Heterogeneous semantics is captured using constraints on logical clocks. The applicability of this method is demonstrated by constructing DSE problem models from various combinations of application and platforms models. Time-triggered and untimed models of the system functionality and heterogeneous target platforms are used for this purpose. The constructed models can be solved using different solvers and heuristics. 

  • 49.
    Badawi, Mohammad
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    A Coarse-Grained Reconfigurable Protocol Processor2011Ingår i: International Symposium on System-on-Chip, 2011. Proceedings, 2011Konferensbidrag (Refereegranskat)
    Abstract [en]

    Trade-off between flexibility and performance became an important factor for characterizing modern protocol processing architectures. While some solutions tend to be more flexible and less computational efficient like GPPs, other solutions like custom ASIC devices provide high computational efficiency while loosing the ability to cope with the diversity of current and evolving protocols. We propose a reconfigurable protocol processor that is flexible and highly adaptable to the needs of the required protocol with the ability to operate individually or as a multi-core integrating processors. We show how a common protocol processing task that consumes one third of RISC CPU time can be performed on our processor at high speed and low energy cost.

  • 50.
    Badawi, Mohammad
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Hemani, Ahmed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Lu, Zhonghai
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Customizable Coarse-grained Energy-efficient Reconfigurable Packet Processing Architecture2014Ingår i: Proceedings Of The 2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), IEEE , 2014, 30-35 s.Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, we present a highly customizable and rapidly reconfigurable multi-core packet processing architecture that provides energy and area efficiency while retaining flexibility. Presented architecture with its agile reconfigurability permits time-critical adaptability where resources can be re-clustered at run time in few cycles, hence, maintaining efficiency if requirements of the use-case change. We elaborate the flexibility and adaptability of our architecture and we report its evaluation results. For evaluation, we performed the widely-used UDP/IP and we compared our proposed architecture to low-power 32-bit general purpose processors, a custom ASIC implementation and a programmable protocol processor. Compared to GPP-based solutions, our architecture is 20-34 times more energy efficient while providing 2.4-4.1 times higher throughput. While retaining the programmability, the proposed solution achieved 78% of the energy efficiency of hardwired ASIC implementation. Compared to a programmable protocol processor, our solution has 2.6 times more throughput and requires only a third of the gate count. lastly, we quantified the worst-case time and average-case time required for time-critical adaptability when reconfiguration occurs during a real-life Voice-Over IP traffic.

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