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  • 1.
    Ahlberg, Patrik
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Seung, Hee Jeong
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Jiao, Mingzhi
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Microsystems Technology.
    Wu, Zhigang
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Microsystems Technology.
    Zhang, Shi-Li
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Zhang, Zhi-Bin
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Graphene as a Diffusion Barrier in Galinstan-Solid Metal Contacts2014In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 61, no 8, p. 2996-3000Article in journal (Refereed)
    Abstract [en]

    This paper presents the use of graphene as a diffusion barrier to a eutectic Ga-In-Sn alloy, i.e., galinstan, for electrical contacts in electronics. Galinstan is known to be incompatible with many conventional metals used for electrical contacts. When galinstan is in direct contact with Al thin films, Al is readily dissolved leading to the formation of Al oxides present on the surface of the galinstan droplets. This reaction is monitored ex situ using several material analysis methods as well as in situ using a simple circuit to follow the time-dependent resistance variation. In the presence of a multilayer graphene diffusion barrier, the Al-galinstan reaction is effectively prevented for galinstan deposited by means of drop casting. When deposited by spray coating, the high-impact momentum of the galinstan droplets causes damage to the multilayer graphene and the Al-galinstan reaction is observed at some defective spots. Nonetheless, the graphene barrier is likely to block the formation of Al oxides at the Al/galinstan interface leading to a stable electrical current in the test circuit.

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  • 2.
    Ankarcrona, Johan
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Vestling, Lars
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Eklund, Klas-Håkan
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Olsson, Jörgen
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Low Resistivity SOI for Substrate Crosstalk Reduction2005In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, IEEE Trans on Electronic Devices, Vol. 52, no 8, p. 1920-1922Article in journal (Refereed)
  • 3.
    Ankarcrona, Johan
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Vestling, Lars
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Eklund, Klas-Håkan
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Olsson, Jörgen
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Low Resistivity SOI for Substrate Crosstalk Reduction2005In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 52, no 8, p. 1920-1922Article in journal (Refereed)
  • 4.
    Bakowski, Mietek
    et al.
    RISE, Swedish ICT, Acreo.
    Ranstad, P.
    Alstom Power Sweden AB, Sweden.
    Lim, Jang-Kwon
    RISE, Swedish ICT, Acreo.
    Kaplan, Wlodek
    RISE, Swedish ICT, Acreo. Ascatron AB, Sweden.
    Reshanov, Sergey
    RISE, Swedish ICT, Acreo. Ascatron AB, Sweden.
    Schoner, Adolf
    RISE, Swedish ICT, Acreo. Ascatron AB, Sweden.
    Giezendanner, F.
    Alstom Power Sweden AB, Sweden.
    Ranstad, A.
    Alstom Power Sweden AB, Sweden.
    Design and characterization of newly developed 10 kV 2 A SiC p-i-n diode for soft-switching industrial power supply2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 2, p. 366-373Article in journal (Refereed)
    Abstract [en]

    10 kV, 2 A SiC p-i-n diodes have been designed and fabricated. The devices feature excellent stability of forward characteristics and robust junction termination with avalanche capability of 1 J. The fabricated diodes have been electrically evaluated with respect to dynamic ON-state voltage, reverse recovery behavior, bipolar stability, and avalanche capability. More than 60% reduction of losses has been demonstrated using newly developed 10-kV p-i-n diodes in a multikilowatt high voltage, high-frequency dc/dc soft-switching converter

  • 5.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Vestling, Lars
    Solid State Electronics, Ångström Laboratory, Uppsala University, Uppsala, Sweden.
    Olsson, Jörgen
    Solid State Electronics, Ångström Laboratory, Uppsala University, Uppsala, Sweden.
    Investigation of SOI-LDMOS for RF-Power Applications Using Computational Load Pull2009In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 56, no 3, p. 505-511Article in journal (Refereed)
    Abstract [en]

    Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the OFF-state out put resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simu lations. It is shown that, albeit high OFF-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed ON-state analysis necessary. It is shown that very low resistivity and high resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.

  • 6.
    Bengtsson, Olof
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Vestling, Lars
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Olsson, Jörgen
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Investigation of SOI-LDMOS for RF-power applications using Computational Load-Pull2009In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 56, no 3, p. 505-511Article in journal (Refereed)
    Abstract [en]

    Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on-insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the OFF-state output resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simulations. It is shown that, albeit high OFF-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed ON-state analysis necessary. It is shown that very low resistivity and high-resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.

  • 7.
    Bergsten, Johan
    et al.
    Chalmers, Sweden.
    Chen, Jr-Tai
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering.
    Gustafsson, Sebastian
    Chalmers, Sweden.
    Malmros, Anna
    Chalmers, Sweden.
    Forsberg, Urban
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering.
    Thorsell, Mattias
    Chalmers, Sweden.
    Janzén, Erik
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering.
    Rorsman, Niklas
    Chalmers, Sweden.
    Performance Enhancement of Microwave GaN HEMTs Without an AlN-Exclusion Layer Using an Optimized AlGaN/GaN Interface Growth Process2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 1, p. 333-338Article in journal (Refereed)
    Abstract [en]

    The impact of the sharpness of the AlGaN/GaN interface in high-electron mobility transistors (HEMTs) is investigated. Two structures, one with an optimized AlGaN/GaN interface and another with an unoptimized, were grown using hot-wall metal-organic chemical vapor deposition. The structure with optimized sharpness of the interface shows electron mobility of 1760 cm(2)/V . s as compared with 1660 cm(2)/V . s for the nonoptimized interface. Gated Hall measurements indicate that the sharper interface maintains higher mobility when the electrons are close to the interface compared with the nonoptimized structure, indicating less scattering due to alloy disorder and interface roughness. HEMTs were processed and evaluated. The higher mobility manifests as lower parasitic resistance yielding a better dc and high-frequency performance. A small-signal equivalent model is extracted. The results indicate a lower electron penetration into the buffer in the optimized sample. Pulsed-IV measurements imply that the sharper interface provides less dispersive effects at large drain biases. We speculate that the mobility enhancement seen AlGaN/AlN/GaN structures compared with the AlGaN/GaN case is not only related to the larger conduction band offset but also due to a more welldefined interface minimizing scattering due to alloy disorder and interface roughness.

  • 8.
    Bergsten, Johan
    et al.
    Chalmers Univ Technol, Sweden.
    Thorsell, Mattias
    Chalmers Univ Technol, Sweden.
    Adolph, David
    Chalmers Univ Technol, Sweden.
    Chen, Jr-Tai
    SweGaN AB, SE-58330 Linkoping, Sweden.
    Kordina, Olof
    SweGaN AB, SE-58330 Linkoping, Sweden.
    Sveinbjörnsson, Einar
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering. Univ Iceland, Iceland.
    Rorsman, Niklas
    Chalmers Univ Technol, Sweden.
    Electron Trapping in Extended Defects in Microwave AlGaN/GaN HEMTs With Carbon-Doped Buffers2018In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 6, p. 2446-2453Article in journal (Refereed)
    Abstract [en]

    This paper investigates AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated on epistructures with carbon (C)-doped buffers. Metalorganic chemical vapor deposition is used to grow two C-doped structures with different doping profiles, using growth parameters to change the C incorporation. The C concentration is low enough to result in n-type GaN. Reference devices are also fabricated on a structure using iron (Fe) as dopant, to exclude any process related variations and provide a relevant benchmark. All devices exhibit similar dc performance. However, pulsed I-V measurements show extensive dispersion in the C-doped devices, with values of dynamicRON 3-4 times larger than in the dc case. Due to the extensive trapping, the devices with C-dopedbuffers can only supply about half the outputpower of the Fe-doped sample, 2.5 W/mm compared to 4.8 W/mm at 10 GHz. In drain current transient measurements, the trap filling time is varied, finding large prevalence of trapping at dislocations for the C-doped samples. Clusters of C around the dislocations are suggested to be the main cause for the increased dispersion.

  • 9. Bleichner, H
    et al.
    Rosling, M
    Vobecky, J
    Bakowski, M
    Nordlander, E
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Measurements of failure phenomena ininductively loaded multi-cathode GTO thyristors1994In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 41, no 2, p. 251-257Article in journal (Refereed)
  • 10.
    Borg, Johan
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Evaluation of a surface-channel CCD manufactured in a pinned active-pixel-sensor CMOS process2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 8, p. 2660-2664Article in journal (Refereed)
    Abstract [en]

    This paper presents measurements on a surfacechannel CCD with gates implemented using single-layer polysilicongates. The device was manufactured in a 0.18 μm PINNEDphoto diode CMOS process commercially available from UMC.The CCD was built with a field-plate covering all gates as wellas the space between them, which allows the potential in the gapbetween non-overlapping gates to be manipulated.We present charge transfer efficiency measurements performedat clock frequencies of 1 MHz and 5 MHz, at multiplebackground packet sizes, and field-plate voltages. We furtherpropose and apply a method for separating CTI in four-phaseCCDs due to trapping from the inefficiency stemming from otherphenomena.The measurements show a single stage CTI ranging from 1.7×10−4 with a moderate background charge and substantial fieldplatevoltage, to 0.007 at zero field-plate voltage and the highestbackground charge tested. The CTI can be reduced significantly(more than a factor of 10 in some cases) by applying a significantnegative voltage at the field-plate. This, and the fact that only aminor part of the CTI can be attributed to trapping, indicatesthat the performance of the device is limited by the presence ofpotential hollows in the gaps between the gates.

  • 11. Bruce, Staffan
    et al.
    Vandamme, L. K. J.
    Rydberg, Anders
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Microwave and Terahertz Technology.
    Measurement of low-frequency base and collector current noise and coherence in SiGe heterojunction bipolar transistors using transimpedance amplifiers1999In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 46, no 5, p. 993-1000Article in journal (Refereed)
  • 12. Bruce, Staffan
    et al.
    Vandamme, L. K. J.
    Rydberg, Anders
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences.
    Temperature dependence and dielectric properties of dominant low-frequency noise sources in SiGe HBT2000In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 47, no 5, p. 1107-1112Article in journal (Refereed)
  • 13.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of Emitter Width and Emitter-Base Distance on the Current Gain in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 10, p. 2664-2670Article in journal (Refereed)
    Abstract [en]

    The influence of the emitter-base geometry on the current gain has been investigated by means of measurements and simulations. Particular attention has been placed on the emitter width and on the distance between the emitter edge and the base contact. When the emitter width is decreased from 40 to 8 mu m, the current gain is reduced by 20%, whereas when the distance between the base contact and the emitter edge is decreased from 5 to 2 mu m, the current gain is reduced by 10%. Simulations have been used to investigate the reasons for the current gain reduction. The reduction of the emitter width induces two mechanisms of current gain reduction: earlier forward biasing of the base-collector junction and higher recombination in the emitter region. Both mechanisms result from the higher current density flowing under the emitter region. Placing the base contact very close to the emitter edge increases the base current by increasing the gradient of the electron concentration toward the base contact. The effect of increasing the base doping in the extrinsic region has been simulated, and the results demonstrate that the current gain can be improved if a high doping concentration in the range of 5 x 10(18) cm(-3) is used.

  • 14.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 3, p. 704-711Article in journal (Refereed)
    Abstract [en]

    Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO2 have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained using one single energy level at 1 eV above the valence band, a capture cross section of 1 x 10(-15) cm(2), and a trap concentration of 2 x 10(12) cm(-2). Simulations have been performed at different temperatures to validate the model and characterize the temperature behavior of SiC BJTs. An analysis of the carrier concentration at different collector currents has been performed in order to describe the mechanisms of the current gain fall-off at a high collector current both at room temperature and high temperatures. At room temperature, high injection in the base ( which has a doping concentration of 3 x 10(17) cm(-3)) and forward biasing of the base-collector junction occur simultaneously, causing an abrupt drop of the current gain. At higher temperatures, high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the acting mechanism for the current gain fall-off. Forward biasing of the base-collector junction can also explain the reduction of the knee current with increasing temperature by means of the negative temperature dependence of the mobility.

  • 15.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of the ON-Resistance in 4H-SiC Power BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 2081-2087Article in journal (Refereed)
    Abstract [en]

    The ON-resistance of silicon carbide bipolar transistors is characterized and simulated. Output characteristics are compared at different base currents and different temperatures in order to validate the physical model parameters. A good agreement is obtained, and the key factors, which limit the improvement of R-ON, are identified. Surface recombination and material quality play an important role in improving device performances, but the device design is also crucial. Based on simulation results, a design that can enhance the conductivity modulation in the lowly doped drift region is proposed. By increasing the base doping in the extrinsic region, it is possible to meet the requirements of having low voltage drop, high current density, and satisfactory forced current gain. According to simulation results, if the doping is 5 x 10(18) cm(-3), it is possible to conduct 200 A/cm(2) at V-CE = 1 V by having a forced current gain of about 8, which represents a large improvement, compared with the simulated value of only one in the standard design.

  • 16.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I: Analytical Model of the MTJ STO2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1037-1044Article in journal (Refereed)
    Abstract [en]

    Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STO's characteristics, while enabling system-and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations.

  • 17.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part II: Verilog-A Model Implementation2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1045-1051Article in journal (Refereed)
    Abstract [en]

    The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various applications. In Part I of this paper, an analytical model based on the macrospin approximation has been introduced and verified by comparing it with the measurements of three different MTJ STOs. In Part II, the full Verilog-A implementation of the proposed model is presented. To achieve a reliable model, an approach to reproducing the phase noise generated by the MTJ STO has been proposed and successfully employed. The implemented model yields a time domain signal, which retains the characteristics of operating frequency, linewidth, oscillation amplitude, and DC operating point, with respect to the magnetic field and applied DC current. The Verilog-A implementation is verified against the analytical model, providing equivalent device characteristics for the full range of biasing conditions. Furthermore, a system that includes an MTJ STO and CMOS RF circuits is simulated to validate the proposed model for system-and circuit-level designs. The simulation results demonstrate that the proposed model opens the possibility to explore STO technology in a wide range of applications.

  • 18.
    Chen, Xi
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Chen, Si
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Zhang, Shi-Li
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Solomon, Paul
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics. IBM Thomas J. Watson Research Center.
    Zhang, Zhen
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Low-Noise Schottky Junction Trigate Silicon Nanowire Field-effect Transistor for Charge Sensing2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 9, p. 3994-4000Article in journal (Refereed)
    Abstract [en]

    Silicon nanowire (SiNW) field-effect transistors (SiNWFETs) are of great potential as a high-sensitivity charge sensor. The signal-to-noise ratio (SNR) of an SiNWFET sensor is ultimately limited by the intrinsic device noise generated by carrier trapping/detrapping processes at the gate oxide/silicon interface. This carrier trapping/detrapping-induced noise can be significantly reduced by replacing the noisy oxide/silicon interface with a Schottky junction gate (SJG) on the top of the SiNW. In this paper, we present a tri-SJG SiNWFET (Tri-SJGFET) with the SJG formed on both the top surface and the two sidewalls of the SiNW so as to enhance the gate control over the SiNW channel. Both experiment and simulation confirm that the additional sidewall gates in a narrow Tri-SJGFET indeed can confine the conduction path within the bulk of the SiNW channel away from the interfaces and significantly improve the immunity to the traps at the bottom buried oxide/silicon interface. Therefore, the optimal low-frequency noise performance can be achieved without the need for any substrate bias. This new gating structure holds promises for further development of robust SiNWFET-based charge sensors with low noise and low operation voltage.

  • 19. Corman, Thierry
    et al.
    Noren, K.
    Enoksson, Peter
    Melin, Jessica
    Stemme, Göran
    KTH, Superseded Departments (pre-2005), Signals, Sensors and Systems.
    Burst technology with feedback-loop control for capacitive detection and electrostatic excitation of resonant silicon sensors2000In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 47, no 11, p. 2228-2235Article in journal (Refereed)
    Abstract [en]

    A method for excitation and detection of resonant silicon sensors based on discontinuous, burst excitation is presented. The solution eliminates the crosstalk between electrostatic excitation and capacitive detection by separating them in time. High excitation voltages can be combined with highly sensitive detection electronics. The method facilitates the use of large distances between the resonator and electrodes used for elicitation and detection. The method was successfully tested with feedback-loop control on silicon resonant density and pressure sensors where the electrodes were positioned outside a glass, Continuous measurements of gas pressures and liquid densities were realized, The simplified fabrication process utilized reduces the risk of leakage from the ambient pressure to the low-pressure cavities in which the resonators are encapsulated since electrical feedthroughs are not needed, Excitation voltages alternating between 0 and 150 V could be applied to the resonators with measured electronics sensitivities of 0.4 fF Signal-to-noise ratios (SNRs) as high as 100 (density sensor) and 360 (pressure sensor) were obtained. The electronic evaluation revealed that the burst duty cycle (i.e,, the excitation time relative to the free oscillation time) had a strong influence on the output detection voltage, As few as two excitation periods with a burst cycle frequency of 115 Hz and a burst duty cycle of 1% was sufficient to select and lock the resonance frequency (28 042 Hz) for the tested pressure sensor. The same electrodes could be used for both excitation and detection, A novel solution is also presented that eliminates the charging effect of dielectric surfaces which otherwise can be a problem for capacitive detection.

  • 20. Danielsson, E.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Nikolaev, A.
    Nikitina, I. P.
    Dmitriev, V.
    Fabrication and characterization of heterojunction diodes with HVPE-Grown GaN on 4H-SiC2001In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 48, no 3, p. 444-449Article in journal (Refereed)
    Abstract [en]

    GaN/SiC heterojunctions can improve the performance considerably for BJTs and FETs. In this work, heterojunction diodes have been manufactured and characterized. The fabricated diodes have a GaN n-type cathode region on top of a JH-SIC p-type epi layer. The GaN layer was grown with HVPE directly on off-axis SiC without a buffer layer. Mesa structures were formed and a Ti metallization was used as cathode contact to GaN, and the anode contact was deposited on the backside using sputtered Al. Both current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed on the diode structures. The ideality factor of the measured diodes was 1.1 and was constant with temperature. A built in potential of 2.06 V was extracted from I-V-measurements and agrees well with the built in potential from C-V-measurements. The conduction band offset was extracted to 1.1 eV and the heterojunction was of type II. The turn on voltage for the diodes is about 1 V lower than expected and a suggested mechanism for this effect is discussed.

  • 21.
    Del Castillo, Ragnar Ferrand-Drake
    et al.
    Chalmers Univ Technol, Sweden.
    Chen, Ding-Yuan
    SweGaN AB, S-58278 Linkoping, Sweden.
    Chen, Jr-Tai
    SweGaN AB, S-58278 Linkoping, Sweden.
    Thorsell, Mattias
    Chalmers Univ Technol, Sweden; SAAB AB, Sweden.
    Darakchieva, Vanya
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering. Lund Univ, Sweden.
    Rorsman, Niklas
    Chalmers Univ Technol, Sweden.
    Characterization of Trapping Effects Related to Carbon Doping Level in AlGaN Back-Barriers for AlGaN/GaN HEMTs2024In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646Article in journal (Refereed)
    Abstract [en]

    The impact of different carbon concentrations in the Al 0.06 Ga 0.94 N graded back-barrier and GaN buffer of high electron mobility transistors (HEMTs) is investigated. Four epi-wafers with different carbon concentrations, ranging from 1 x 10(17) to 5 x 10(17) cm( -3) , were grown by metal organic chemical vapor deposition (MOCVD). HEMTs with 100 and 200 nm gate lengths were fabricated and characterized with dc, Pulsed-IV, drain current transient spectroscopy (DCTS), and large-signal measurements at 30 GHz. It is shown that the back-barrier effectively prevents buffer-related electron trapping. The highest C-doping provides the best 2DEG confinement, while lower carbon doping levels are beneficial for a high output power and efficiency. A C-doping of 1 x 10(17)cm( -3) offers the highest output power at maximum power added efficiency (PAE) (1.8 W/mm), whereas 3 x 10(17) cm( -3) doping provides the highest PAE ( > 40%). The C-profiles acquired by using secondary ion mass spectroscopy (SIMS), in combination with DCTS, is used to explain the electron trapping effects. Traps associated with the C-doping in the back-barrier are identified and the bias ranges for the trap activation are discussed. The study shows the importance of considering the C-doping level in the back-barrier of microwave GaN HEMTs for power amplification and generation.

  • 22.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Thulium silicate interfacial layer for scalable high-k/metal gate stacks2013In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, no 10, p. 3271-3276Article in journal (Refereed)
    Abstract [en]

    Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.

  • 23.
    Domeij, Martin
    et al.
    KTH, Superseded Departments (pre-2005), Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments (pre-2005), Electronics.
    Hillkirk, Leonardo
    KTH, Superseded Departments (pre-2005), Electronics.
    Linnros, Jan
    KTH, Superseded Departments (pre-2005), Electronics.
    Östling, Mikael
    KTH, Superseded Departments (pre-2005), Electronics.
    Dynamic avalanche in 3.3-kV Si power diodes1999In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 46, no 4, p. 781-786Article in journal (Refereed)
    Abstract [en]

    Measurements of the safe reverse recovery limit were performed for 3.3-kV Si power diodes using a novel optical experimental technique. In this experiment, influence of the junction termination is effectively eliminated by optical generation of a laterally-localized carrier plasma. The turn-off failures observed in measurements at two temperatures showed no temperature dependence and could not be reproduced in ordinary one-dimensional (1-D) or two-dimensional (2-D) device simulations. To simulate the stability of the current density toward current filamentation, two 1-D diodes with an area ratio 1:19 and a 10% difference in initial carrier plasma level, were simulated in parallel. This resulted in a strongly inhomogeneous current distribution, and a rapid reverse voltage fall resembling the measured turn-off failures. Inhomogeneous current distribution in these simulations appears as the current decay ceases due to impact ionization, in qualitative agreement with a current instability condition proposed by Wachutka [1].

  • 24.
    Domeij, Martin
    et al.
    KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
    Lutz, J.
    Silber, D.
    On the destruction limit of Si power diodes during reverse recovery with dynamic avalanche2003In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 50, no 2, p. 486-493Article in journal (Refereed)
    Abstract [en]

    The reverse recovery destruction limit of 3.3 kV fast recovery diodes was investigated by measurements and device simulations. Based on a good agreement between the measured destruction limit and current filamentation in simulations, it is proposed that the destruction is triggered by the onset of impact ionization at the nn(+) junction. The proposed destruction mode has large similarities with previously described second breakdown at the static breakdown voltage. An approximate analytical model which was derived indicate that avalanche at the nn(+) junction should become unstable with a time constant on the order of nanoseconds, whereas dynamic avalanche at the pn junction should be stable. Simulations and measurements give at hand that the reverse recovery safe operating area depends on the n-base width. An approximate equation is proposed to determine the minimum n-base width required for a nondestructive reverse recovery with dynamic avalanche as function of the reverse peak voltage.

  • 25. Drugge, B
    et al.
    Nordlander, E
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Laser scanning technique for the detection of resistivity inhomogeneities in silicon using liquid rectifying contacts1980In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. ED-27, no 11Article in journal (Refereed)
  • 26. Duan, Ningyuan
    et al.
    Luo, Jun
    Wang, Guilei
    Liu, Jinbiao
    Simoen, Eddy
    Mao, Shujuan
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wang, Xiaolei
    Li, Junfeng
    Wang, Wenwu
    Zhao, Chao
    Ye, Tianchun
    Reduction of NiGe/n- and p-Ge Specific Contact Resistivity by Enhanced Dopant Segregation in the Presence of Carbon During Nickel Germanidation2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 11, p. 4546-4549Article in journal (Refereed)
    Abstract [en]

    This brief explores the specific contact resistivity (rho(c)) of NiGe/n- and p-Ge contacts with and without carbon pregermanidation implantation. It is found that in the presence of carbon, not only the thermal stability of NiGe films is improved, but also the rho(c) of the NiGe/n- and p-Ge contacts is reduced remarkably due to enhanced phosphorus (P) and boron (B) dopant segregation (DS) at the NiGe/Ge interface after nickel germanidation. At 500 degrees C germanidation temperature, the.c values are reduced from 1.1 x 10(-4) Omega-cm(2) and 2.9 x 10(-5) Omega-cm(2) for NiGe/n- and p-Ge contacts without carbon to 7.3 x 10(-5) Omega-cm(2) and 1.4 x 10(-5) Omega-cm(2) for their counterparts with carbon, respectively.

  • 27.
    Edholm, Bengt
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Olsson, Jörgen
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Söderbärg, Anders
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    A Self-Aligned Lateral Bipolar Transistor Concept Realized on SIMOX-material1993In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 40, no 12, p. 2359-2360Article in journal (Refereed)
  • 28.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High Voltage SiC BJTs and Darlington Transistors2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 11, p. 4366-4372Article in journal (Refereed)
    Abstract [en]

    A novel lithographic method called intertwined design is demonstrated for high-power SiC devices to improve the area usage and current drive with more uniform current distribution along the device. The higher current drive is achieved by employing the inactive area underneath the base metal contact pads; more uniform current distribution is obtained by the center-base design; whereas the hexagon and square cell geometries result in >15% higher current density at lower on-resistance compared with the conventional finger design. For the first time, we have experimentally presented the intertwined design to marry these advantages and realize a high-efficient SiC power device. Center-base high-voltage 4H–SiC BJTs and Darlington pairs with different square and hexagon cell geometries are fabricated and compared with conventional designs to prove the ability of the intertwined design. The method can widely be used for large-area high-voltage BJTs as well as for integrated devices.

  • 29.
    Fjer, M.
    et al.
    School of Electrical, Electronic and Computer Engineering, Newcastle University, NE1 7RU Newcastle upon Tyne, United Kingdom.
    Persson, Stefan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Escobedo-Cousin, E.
    School of Electrical, Electronic and Computer Engineering, Newcastle University, NE1 7RU Newcastle upon Tyne, United Kingdom.
    O'Neill, A. G.
    School of Electrical, Electronic and Computer Engineering, Newcastle University, NE1 7RU Newcastle upon Tyne, United Kingdom.
    Low frequency noise in strained Si heterojunction bipolar transistors2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 12, p. 4196-4203Article in journal (Refereed)
    Abstract [en]

    The low frequency noise performance of strained Si heterojunction bipolar transistors (sSi HBTs) is presented for the first time. Conventional SiGe HBTs and Si bipolar junction transistors (BJTs), processed with strained Si devices, were also measured as a reference. It is found that a lower noise level is obtained in sSi HBTs for a given collector current, which is important for circuit applications, compared with either SiGe HBTs or Si BJTs. However, sSi HBTs exhibit greater low frequency noise compared with other devices at fixed base current. This is due to the presence of defects that are caused by the integration of the strain-relaxed buffer in the fabrication of sSi HBTs. The relationship between low frequency noise and defects is supported by material characterization. © 2011 IEEE.

  • 30.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Esteve, Romain
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schöner, Adolf
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Han, Jisheng
    Dimitrijev, Sima
    Reshanov, Sergey A.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Surface-passivation effects on the performance of 4H-SiC BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, p. 259-265Article in journal (Refereed)
    Abstract [en]

    In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100 °C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.

  • 31.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Voltage (2.8 kV) Implantation-free 4H-SiC BJTs with Long-TermStability of the Current Gain2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 8, p. 2665-2669Article in journal (Refereed)
    Abstract [en]

    In this work, implantation-free 4H-SiC BJTs with high breakdown of 2800 V have been fabricated utilizing acontrolled two-step etched junction termination extension (JTE). The small area devices show a maximum dc current gainof 55 at Ic=0.33 A (JC=825 A/cm2) and VCESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4mΩ·cm2. The large area device have a maximum dc current gain of 52 at Ic = 9.36 A (JC=289 A/cm2) and VCESAT = 1.14 Vat Ic = 5 A that corresponds to an ON-resistance of 6.8 mΩ·cm2. Also these devices demonstrate a negative temperaturecoefficient of the current gain (β=26 at 200°C) and a positive temperature coefficient of the ON-resistance (RON = 10.2mΩ·cm2 at 200°C). The small area BJT shows no bipolar degradation and low current gain degradation after 150 Hrs stressof the base-emitter diode with current level of 0.2A (JE=500 A/cm2). Also, large area BJT shows a VCE fall time of 18 nsduring turn-on and a VCE rise time of 10 ns during turn-off for 400 V switching characteristics.

  • 32.
    Gribisch, Philipp
    et al.
    Lund Univ, Sweden.
    Delgado Carrascon, Rosalia
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering.
    Darakchieva, Vanya
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering. Lund Univ, Sweden.
    Lind, Erik
    Lund Univ, Sweden.
    Capacitance and Mobility Evaluation for Normally-Off Fully-Vertical GaN FinFETs2023In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 70, no 8, p. 4101-4107Article in journal (Refereed)
    Abstract [en]

    In this work, we present the fabrication and analysis of fully-vertical GaN FinFETs with a gate length of 550 nm. The devices with fin widths of around 100 nm reveal normally-OFF behavior and subthreshold swings (SSs) very close to the 60-mV/dec limit. Low hysteresis values indicate low defect densities at the oxide/GaN interface. The devices exhibit low specific ON-resistances at a maximum of around 90 V breakdown voltage, which is reasonable for the drift layer thickness of 1 mu m. The capacitances in the devices were modeled and identified with capacitance voltage measurements, which could also be used to approximate the effective and field effect mobility in the channel and reveal to around 164 and 54 cm(2)/(Vs) at higher gate voltages, which is a slight improvement to reported values for similar devices.

  • 33.
    Gribisch, Philipp
    et al.
    Department of Electrical and Information Technology and NanoLund, Lund University, Lund, Sweden.
    Delgado Carrascon, Rosalia
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering.
    Darakchieva, Vanya
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering. NanoLund and the Physics Department, Lund University, Lund, Sweden.
    Lind, Erik
    Department of Electrical and Information Technology and NanoLund, Lund University, Lund, Sweden.
    Tuning of Quasi-Vertical GaN FinFETs Fabricated on SiC Substrates2023In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 70, no 5, p. 2408-2414Article in journal (Refereed)
    Abstract [en]

    In this work, we present the fabrication and investigation of the properties of quasi-vertical gallium nitride (GaN) fin field effect transistors (FinFETs) on silicon carbide (SiC) substrates and the influence of a postgate metallization annealing (PMA). The devices reveal low subthreshold swings (SSs) down to around 70 mV/dec. For a 1- μm -thick drift layer, a low ON-resistance below 0.05 mΩ⋅ cm2 (normalized on the fin area) and a breakdown voltage of 60 V were obtained. Devices with included PMA show a decreased threshold voltage and ON-resistance and by several orders of magnitude reduced gate leakage current compared to non-annealed devices. The devices show ohmic contact behavior and slightly negative threshold voltages, which indicates normally- ON behavior. The effective and field-effect mobility of the fin channel was obtained with a modeled carrier concentration and reveal to around 70 and 13 cm2/(Vs) at high gate voltages, which is in a good comparison to so far reported similar devices.

  • 34.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Error Propagation in Contact Resistivity Extraction Using Cross-Bridge Kelvin Resistors2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 6, p. 1585-1591Article in journal (Refereed)
    Abstract [en]

    The cross-bridge Kelvin resistor is a commonly used method for measuring contact resistivity (rho(c)). For low rho(c), the measurement has to be corrected for systematic error using measurements of contact resistance, semiconductor sheet resistance, and device dimensions. However, it is not straightforward to estimate the propagation of random measurement error in the measured quantities on the extracted rho(c). In this paper, a method is presented to quantify the effect of random measurement error on the accuracy of rho(c) extraction. This is accomplished by generalized error propagation curves that show the error in rho(c) caused by random measurement errors. Analysis shows that when the intrinsic resistance of the contact is smaller than the semiconductor sheet resistance, it becomes important to consider random error propagation. Comparison of literature data, where rho(c) < 5.10(-8) Omega.cm(2) has been reported, shows that care should be taken since, even assuming precise electrical data, a 1% error in the measurement of device dimensions can lead to up to similar to 50% error in the estimation of rho(c).

  • 35.
    Gustafsson, Sebastian
    et al.
    Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, Chalmers University of Technology, Göteborg, Sweden.
    Chen, Jr-Tai
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    Bergsten, Johan
    Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, Chalmers University of Technology, Göteborg, Sweden.
    Forsberg, Urban
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    Thorsell, Mattias
    Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, Chalmers University of Technology, Göteborg, Sweden.
    Janzén, Erik
    Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, The Institute of Technology.
    Rorsman, Niklas
    Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, Chalmers University of Technology, Göteborg, Sweden.
    Dispersive Effects in Microwave AlGaN/AlN/GaN HEMTs With Carbon-Doped Buffer2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 7, p. 2162-2169Article in journal (Refereed)
    Abstract [en]

    Aluminium gallium nitride (AlGaN)/GaN high-electron mobility transistor performance is to a large extent affected by the buffer design, which, in this paper, is varied using different levels of carbon incorporation. Three epitaxial structures have been fabricated: 1) two with uniform carbon doping profile but different carbon concentration and 2) one with a stepped doping profile. The epitaxial structures have been grown on 4H-SiC using hot-wall metal-organic chemical vapor deposition with residual carbon doping. The leakage currents in OFF-state at 10 V drain voltage were in the same order of magnitude (10-4 A/mm) for the high-doped and stepped-doped buffer. The high-doped material had a current collapse (CC) of 78.8% compared with 16.1% for the stepped-doped material under dynamic I-V conditions. The low-doped material had low CC (5.2%) but poor buffer isolation. Trap characterization revealed that the high-doped material had two trap levels at 0.15 and 0.59 eV, and the low-doped material had one trap level at 0.59 eV.

  • 36.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 500 degrees C 8-b Digital-to-Analog Converter in Silicon Carbide Bipolar Technology2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 9, p. 3445-3450Article in journal (Refereed)
    Abstract [en]

    High-temperature integrated circuits provide important sensing and controlling functionality in extreme environments. Silicon carbide bipolar technology can operate beyond 500 degrees C and has shown stable operation in both digital and analog circuit applications. This paper demonstrates an 8-b digital-to-analog converter (DAC). The DAC is realized in a current steering R-2R configuration. High-gain Darlington current switches are used to ensure ideal switching at 500 degrees C. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) at 25 degrees C are 0.79 and 1.01 LSB, respectively, while at 500 degrees C, the DNL and INL are 4.7 and 2.5 LSB, respectively. In addition, the DAC achieves 53.6 and 40.6 dBc of spurious free dynamic range at 25 degrees C and 500 degrees C, respectively.

  • 37.
    Hjelmgren, H
    et al.
    Ericsson Microelect AB, S-16481 Stockholm, Sweden.
    Litwin, A
    Ericsson Microelect AB, S-16481 Stockholm, Sweden.
    Small-signal substrate resistance effect in RF CMOS identified through device simulations2001In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 48, no 2, p. 397-399Article in journal (Refereed)
    Abstract [en]

    An anomalous dip in the measured s(22) characteristic, as well as a decrease in the output resistance, of MOS devices for rf applications was found to be a pure ac effect caused by the small-signal substrate transconductance. The study of the ac characteristics of multifinger transistors in rf applications with high-resistivity substrate also puts a question mark on the possibility of achieving fully scalable models, considering the observed ac substrate effect.

  • 38. Huang, Daming
    et al.
    Liu, Wei
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Liu, Zhiying
    KTH, School of Information and Communication Technology (ICT), Material Physics.
    Liao, C. C.
    Zhang, Li-Fei
    Gan, Zhenghao
    Wong, Waisum
    Li, Ming-Fu
    A Modified Charge-Pumping Method for the Characterization of Interface-Trap Generation in MOSFETs2009In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 56, no 2, p. 267-274Article in journal (Refereed)
    Abstract [en]

    A novel recovery-free interface-trap measurement method is presented in detail. This method is the modification of the conventional charge pumping (CP) by extending the pulse low level to the stress-bias and minimizing the pulse high-level duty cycle to suppress the recovery effect. The method is applied to study the negative-bias temperature instability in p-MOSFETs. As compared with the conventional CP, a much larger interface-trap generation under stress is observed by the new method. A power law time dependence (similar to t(n)) of interface-trap generation is observed. The index n. is less than that derived from conventional CP and increases with temperature, demonstrating a dispersive process involved in the trap generation dynamics.

  • 39.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH.
    Schröder, Stephan
    KTH.
    Rodriguez, Saul
    KTH.
    Malm, B. Gunnar
    KTH.
    Östling, Mikael
    KTH.
    Rusu, Ana
    KTH.
    An Intermediate Frequency Amplifier for High-Temperature Applications2018In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed)
    Abstract [en]

    This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

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    fulltext
  • 40.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Malm, Bengt Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    An Intermediate Frequency Amplifier for High-Temperature Applications (vol 65, pg 1411, 2018)2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 8, p. 3694-3694Article in journal (Refereed)
    Abstract [en]

    This correspondence highlights an error in the above-titled paper. The corrected material is presented here.

  • 41.
    Iannazzo, Mario
    et al.
    Technical University of Catalonia.
    Lo Muzzo, Valerio
    STMicroelectronics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Pandey, Himadri
    University of Siegen.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max
    University of Siegen.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Optimization of a Compact I–V Model forGraphene FETs: Extending Parameter Scalability for Circuit Design Exploration2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, p. 3870-3875Article in journal (Refereed)
    Abstract [en]

    An optimization of the current-to-voltage transfer characteristic of a graphene FET (GFET) compact model, based on drift-diffusion carrier transport, is presented. The improved accuracy at Dirac point extends the model usability for GFETs when scaling parameters, such as voltage supply, gate length, oxide thickness, and mobility, for circuit design exploration. The model's accuracy is demonstrated through fitting to GFETs processed in-house. The model has been written in a standard behavioral language, and extensively run in an analog circuit simulator for designing basic circuits, such as inverters and cascode cells, demonstrating its robustness.

  • 42. Illarionov, Yury
    et al.
    Smith, Anderson
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mueller, Thomas
    Lemme, Max
    Grasser, Tibor
    Hot-Carrier Degradation and Bias-Temperature Instability in Single-Layer Graphene Field-Effect Transistors: Similarities and Differences2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, p. 3876-3881Article in journal (Refereed)
    Abstract [en]

    We present a detailed analysis of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs) and compare those findings with the bias-temperature instability (BTI). Our results show that the HCD in GFETs is recoverable, similar to its BTI counterpart. Moreover, both the degradation mechanisms strongly interact. Particular attention is paid to the dynamics of HCD recovery, which can be well fitted with the capture/emission time (CET) map model and the universal relaxation function for some stress conditions, quite similar to the BTI in both GFETs and Si technologies. The main result of this paper is an extension of our systematic method for benchmarking new graphene technologies for the case of HCD.

  • 43.
    Kargarrazi, Saleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Saggini, Stefano
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    500 degrees C Bipolar SiC Linear Voltage Regulator2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 6, p. 1953-1957Article in journal (Refereed)
    Abstract [en]

    In this paper, we demonstrate a fully integrated linear voltage regulator in silicon carbide NPN bipolar transistor technology, operational from 25 degrees C up to 500 degrees C. For 15-mA load current, this regulator provides a stable output voltage with <2% variation in the temperature range 25 degrees C-500 degrees C. For both line and load regulations, degradation of 50% from 25 degrees C to 300 degrees C and improvement of 50% from 300 degrees C to 500 degrees C are observed. The transient response measurements of the regulator show robust behavior in the temperature range 25 degrees C-500 degrees C.

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    500 C Bipolar SiC Linear Voltage Regulator
  • 44. Kassamakova, L
    et al.
    Kakanakov, R D
    Kassamakov, I V
    Nordell, N
    Savage, S
    Hjorvarsson, B
    Svedberg, E B
    Abom, L
    Madsen, L D
    Temperature stable Pd ohmic contacts to p-type 4H-SiC formed at low temperatures1999In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 46, no 3, p. 605-611Article in journal (Refereed)
  • 45.
    Kassamakova, L
    et al.
    Bulgarian Acad Sci, Inst Appl Phys, Plovdiv 4000, Bulgaria IMC, Ind Microelect Ctr, S-16421 Kista, Sweden Royal Inst Technol, S-10044 Stockholm, Sweden Linkoping Univ, S-58183 Linkoping, Sweden.
    Kakanakov, RD
    Bulgarian Acad Sci, Inst Appl Phys, Plovdiv 4000, Bulgaria IMC, Ind Microelect Ctr, S-16421 Kista, Sweden Royal Inst Technol, S-10044 Stockholm, Sweden Linkoping Univ, S-58183 Linkoping, Sweden.
    Kassamakov, IV
    Bulgarian Acad Sci, Inst Appl Phys, Plovdiv 4000, Bulgaria IMC, Ind Microelect Ctr, S-16421 Kista, Sweden Royal Inst Technol, S-10044 Stockholm, Sweden Linkoping Univ, S-58183 Linkoping, Sweden.
    Nordell, N
    Bulgarian Acad Sci, Inst Appl Phys, Plovdiv 4000, Bulgaria IMC, Ind Microelect Ctr, S-16421 Kista, Sweden Royal Inst Technol, S-10044 Stockholm, Sweden Linkoping Univ, S-58183 Linkoping, Sweden.
    Savage, S
    Bulgarian Acad Sci, Inst Appl Phys, Plovdiv 4000, Bulgaria IMC, Ind Microelect Ctr, S-16421 Kista, Sweden Royal Inst Technol, S-10044 Stockholm, Sweden Linkoping Univ, S-58183 Linkoping, Sweden.
    Hjorvarsson, B
    Bulgarian Acad Sci, Inst Appl Phys, Plovdiv 4000, Bulgaria IMC, Ind Microelect Ctr, S-16421 Kista, Sweden Royal Inst Technol, S-10044 Stockholm, Sweden Linkoping Univ, S-58183 Linkoping, Sweden.
    Svedberg, EB
    Abom, L
    Bulgarian Acad Sci, Inst Appl Phys, Plovdiv 4000, Bulgaria IMC, Ind Microelect Ctr, S-16421 Kista, Sweden Royal Inst Technol, S-10044 Stockholm, Sweden Linkoping Univ, S-58183 Linkoping, Sweden.
    Madsen, LD
    Bulgarian Acad Sci, Inst Appl Phys, Plovdiv 4000, Bulgaria IMC, Ind Microelect Ctr, S-16421 Kista, Sweden Royal Inst Technol, S-10044 Stockholm, Sweden Linkoping Univ, S-58183 Linkoping, Sweden.
    Temperature stable Pd ohmic contacts to p-type 4H-SiC formed at low temperatures1999In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 46, no 3, p. 605-611Article in journal (Refereed)
    Abstract [en]

    The formation of low resistivity Pd-based ohmic contacts to p-type 4H-SiC below 750 degrees C are reported herein, The electrical properties of the contacts were examined using I-V measurements and the transmission-line model (TLM) technique. Contact resistivity as a function of annealing was investigated over the temperature range of 600 degrees C-700 degrees C, The lowest contact resistivity (5.5 x 10(-5) Ohm cm(2)) was obtained after annealing at 700 degrees C for 5 min, Atomic force microscopy of the as-deposited Pd layer showed a root-mean square roughness of similar to 8 nm, while after annealing at 700 degrees C, agglomeration occurred, increasing the roughness to 111 nm, Auger electron spectroscopy depth profiles revealed that with annealing, interdiffusion had resulted in the formation of Pd-rich silicides. However, X-ray diffraction and Rutherford backscattering showed that the majority of the film was still (unreacted) Pd. The thermal stability and reliability of the Pd contacts were examined by aging and temperature dependence electrical tests, The contacts annealed at 700 OC were stable at prolonged heating at a constant temperature of 500 degrees C and they showed thermal stability in air at operating temperatures up to 450 degrees C, This stability was not found for contacts formed at lower temperatures of 600 degrees C or 650 degrees C.

  • 46.
    Kawahara, Jun
    et al.
    Department of Printed Electronics, Acreo Swedish ICT AB, Norrköping.
    Andersson Ersman, Peter
    Department of Printed Electronics, Acreo Swedish ICT AB, Norrköping.
    Katoh, Kazuya
    R&D Strategy Department, Lintec Corporation, Saitama, Japan.
    Berggren, Magnus
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Fast-switching printed organic electrochemical transistors including electronic vias through plastic and paper substrates2013In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, no 6, p. 2052-2056Article in journal (Refereed)
    Abstract [en]

    A novel vertical architecture for all-printed organic electrochemical transistors, based on poly(3, 4-ethylenedioxythiophene):poly(styrene sulfonate), realized on flexible substrates, is reported. The transistors are manufactured along both faces of plastic or paper substrates and via connections are realized using laser ablation or simple punch through using a pin. Successful modulation of the electric current that flows between the two sides of the substrate is achieved using electrolyte-gating and electrochemical modulation of the electronic charge transport of the bulk of the transistor channel. In addition to this, the transistors are exhibiting fast switching and high ON/OFF current ratios.

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    fulltext
  • 47.
    Kawahara, Jun
    et al.
    RISE, Swedish ICT, Acreo.
    Andersson Ersman, Peter
    RISE, Swedish ICT, Acreo.
    Katoh, Kazuya
    Lintec Corporation, Japan.
    Berggren, Magnus
    Linköping University, Sweden.
    Fast-Switching Printed Organic Electrochemical Transistors Including Electronic Vias Through Plastic Paper Substrates2013In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, no 6, p. 2052-2056, article id 6515640Article in journal (Refereed)
    Abstract [en]

    A novel vertical architecture for all-printed organic electrochemical transistors, based on poly(3, 4-ethylenedioxythiophene):poly(styrene sulfonate), realized on flexible substrates, is reported. The transistors are manufactured along both faces of plastic or paper substrates via connections are realized using laser ablation or simple punch through using a pin. Successful modulation of the electric current that flows between the two sides of the substrate is achieved using electrolyte-gating electrochemical modulation of the electronic charge transport of the bulk of the transistor channel. In addition to this, the transistors are exhibiting fast switching high ON/OFF current ratios.

  • 48.
    Konofaos, N.
    et al.
    Comp. Engineering/Informatics Dept., University of Patras, Patras 26500, Greece.
    Evangelou, E.K.
    Laboratorio MDM-INFM, Agrate Briana 20041, Italy.
    Wang, Z.
    Helmersson, Ulf
    Linköping University, The Institute of Technology. Linköping University, Department of Physics, Chemistry and Biology, Plasma and Coating Physics .
    Properties of Al-SrTiO3-ITO capacitors for microelectronic device applications2004In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 51, no 7, p. 1202-1205Article in journal (Refereed)
    Abstract [en]

    Growth of SrTiO3 (STO) thin films on indium tin oxide (ITO) substrates took place by RF magnetron sputtering under various deposition conditions. Subsequent AI metallization created metal-insulator-metal (MIM) capacitors. The properties of such capacitors were investigated by means of structural and electrical measurements, revealing the films transparency, the dielectric constant, the switching time characteristics, and the trapped charges density. Dielectric constant values as high as 120 were obtained for low frequencies of around 2 kHz, the switching time was found to be 3.2 µs and the trapped charges were found equal to 2.9 nCcm-2. The results showed that the films were suitable for use in electronic devices where high capacitance is required and for potential applications in optical devices. © 2004 IEEE.

  • 49.
    Kundozerova, Tatyana V.
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Grishin, Alexander M.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Stefanovich, G. B.
    Velichko, A. A.
    Anodic Nb2O5 Nonvolatile RRAM2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 4, p. 1144-1148Article in journal (Refereed)
    Abstract [en]

    We report nonvolatile resistive switching in anodic niobium pentoxide thin-film memory cells. Highly dielectric Nb2O5 films were prepared at room temperature by the anodic oxidation of submicrometer-thick Nb films sputtered onto an Si wafer. After the electroforming process, Au/Nb2O5/Nb/Si sandwich memory cells demonstrate reproducible direct current and pulse mode switching between two resistance states with a resistance ON-OFF ratio around 10(3). Low and high resististive states show ohmic conductivity and field-assisted Poole-Frenkel-type conductivity, respectively. Nonvolatile resistance storage was traced within 40 days to quantify retention characteristics of the Nb2O5 memristor. The low-temperature anodic oxidation of Nb was found to be feasible to fabricate high-density cross-point memory with 3-D stack structures.

  • 50.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Design and Characterization of High-Temperature ECL-Based Bipolar Integrated Circuits in 4H-SiC2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 4, p. 1076-1083Article in journal (Refereed)
    Abstract [en]

    Operation up to 300 degrees C of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter-coupled logic is demonstrated. Stable noise margins of about 1 V are reported for a two-input OR-NOR gate operated on - 15 V supply voltage from 27 degrees C up to 300 degrees C. In the same temperature range, an oscillation frequency of about 2 MHz is also reported for a three-stage ring oscillator.

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    LanniTED2012
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