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  • 1. Adiseno,
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 9, p. 1162-1168Article in journal (Refereed)
    Abstract [en]

    A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in RF Si-bipolar process with an f(T) of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP3 (+15.5-dBm OIP3) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA dc current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with - 10 to -41-dB S-11 is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 x 0.9 mm(2). The circuit is suitable for area-efficient multiband multistandard low-IF receivers.

  • 2.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Arimoto, Kazutami
    Renesas Corp, Itami, Hyogo 6640005 Japan .
    Cantatore, Eugenio
    Eindhoven University Technology, NL-5600 MB Eindhoven, Netherlands .
    Zhang, Kevin
    Intel Corp, Hillsboro, OR 97124 USA .
    Introduction to the Special Issue on the 2009 IEEE International Solid-State Circuits Conference2010In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 45, no 1, p. 3-6Article in journal (Other academic)
    Abstract [en]

    n/a

  • 3.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Krishnamurthy, R.K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Borkar, S.Y.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    A sub-130-nm conditional keeper technique2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 5, p. 633-638Article in journal (Refereed)
    Abstract [en]

    Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction

  • 4.
    Alvandpour, Atila
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Reynaert, Patrick
    Katholieke University of Leuven, Belgium .
    Ytterdal, Trond
    Norwegian University of Science and Technology, Norway .
    Editorial Material: Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC)2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 7, p. 1511-1514Article in journal (Other academic)
    Abstract [en]

    n/a

  • 5. Alzaher, H. A.
    et al.
    Elwan, H. O.
    Ismail, Mohammed
    A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 1, p. 27-37Article in journal (Refereed)
    Abstract [en]

    A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm(2) in a 0.5-mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54),89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA.

  • 6.
    Andreani, P.
    et al.
    IEEE, Denmark.
    Fard, Ali P.
    More on the 1/f 2 phase noise performance of CMOS differential-pair LC-tank oscillators2006In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 41, no 12, p. 2703-2711Article in journal (Refereed)
    Abstract [en]

    This paper presents a rigorous phase noise analysis in the 1/f 2 region for the differential CMOS LC-tank oscillator with both nMOS and pMOS switch pairs. A compact, closed-form phase noise equation is obtained, accounting for the noise contributions from both tank losses and transistors currents, which allows a robust comparison between LC oscillators built with either one or two switch pairs. The fabricated oscillator prototype is tunable between 2.15 and 2.35 GHz, and shows a phase noise of - 144 dBc/Hz at 3 MHz offset from the 2.3 GHz carrier for a 4 mA bias current. The phase noise figure-of-merit is practically constant across the tuning range, with a minimum of 191.5 dBc/Hz. A reference single-switch-pair oscillator has been implemented and tested as well, and the difference between the phase noise levels displayed by the two oscillators is very nearly the one expected from theory.

  • 7.
    Andreani, Pietro
    et al.
    Technical University of Denmark.
    Wang, Xiaoyan
    Technical University of Denmark.
    Vandi, Luca
    Technical University of Denmark.
    Fard, Ali
    Mälardalen University, Department of Computer Science and Electronics.
    A Study of Phase Noise in Colpitts and LC-tank CMOS Oscillators2005In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 40, no 5, p. 1107-1118Article in journal (Refereed)
    Abstract [en]

    This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f2 phase-noiseregion are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise flgure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypesof both Colpitts and LC-tank oscillators have been implemented in a 0.35-μm CMOS process. The best performance of the LC-tank oscillatorsshows a phase noise of - 142 dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of ∼189 dBc/Hz. For the same oscillation frequency, the FoM displayed by the differential Colpitts oscillators is ∼5 dB lower.

  • 8. Badaroglu, M.
    et al.
    Donnay, S.
    De Man, H. J.
    Zinzius, Y. A.
    Gielen, G. G. E.
    Sansen, W.
    Fonden, T.
    Signell, Svante
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no 7, p. 1250-1260Article in journal (Refereed)
    Abstract [en]

    Substrate noise is a major obstacle for mixed-signal integration. While the power consumption scales linearly with the clock frequency, substrate noise does not have thin scaling due to the resonances in the transfer function of the supply current to the substrate. This paper addresses a practical technique to estimate the substrate noise frequency spectrum of a large mixed-mode System-on-Chip (SoC) with multiple supplies and embedded memories. The results have been verified with substrate noise measurements on a 60-MHz 220-Kgates telecom SoC implemented in a 0.3 mum CMOS process on an EPI-type substrate. We compute a linear chip-level substrate model together with the single-cycle representation of piecewise-linear noise sources of three. supply regions used in this ASIC. Based on this model we accurately estimate the four major resonances in the substrate poise spectrum and their relative magnitudes with 2 dB relative error at the major resonance with respect to measurements. We also present substrate noise measurements at different operating modes of the WLAN receiver. These measurements show that output I/O buffers generate significant substrate noise where an increase of 44% is measured for substrate noise peak-to-peak value due to the additional simultaneous switching of six output I/O buffers with already fully switching datapath and two output I/Os.

  • 9. Bao, Dongxuan
    et al.
    Zou, Zhuo
    Nejad, Majid Baghaei
    Qin, Yajie
    Zheng, Li-rong
    KTH.
    A Wirelessly Powered UWB RFID Sensor Tag With Time-Domain Analog-to-Information Interface2018In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 53, no 8, p. 2227-2239Article in journal (Refereed)
    Abstract [en]

    This paper presents a wirelessly powered radio frequency identification sensor tag with an analog-to-information interface. A time-domain interface, incorporating an ultra-lowpower impulse radio ultra-wideband (IR-UWB) transmitter (TX), is employed. The analog signal from the sensor is compared with a triangular waveform, resulting in a pulse-position modulation signal to trigger UWB pulses. Thanks to the high time-resolution IR-UWB radio, time intervals of the impulses can be used to represent the original input value, which is measured remotely on the reader side by a time-of-arrival estimator. This approach not only eliminates the analog-to-digital converter (ADC) but also significantly reduces the number of bits to be transmitted for power saving. The proposed tag is fabricated in a 0.18-mu m CMOS process with an active area of 2.5 mm(2). The measurement results demonstrate that a 300-kS/s sampling rate with a 6.7-bit effective number of bits (ENOB) is obtained via a UWB receiver with a sensitivity of -93 dBm and an integration window of 10 ns. The ENOB is improved to 7.3 bits when the integration window is reduced to 2 ns. The tag can be powered up by a -18-dBm UHF input signal. The power consumption of the proposed tag is 41.5 mu W yielding a 1.3-pJ/conv.step figure of merit, offering 9x and 67x improvements compared with the state of the art based on an ADC and a backscattering TX, and the tag based on an ADC and a narrowband TX, respectively.

  • 10.
    Bhide, Ameya
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS2015In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, p. 2306-2310Article in journal (Refereed)
    Abstract [en]

    This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

  • 11.
    Borg, Johan
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    An ultrasonic transducer interface IC with integrated push-pull 40 Vpp, 400 mA current output, 8-bit DAC and integrated HV multiplexer2011In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 46, no 2, p. 475-484Article in journal (Refereed)
  • 12.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Rong, Liang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yang, Geng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    The Design of All-Digital Polar Transmitter based on ADPLL and Phase Synchronized Delta Sigma Modulator2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 5, p. 1154-1164Article in journal (Refereed)
    Abstract [en]

    An improved architecture of polar transmitter (TX) is presented. The proposed architectureis digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phasemodulation, a 1-bit low-pass delta sigma (Delta Sigma) modulator for envelop modulation, and aH-bridge class-D power amplifier (PA) for differential signaling. The (Delta Sigma) modulator isclocked using the phase modulated RF carrier to ensure phase synchronization between theamplitude and phase path, and to guarantee the PA is switching at zero crossings of theoutput current.An on chip pre-filter is used to reduce the parasitic capacitance from packages at theswitch stage output. The high over sampling ratio of the (Delta Sigma) modulator move quantizationnoise far away from the carrier frequency, ensuring good in-band performance and relax filterrequirements. The on-chip filter also acts as impedance matching and differential to singleended conversion. The measured digital transmitter consumes 58 mW from a 1 V at 6.8 dBm output power.

  • 13. Dielacher, Franz
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Special issue on the 2002 European Solid State Circuits Conference (Esscirc): Guest editorial2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no 7, p. 1095-1097Article in journal (Refereed)
  • 14.
    Edman, Anders
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Computer Engineering.
    Christensen, J
    Emrich, A.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6um CMOS.2001In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 36, p. 258-265Article in journal (Refereed)
    Abstract [en]

    The autocorrelation spectrometer is an important instrument for radio astronomy. In satellite-based spectrometers, low power consumption is essential. The correlator chip presented in this paper reduces the power consumption more than five times compared to other full-custom designs. This has been achieved by reducing the number of clocked transistors, using a compact layout of cells, which reduces wire lengths, and using parallel processing of data. Also, the low power performance is combined with a large number of lags and a high data throughput. The correlator performs 0.5-TMAC operations in 416 lags at a sample rate of 1.28-GSample/s with an input data precision of 1.5-b and a correlation period of one second. The chip is also designed to reduce noise generation by using multiple internal clock phases.

  • 15.
    Fard, Ali P.
    et al.
    Mälardalen University. IEEE, Denmark.
    Andreani, P.
    Catena, 164 46 Kista, Sweden.
    An analysis of 1/f2 phase noise in bipolar Colpitts oscillators (with a digression on bipolar differential-pair LC oscillators)2007In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 42, no 2, p. 374-384Article in journal (Refereed)
    Abstract [en]

    This work presents an analysis of phase noise in the 1/f2 region displayed by both single-ended and differential bipolar Colpitts oscillators. Very accurate and rigorous symbolic phase noise expressions are derived, enabling a deeper insight into the major mechanisms of phase noise generation, and providing new tools for design optimization. Phase noise expressions for the cross-coupled differential-pair LC-tank oscillator are derived as well. The theoretical analysis is validated on a 3 GHz differential bipolar Colpitts VCO implemented in a 0.35 μm SiGe process. Measurements show a phase noise of -123 dBc/Hz or less at 1 MHz offset frequency from the 2.8-3.1 GHz carrier, for a phase noise figure-of-merit of at least 183 dBc/Hz across the tuning range. A very good agreement between theory, numerical simulations, and measurements is observed.

  • 16. Fouts, D. J.
    et al.
    Pace, P. E.
    Karow, C.
    Ekestorm, Stig R. T.
    Swedish National Defence College, Department of Military Studies, Military-Technology Division.
    A single-chip false target radar image generator for countering wideband imaging radars2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 6, p. 751-759Article in journal (Refereed)
    Abstract [en]

    This paper describes the theory, design, implementation, simulation, and testing of an ASIC capable of generating false target radar images for countering wideband synthetic aperture and inverse synthetic aperture imaging radars. The 5.5 x 6.1 mm IC has 81632 transistors, 132 I/O pins, and consumes 0.132 W at 70 MHz from a 3.3-V supply. An introduction to the application and operation of the ASIC in an electronic attack system is also presented. The false target image is fully programmable and the chip is capable of generating images of both small and large targets, even up to the size of an aircraft carrier. This is the first reported use of all-digital technology to generate false target radar images of large targets.

  • 17.
    Hazucha, P.
    et al.
    Electronic Devices Department, Linkoping University, S-581 83 Linkoping, Sweden.
    Svensson, C.
    Electronic Devices Department, Linkoping University, S-581 83 Linkoping, Sweden.
    Optimized test circuits for SER characterization of a manufacturing process2000In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 35, no 2, p. 142-148Article in journal (Refereed)
    Abstract [en]

    Novel test circuits for the accurate determination of soft error rate (SER) dependency on critical charges QCRIT have been developed. The minimum charge necessary for flipping the state of a sensor cell, denoted by QCRIT, is measured with 1%-2% accuracy before exposing the circuits to radiation. During the accelerated testing, circuits biased with multiple different supply voltages VCC are simultaneously placed into a beam and any bit flips are logged. From the measured SER dependency on VCC and previously measured QCRIT dependency on VCC, the dependency of SER on QCRIT can be deduced by correlating VCC's for the two measurements. Furthermore, the sensor cell utilizes a single dynamic node which can be programmed to detect strikes on either N- or P-type diffusions, but not both at the same time. The measured dependency SER(QCRIT), normalized by the diffusion area, can be used for predicting SER of any other circuit fabricated in the same process and aid designers in optimization for reduced SER. Predictions of a theoretical SER model, if one is available, can be compared directly with the measurements. Since the true QCRIT of the test circuits is known accurately, any discrepancy larger than given by the measurement uncertainty of SER(QCRIT) would be clearly due to limitations of the SER model. We implemented the test circuits in a 0.6-µm bulk CMOS process and verified accuracy of QCRIT (VCC) calibration method.

  • 18. Hazucha, P.
    et al.
    Svensson, C.
    Wender, S.A.
    Los Alamos National Laboratory, Los Alamos, NM 87545, United States.
    Cosmic-ray soft error rate characterization of a standard 0.6-µm CMOS process2000In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 35, no 10, p. 1422-1429Article in journal (Refereed)
    Abstract [en]

    Cosmic-ray soft errors from ground level to aircraft flight altitudes are caused mainly by neutrons. We derived an empirical model for estimation of soft error rate (SER). Test circuits were fabricated in a standard 0.6-µm CMOS process. The neutron SER dependence on the critical charge and supply voltage was measured. Time constants of the noise current were extracted from the measurements and compared with device simulations in three dimensions. The empirical model was calibrated and verified by independent SER measurements. The model is capable of predicting cosmic-ray neutron SER of any circuit manufactured in the same process as the test circuits. We predicted SER of a static memory cell.

  • 19.
    Hsu, Steven
    et al.
    Intel Corp., Hillsboro, USA.
    Alvandpour, Atila
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Mathew, Sanu
    Intel Corp., Hillsboro, USA.
    Lu, Shih-Lien
    Intel Corp., Hillsboro, USA.
    Krishnamurthy, Ram K.
    Intel Corp., Hillsboro, USA.
    Borkar, Shekar
    Intel Corp., Hillsboro, USA.
    A 4.5 GHz 130nm 32-kb LO cache with a leakage-tolerant self reverse-bias bitline scheme.2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no No. 5, p. 755-761Article in journal (Refereed)
  • 20.
    Hyyppä, Kalevi
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Ericson, Klas
    Luleå tekniska universitet.
    Low-noise photodiode-amplifier circuit1994In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 29, no 3, p. 362-365Article in journal (Refereed)
    Abstract [en]

    A photodiode-amplifier circuit with the photodiode in the feedback path is presented. It is named the PIF-circuit. No resistor is needed at the amplifier input to provide a path to ground for the signal and leakage currents from the photodiode and the amplifier input bias current. Therefore, one potentially dominating noise source is eliminated. At frequencies below 10 kHz, the implemented PIF-circuit has an NEP≈3 fW/√Hz

  • 21.
    Jakonis, Darius
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Folkesson, Kalle
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Eriksson, P.
    Wavebreaker AB, Norrköping, Sweden.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS2005In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 40, no 6, p. 1265-1277Article in journal (Refereed)
    Abstract [en]

    This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-μm CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP3 of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm2.

  • 22.
    Ji-Ren, Yuan
    et al.
    Linköping University, Department of Physics, Chemistry and Biology. Linköping University, The Institute of Technology.
    Karlsson (Söderquist), Ingemar
    Linköping University, Department of Physics, Chemistry and Biology. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Physics, Chemistry and Biology. Linköping University, The Institute of Technology.
    A true single-phase-clock dynamic CMOS circuit technique1987In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 5, no 22, p. 899-901Article in journal (Refereed)
    Abstract [en]

    The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted. This class of circuits has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed. Several examples are demonstrated.

  • 23.
    Jonsson, Fredrik
    et al.
    Spirea AB.
    et al.,
    A single-chip CMOS transceiver for 802.11a/b/g wireless LANs2004In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 39, no 12, p. 2250-2258Article in journal (Refereed)
    Abstract [en]

    A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-mum CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3degrees in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes +/-2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm(2). The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.

  • 24.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Dual-Output Thermoelectric Energy Harvesting Interface with 86.6% Peak Efficiency at 30 μW and Total Control Power of 160 nW2016In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173XArticle in journal (Refereed)
    Abstract [en]

    A thermoelectric energy harvesting interface based on a single-inductor dual-output (SIDO) boost converter is presented. A system-level design methodology combined with ultra-low power circuit techniques reduce the power consumption and minimize the losses within the converter. Additionally, accurate zero-current switching (ZCS) and zero-voltage switching (ZVS) techniques are employed in the control circuit to ensure high conversion efficiency at μW input power levels. The proposed SIDO boost converter is implemented in a 0.18 μm CMOS process and can operate from input voltages as low as 15 mV. The measurement results show that the converter achieves a peak conversion efficiency of 86.6% at 30 μW input power.

  • 25.
    Krishnamurthy, R.K.
    et al.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Balamurugan, G.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Shanbhag, R.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Soumyanath, K.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    Borkar, S.Y.
    Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
    A 130-nm 6-GHz 256x32 bit leakage-tolerant register file2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 5, p. 624-632Article in journal (Refereed)
    Abstract [en]

    Describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-Vt usage, and 50% keeper downsizing. Gate-source underdrive of -V cc on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-Vt bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703× bitline active leakage reduction, enabling continued Vt scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented

  • 26. Li, S. G.
    et al.
    Kipnis, I.
    Ismail, Mohammed
    10-GHz CMOS quadrature LC-VCO for multirate optical applications2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no 10, p. 1626-1634Article in journal (Refereed)
    Abstract [en]

    A 10-GHz quadrature LC-VCO (QVCO) fabricated in a 0.13-mum CMOS process for 10-Gb/s multirate optical applications is described. Bimodal oscillation behavior (or phase ambiguity) inherent to quadrature LC-VCOs is analyzed theoretically and a cascode-based coupling method is proposed which effectively eliminates bimodal oscillation. Digitally controlled capacitor arrays are used in this design to extend the tuning range of the QVCO to cover multirate operations. The QVCO achieves a jitter generation of only 32 mUI(pp) at 10 GHz and a phase poise of -95 dBc/Hz at 1-MHz frequency offset with only 8 mA of current consumption in the QVCO core.

  • 27.
    Lindgren, Leif
    et al.
    IVP Integrated Vision Products AB.
    Melander, Johan
    SICK IVP.
    Johansson, Robert
    IVP Integrated Vision Products AB.
    Möller, Björn
    IVP Integrated Vision Products AB.
    A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging2005In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 40, no 6, p. 1350-1359Article in journal (Refereed)
    Abstract [en]

    This paper presents a multiresolution general-purpose high-speed machine vision sensor with on-chip image processing capabilities. The sensor comprises an innovative multiresolution sensing area, 1536 A/D converters, and a SIMD array of 1536 bit-serial processors with corresponding memory. The sensing area consists of an area part with 1536 × 512 pixels, and a line-scan part with a set of rows with 3072 pixels each. The SIMD processor array can deliver more than 100 GOPS sustained and the on-chip pixel-analysing rate can be as high as 4Gpixels/s. The sensor is ideal for high-speed multisense imaging where, e.g., color, greyscale, internal material light scatter, and 3-D profiles are captured simultaneously. When running only 3-D laser triangulation, a data rate of more than 20 000 profiles/s can be achieved when delivering 1536 range values per profile with 8 bits of range resolution. Experimental results showing very good image characteristics and a good digital to analog noise isolation are presented.

  • 28.
    Mesgarzadeh, Behzad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Hansson, Martin
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Jitter Characteristic in Charge Recovery Resonant Clock Distribution2007In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 42, no 7, p. 1618-1625 Article in journal (Refereed)
    Abstract [en]

    This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

  • 29.
    Mu, F.
    et al.
    SwitchCore, S-223 63 Lund, Sweden.
    Svensson, C.
    Pulsewidth control loop in high-speed CMOS clock buffers2000In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 35, no 2, p. 134-141Article in journal (Refereed)
    Abstract [en]

    In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital. Signal quality degradation is influenced by temperature and process deviation. In this paper, we propose a pulsewidth control loop to get required pulsewidth. To investigate the loop stability, a linearized small signal analysis model is used. Results of SPICE simulation show that the pulsewidth can be well controlled if the loop parameters are properly chosen. The pulsewidth can be easily adjusted to a desired value by sizing the ratio of transistor sizes in the current mirror of charge pump.

  • 30. Radiom, Soheil
    et al.
    Baghaei Nejad, Majid
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Mohammadpour-Aghdam, Karim
    Vandenbosch, Guy A. E.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Gielen, Georges G. E.
    Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-mu m Standard CMOS2010In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 45, no 9, p. 1746-1758Article in journal (Refereed)
    Abstract [en]

    This paper discusses two antennas monolithically integrated on-chip to be used respectively for wireless powering and UWB transmission of a tag designed and fabricated in 0.18-mu m CMOS technology. A multiturn loop-dipole structure with inductive and resistive stubs is chosen for both antennas. Using these on-chip antennas, the chip employs asymmetric communication links: at downlink, the tag captures the required supply wirelessly from the received RF signal transmitted by a reader and, for the uplink, ultra-wideband impulse-radio (UWB-IR), in the 3.1-10.6-GHz band, is employed instead of backscattering to achieve extremely low power and a high data rate up to 1 Mb/s. At downlink with the on-chip power-scavenging antenna and power-management unit circuitry properly designed, 7.5-cm powering distance has been achieved, which is a huge improvement in terms of operation distance compared with other reported tags with on-chip antenna. Also, 7-cm operating distance is achieved with the implemented on-chip UWB antenna. The tag can be powered up at all the three ISM bands of 915 MHz and 2.45 GHz, with off-chip antennas, and 5.8 GHz with the integrated on-chip antenna. The tag receives its clock and the commands wirelessly through the modulated RF powering-up signal. Measurement results show that the tag can operate up to 1 Mb/s data rate with a minimum input power of -19.41 dBm at 915-MHz band, corresponding to 15.7 m of operation range with an off-chip 0-dB gain antenna. This is a great improvement compared with conventional passive RFIDs in term of data rate and operation distance. The power consumption of the chip is measured to be just 16.6 mu W at the clock frequency of 10 MHz at 1.2-V supply. In addition, in this paper, for the first time, the radiation pattern of an on-chip antenna at such a frequency is measured. The measurement shows that the antenna has an almost omnidirectional radiation pattern so that the chip's performance is less direction-dependent.

  • 31.
    Sundström, Timmy
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.4 GS/s, Single-channel, 31.3 dB SNDR at Nyquist, 8-bit Pipeline ADC in 65nm CMOS2011In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 46, no 7, p. 1575-1584Article in journal (Refereed)
    Abstract [en]

    This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample-rate is achieved through the use of fast openloop current-mode amplifiers and the early comparison scheme. The bounds on the sub-ADC sampling instance are analyzed based on sufficient settling for a decision as well as metastability. Implemented in a 65nm general purpose CMOS technology the SNDR is above 30.1 dB in the Nyquist band, being 34.1 and 31.3 dB at low frequency and Nyquist, respectively. This shows that multi-GS/s pipeline ADCs are feasible as key building blocks in interleaved structures.

  • 32.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Optimum voltage swing on on-chip and off-chip interconnect2001In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 36, no 7, p. 1108-1112Article in journal (Refereed)
    Abstract [en]

    Reduced voltage swings are often used for saving power on interconnects. In this paper, we demonstrate the existence of an optimum voltage swing for minimum power consumption, for on-chip and off-chip interconnect. Actual values of optimum swings and corresponding power savings for high performance interconnects are estimated.

  • 33.
    Söderquist, Ingemar
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Globally updated mesochronous design style2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no 7, p. 1242-1249Article in journal (Refereed)
    Abstract [en]

    In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure due to metastability. Synchronous design styles are widely used, easy to grasp and to implement, and also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most Important is the relationship between physical size and maximum, clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous (GUM) design style is to overcome those drawbacks by identifying all global signal links in the system and adding synchronization circuits to these. System level simplicity, inherited from synchronous design and its tool support, is retained. In this paper, the GUM design style is described, analyzed, and demonstrated. Experimental results from a large-scale high-speed system using three 0.8-µm BiCMOS chips are given. The GUM design style is scaleable and suitable for future system-on-chip applications both on and among chips.

  • 34.
    Tadjpour, Shahrzad
    et al.
    University of California, Los Angeles.
    Cijvat, Ellie
    University of California, Los Angeles.
    Hegazi, Emad
    University of California, Los Angeles.
    Abidi, A.A
    University of California, Los Angeles.
    A 900-MHz Dual-Conversion Low-IF GSM Receiver in 0.35 μm CMOS2001In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 36, no 12, p. 1992-2002Article in journal (Refereed)
    Abstract [en]

    A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meet GSM phase-noise specifications.

  • 35.
    Zhang, Dai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 7, p. 1585-1593Article in journal (Refereed)
    Abstract [en]

    This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch boot-strapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-mu m CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.

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