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  • 1. Adiseno,
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Multiband high-linearity front-end receivers for wireless applications2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 30, no 1, p. 59-67Article in journal (Refereed)
    Abstract [en]

    In this paper, a modified front-end receiver configuration, which consists of an LNA and mixer suitable for zero-IF or low-IF receivers, is presented. The idea is to achieve a better linearity for receivers by combining circuit and system level solutions. Three circuit topologies, two in bipolar and one in CMOS technology, are presented in this paper with their simulation results. One of the bipolar topologies has been implemented and measurement results are presented. An IIP3 of up to +0.6 dBm of a combined bipolar LNA and mixer is achieved, depending on frequency of interest and with an acceptable noise figure performance at a current consumption of less than 13 mA from 5 V supply voltage in one circuit and 3 V supply voltage in the other one. An IIP3 up to +5 dBm is achieved for the CMOS topology at a lower overall gain and acceptable noise figure (14.4 mA and 3 V). All circuits presented in this paper are wideband circuits, suitable for area-efficient multiband receivers.

  • 2.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Modeling of peak-to-peak core switching noise, output impedance, and decoupling capacitance along a vertical chain of power distribution TSV pairs2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 73, no 1, p. 311-328Article in journal (Refereed)
    Abstract [en]

    In this article we propose an efficient and accurate model to estimate peak-to-peak core switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of dies interconnected through TSVs. The proposed model is accurate with only a 2–3% difference in peak-to-peak core switching noise as compared to the Ansoft Nexxim4.1 equivalent model. The proposed model is 3–4 times faster than Ansoft Nexxim4.1 and uses two times less memory as compared to the Ansoft Nexxim4.1 equivalent model. In this article we also thoroughly establish design guidelines for almost flat output impedance magnitude at each stage of a vertical chain of power distribution TSV pairs to realize a resonance free scenario over a wide operating frequency range. We also establish decoupling capacitance design guidelines based on the optimum output impedance and critically damped supply voltage for the core logic for each stage of a vertical chain of power distribution TSV pairs.

  • 3.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979Article in journal (Other academic)
    Abstract [en]

    This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.

  • 4.
    Ahsan, Naveed
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ramzan, Rashad
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dąbrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Ouacha, Aziz
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Samuelsson, Carl
    Swedish Defence Research Agency (FOI), P.O. Box 1165, SE-581 11 Linköping, Sweden.
    A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, p. 79-90Article in journal (Refereed)
    Abstract [en]

    This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.

  • 5.
    Andersson, Niklas
    et al.
    Ericsson Microelectronics AB.
    Andersson, Ola
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Models and Implementation of a Dynamic Element Matching DAC2003In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, no 1, p. 7-16Article in journal (Refereed)
    Abstract [en]

    The dynamic element matching (DEM) techniques for digital-to-analog converters (DACs) has been suggested as a promising method to improve matching between the DAC''s reference levels. However, no work has so far taken the dynamic effects that limit the performance for higher frequenciesinto account. In this paper we present a model describing the dynamic properties of a DEM DAC and compare the simulated results with measurements of a 14-bit current-steering DEM DAC implemented in a 0.35-μm CMOS process. The measured data agrees well with the results predicted by the used model. It is also shown that the DEM technique does not necessarily increase the performance of a DAC when dynamic errors are dominating the achievable performance.

  • 6.
    Baghaei Nejad, Majid
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Shen, Meigen
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Koivisto, Tero
    Univ Turku, Dept Informat Technol.
    Peltonen, Teemu
    Univ Turku, Dept Informat Technol.
    Tjukanoff, Esa
    Univ Turku, Dept Informat Technol.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    UWB radio module design for wireless sensor networks2007In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 50, no 1, p. 47-57Article in journal (Refereed)
    Abstract [en]

    In this paper, we describe an impulse-based ultra wideband (UWB) radio system for wireless sensor network (WSN) applications. Different architectures have been studied for base station and sensor nodes. The base station node uses coherent UWB architecture because of the high performance and good sensitivity requirements. However, to meet complexity, power and cost constraints, the sensor module uses a novel non-coherent architecture that can autonomously detect the UWB signals. The radio modules include a transceiver block, a baseband processing unit and a power management block. The transceiver block includes a Gaussian pulse generator, a multiplier, an integrator and timing circuits. For long range applications, a wideband low noise amplifier (LNA) is included in the transceiver of the sensor module, whereas in short range applications it is simply eliminated to further reduce the power consumption. In order to verify the proposed system concept, circuit level implementation is studied using 1.5 V 0.18 mu m CMOS technology. Finally, the UWB radio modules have been designed for implementation in liquid-crystal-polymer (LCP) based System-on-Package (SOP) technology for low power, low cost and small size integration. A small low cost, double-slotted, Knight's helm antenna is embedded in the LCP substrate, which shows stable characterization and a return loss better than -10 dB over the UWB band.

  • 7.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Carlsson, Mats
    Hedenäs, Charlotta
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Flicker noise conversion in CMOS LC oscillators: capacitance modulation dominance and core device sizing2011In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 68, no 2, p. 145-154Article in journal (Refereed)
    Abstract [en]

    Flicker noise upconversion mechanisms in oscillators have been acquired in the literature, however their relative weights are still under investigation. It is desirable to find the dominant one, since a certain noise suppression method reduces one mechanism but may increase another. In this work, we propose a systematic simulation method to distinguish their relative impacts. The outcome indicates parasitic capacitance is the dominant factor for both tail 1/f noise and switch pair 1/f noise upconversions, implying to use small dimension core devices. Design guidelines on sizing devices are presented and two suppression techniques are compared. Two voltage-controlled oscillators (VCOs) with these suppression techniques are fabricated in a 0.18 mu m CMOS process, allowing us to compare their performance. The two VCOs can be Focused-Ion-Beam (FIB) trimmed to change the width of switch pair FETs. The fair comparison of measurement results among them verify the dominant role of parasitic capacitance in 1/f noise upconversion. The measurement results also confirm the design guidelines and demonstrate the difference of two suppression methods.

  • 8.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A pipelined SAR ADC with gain-stage based on capacitive charge pump2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 90, no 1, p. 43-53Article in journal (Refereed)
    Abstract [en]

    This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.

  • 9.
    Chen, Kairang
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Harikumar, Prakash
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS2016In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 86, no 1, p. 87-98Article in journal (Refereed)
    Abstract [en]

    This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

  • 10.
    Chouhan, Shailesh Sing
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Halonen, Kari
    Department of Micro-and Nanosciences, School of Electrical Engineering, Aalto University .
    Ultra low power beta multiplier-based current reference circuit2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 93, no 3, p. 523-529Article in journal (Refereed)
    Abstract [en]

     This work presents a current reference circuit fabricated in a standard 0.18 μm CMOS technology. The reference current is obtained by applying thermal compensation voltage in the conventional self-biased or beta multiplier-based current reference circuit. Eight prototypes of the proposed architecture were measured which have resulted into the mean reference current of 26.1 nA with the temperature coefficient of 202.1 ppm/°C. These measurements were performed in the temperature range of − 40 to + 85 °C. The circuit is capable of working over the supply voltage range of 1–2 V with the measured mean line sensitivity of 2.18%/V. The maximum measured power dissipation of the circuit is 104 nW at 2 V.

  • 11.
    Duo, Xinzhong
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zheng, Li-Rong
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu R.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Modeling and simulation of spiral inductors in wafer level packaged RF/wireless chips2003In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, no 1, p. 39-47Article in journal (Refereed)
    Abstract [en]

    In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP) RF/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic) simulations. The performance of spiral inductors fabricated with various geometrical and technological parameters was analyzed. It is shown that Q (the quality factor) and f(res) (the self-resonance frequency) could be improved by using the thick insulator layer and thick/wide metal line, which are fabricated by WLP technology. The value of Q could be over 60 at 20 GHz for such embedded components, attesting a significant improvement compared to the conventional on-chip counterparts in CMOS. Through this study, optimal structures for such components are identified and guidelines for design and fabrications are derived. Finally, a method to estimate the inductance of rectangle spiral inductors is developed. It is useful to determine the approximate structure of an inductor quickly before detailed 3D EM simulation, which may cost a long time.

  • 12.
    Duong, Quoc Tai
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Qazi, Fahad
    Catena AB, Stockholm, Sweden .
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering. Linköping University, Faculty of Science & Engineering.
    Analysis and design of low noise transconductance amplifier for selective receiver front-end2015In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 85, no 2, p. 361-372Article in journal (Refereed)
    Abstract [en]

    Analysis and design of a low-noise transconductance amplifier (LNTA) aimed at selective current-mode (SAW-less) wideband receiver front-end is presented. The proposed LNTA uses double cross-coupling technique to reduce noise figure (NF), complementary derivative superposition, and resistive feedback to achieve high linearity and enhance input matching. The analysis of both NF and IIP3 using Volterra series is described in detail and verified by SpectreRF (A (R)) circuit simulation showing NF less than 2 dB and IIP3 = 18 dBm at 3 GHz. The amplifier performance is demonstrated in a two-stage highly selective receiver front-end implemented in 65 nm CMOS technology. In measurements the front-end achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 greater than+17 dBm and blocker P-1dB greater than+5 dBm over frequency range of 0.5-3 GHz.

  • 13.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Bhide, Ameya
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Design and analysis of high-speed split-segmented switched-capacitor DACs2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 92, no 2, p. 199-217Article in journal (Refereed)
    Abstract [en]

    In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area WCu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (WCu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.

  • 14.
    Duong, Quoc-Tai
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Design and Analysis of High Speed Capacitive Pipeline DACs2014In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 80, no 3, p. 359-374Article in journal (Refereed)
    Abstract [en]

    Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

  • 15.
    Eklund, Jan-Erik
    et al.
    Infineon Techn. Linköping.
    Svensson, Christer
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronic Devices.
    Influence of metastability errors on SNR in successive-approximation A/D converters.2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 26, p. 191-198Article in journal (Refereed)
  • 16. Fayed, A. A.
    et al.
    Ismail, Mohammed
    A high speed, low voltage CMOS offset comparator2003In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 36, no 3, p. 267-272Article in journal (Refereed)
    Abstract [en]

    A high speed, low voltage offset comparator is presented. No common mode tracking circuit is used and the offset is added without compromising the high input impedance nature of the circuit. The circuit operates at 480 Mbps with 3.0-3.6 V and 1.6-2.0 V supplies and -40 to 125 degreesC temperature range on a typical 0.5 mum technology.

  • 17. Fayed, A.
    et al.
    Ismail, Mohammed
    A digital calibration algorithm for implementing accurate on-chip resistors2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 47, no 3, p. 259-272Article in journal (Refereed)
    Abstract [en]

    A digital calibration algorithm that provides a systematic method for implementing accurate integrated resistors without compromising linearity or noise performance is described. The technique uses a single external resistor as a reference to implement multiple, different valued integrated resistors without requiring any accurate reference voltage. The algorithm provides a method to calibrate several on-chip resistors without replicating the calibration circuit, and it can achieve an arbitrary accuracy limited only by the external resistor's accuracy and mismatch errors. Terminations for two high speed wire line transceivers are implemented using the algorithm and simulations and measurements results show adequate performance across process, temperature, and supply voltage.

  • 18.
    Fazli Yeknami, Ali
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, p. 69-78Article in journal (Refereed)
    Abstract [en]

    This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

  • 19.
    Fritzin, Jonas
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, p. 241-247Article in journal (Refereed)
    Abstract [en]

    This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

  • 20. Gao, Y. C.
    et al.
    Wikner, J. J.
    Tenhunen, Hannu
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Design and analysis of an oversampling D/A converter in DMT-ADSL systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, p. 201-210Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 mum 3.3 V CMOS process and integrated into the whole DAC chip.

  • 21. Gao, Y. H.
    et al.
    Jia, L. H.
    Isoaho, J.
    Tenhunen, Hannu
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A comparison design of comb decimators for sigma-delta analog-to-digital converters2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 22, no 1, p. 51-60Article in journal (Refereed)
    Abstract [en]

    This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 mu m 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.

  • 22.
    Gao, YC
    et al.
    Royal Inst Technol, Elect Syst Design Lab, S-16440 Kista, Sweden Ericsson Microelect AB, SE-58117 Linkoping, Sweden.
    Wikner, JJ
    Tenhunen, H
    Royal Inst Technol, Elect Syst Design Lab, S-16440 Kista, Sweden Ericsson Microelect AB, SE-58117 Linkoping, Sweden.
    Design and analysis of an oversampling D/A converter in DMT-ADSL systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, p. 201-210Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 mum 3.3 V CMOS process and integrated into the whole DAC chip.

  • 23.
    Gao, Yonghong
    et al.
    Electronic System Design Laboratory, Royal Institute of Technology, Kista.
    Wikner, Jacob
    Ericsson Microelectronics AB, Linköping.
    Tenhunen, Hannu
    Electronic System Design Laboratory, Royal Institute of Technology, Kista.
    Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, p. 201-210Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 μm 3.3 V CMOS process and integrated into the whole DAC chip.

  • 24.
    Gao, Yonghong
    et al.
    Electronic System Design Laboratory, Royal Institute of Technology, Electrum, Kista .
    Wikner, Jacob
    Ericsson Microelectronics AB, Linköping.
    Tenhunen, Hannu
    Electronic System Design Laboratory, Royal Institute of Technology, Electrum, Kista .
    Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, p. 201-210Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunicationapplications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigmadeltamodulators are needed to meet the dynamic performance requirements. This paper presents an oversamplingDAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the highorderone-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limitcycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. Fromour analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator havenon-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients isprovided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented ina 0.6 μm 3.3 V CMOS process and integrated into the whole DAC chip.

  • 25. Gothenberg, A.
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nonlinear quantization in low oversampling ratio sigma-delta noise shapers for RF applications2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 30, no 3, p. 193-206Article in journal (Refereed)
    Abstract [en]

    Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low oversampling ratio in order to achieve the desired baseband width. In this paper, we present system architecture results for the 4th-order cascaded noise shaper architectures to be used in baseband front-ends. We show that the cascaded structures with proper scaling will satisfy simultaneous demand on linearity (spurious free dynamic range) and high SQNR with low oversampling ratio based on usage of multibit quantizers outside the actual signal noise shaping path. We also present results for nonlinear quantization effects in low oversampling ratio cascaded noise shaper architectures. We analyse the effect of the non-linearity in both the A/D and D/A-block in quantization error quantizer path for the 4th-order cascaded topology and the design constraints associated to the performance of the used A/D and D/A structures. The performance requirement for the multi-bit quantizer for high SQNR is shown for the case of low oversampling ratios. The results show that non-uniform quantization around zero input are far more crucial to the SQNR than nonlinear quantization deviating from the ideal transfer function. As the key difference to standard multibit quantizers, no special error correction or error distribution schemes are required; the linearity requirements are satisfied with 0.2 LSB accuracy of the few bit quantizer. Finally, the performance of non-linear quantization using multitone test signals are also shown.

  • 26. Hwang, C.
    et al.
    Hyogo, A.
    Kim, H. S.
    Ismail, Mohammed
    Sekine, K.
    Low voltage high-speed CMOS square-law composite transistor cell2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 25, no 3, p. 347-349Article in journal (Refereed)
    Abstract [en]

    A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \V-t\ +2V(ds,sat) and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 mu m N-well process with a 3 V supply are given.

  • 27. Jonsson, B. E.
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A 3 V wideband CMOS switched-current A/D-converter suitable for time-interleaved operation2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 23, no 2, p. 127-139Article in journal (Refereed)
    Abstract [en]

    The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f(in) = 1.83 MHz, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5 dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 mu m CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR greater than or equal to 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.

  • 28.
    Khan, Hashim Raza
    et al.
    Department of Electronic Engineering, Electronics Design Centre, NED University of Engineering & Technology, Karachi, Pakistan.
    Qureshi, Abdul Raheem
    Department of Electronic Engineering, Electronics Design Centre, NED University of Engineering & Technology, Karachi, Pakistan; Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, Delft, The Netherlands.
    Zafar, Faiza
    Department of Electronic Engineering, Electronics Design Centre, NED University of Engineering & Technology, Karachi, Pakistan.
    Wahab, Qamar ul
    Linköping University, Department of Physics, Chemistry and Biology. Linköping University, Faculty of Science & Engineering.
    Design of a broadband current mode class-D power amplifier with harmonic suppression2016In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 89, no 1, p. 15-24Article in journal (Refereed)
    Abstract [en]

    Current mode class-D power amplifiers (CMCD-PA) are attractive for fully integrated PA implementation as the output capacitance of the active device can be absorbed in the output matching network that can be realized with minimum number of components. This paper presents a simplified design approach for CMCD PA design using an integrated balun transformers. Expressions are derived for the optimum device sizing for second harmonic suppression resulting in improved efficiency. An expression of amplifier efficiency as a function of device size is is presented proving that current mode class-D amplifier yields higher higher efficiency than a class-E amplifier for the same device size. The amplifier is implemented in 130 nm CMOS process and encapsulated in QFN package. Measurement results show that the amplifier exhibits broadband response between 1.4 and 2.1 GHz with peak output power of 26.8 dBm at 1.8 GHz using a 2.4 V supply. PAE remains above 40 % for the entire range while peak PAE is 48 %. Results show a good match between simulation and measurement work. Voltage sweep of the amplifier shows that it can be used in supply modulation based LINC techniques.

  • 29. Kozmin, Kirill
    et al.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Kostamovaara, Joha
    Oulu University.
    A low propagation delay dispersion comparator for a level-crossing AD converter2010In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 62, no 1, p. 51-61Article in journal (Refereed)
    Abstract [en]

    This paper presents the design of a continuous time voltage comparator with low propagation delay dispersion. The comparator is intended to be used as a building block for a level-crossing AD converter: a type of AD converter where the sampling moments are triggered when an input signal crosses predetermined threshold levels. This type of system sets very high demands on the time measurement and the comparator to achieve the desired performance. The comparator design is based on several techniques to minimize the comparator propagation delay dispersion. The comparator has been implemented in a 0.35 μm BiCMOS process. Measured results show good agreement with simulations. The slew rate related propagation delay dispersion is measured to 90 ps for an input frequency range from 3 to 10 MHz and amplitudes from 200 mV to 1.65 V. The comparator static power consumption is 9 mW.

  • 30. Larson, F.
    et al.
    Kascak, P.
    Ismail, Mohammed
    A BiCMOS wideband amplifier for the extraction of base spreading resistance with noise measurement techniques2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 24, no 3, p. 187-194Article in journal (Refereed)
    Abstract [en]

    This paper presents a BiCMOS wide band amplifier optimized for maximum sensitivity to noise introduced in the base spreading resistance. It was used to characterize the base spreading resistance of bipolar devices found in Orbit's low-noise, n-well BiCMOS process available through MOSIS. The base spreading resistance is extracted by measuring the output power spectral density of the aforementioned amplifier and isolating the amount caused by thermal noise in the base. The results give insight as to what noise sources are significant in this technology.

  • 31.
    Li, B. X.
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A second order multi-bit Sigma Delta modulator with single-bit feedback2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 38, no 1, p. 63-72Article in journal (Refereed)
    Abstract [en]

    Multi-bit Sigma Delta modulators suffer from the DAC non-linearity problem and often need complicated Dynamic Element Matching (DEM) circuits. Combining a multi-bit quantizer and a single-bit DAC eliminates the need of DEM circuits, simplifies the design, and reduces the power consumption. Using a digital circuit to compensate the truncation error caused by cutting the multi-bit feedback to single-bit, the structure can achieve the same noise transfer function as a conventional multi-bit modulator. One drawback is that the signal scaling in such a structure lowers the overall resolution. In this paper the influence of signal scaling is analyzed and a design example given. A second order 3-bit modulator is fabricated in 0.35 mum CMOS process, achieving 82 dB dynamic range at OSR 128 and a peak SNDR of 73.1 dB.

  • 32. Li, B. X.
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Design of semi-uniform quantizers and their application in sigma delta A/D converters2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 41, no 03-feb, p. 253-267Article in journal (Refereed)
    Abstract [en]

    In this paper a new type of non-uniform quantizer, semi-uniform quantizer, is introduced. A k-bit semi-uniform quantizer uses the thresholds defined by a (k+1)-bit uniform quantizer and arranges them in such a way that small-amplitude inputs will be quantized by small quantization steps and large-amplitude inputs by large quantization steps. Therefore the total quantization error power could be reduced and the modulator's dynamic range could be increased by 1-bit. The condition for a semi-uniform quantizer to achieve a better performance than a uniform quantizer is analyzed and verified using a second order 3-bit sigma delta modulator prototype chip, fabricated in 0.35 mum CMOS process. At 32 x oversampling ratio the modulator achieves 81 dB dynamic range and 63.8 dB peak SNDR with 3-bit semi-uniform quantizer. With 3-bit uniform quantizer the dynamic range is 70 dB and the peak SNDR is 54.1 dB.

  • 33. Li, S. G.
    et al.
    Ismail, Mohammed
    A 7 GHz 1.5-V dual-modulus prescaler in 0.18 mu m copper-CMOS technology2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 1, p. 89-95Article in journal (Refereed)
    Abstract [en]

    A dual-modulus prescaler using True-Single-Phase-Clock (TSPC) logic is implemented in a 0.18 mum copper CMOS technology. With careful design and optimization the prescaler is able to operate at frequency up to 7.14 GHz at 1.5 V supply voltage. The high-speed operation is attributed to the adoption of the TSPC dynamic logic, and the all copper interconnect CMOS process which has much less interconnect parasitics than conventional aluminum technology. The design facilitates the implementation of a fully integrated RF CMOS phase-locked loop for applications in the 5.8 GHz ISM band such as wireless LAN.

  • 34.
    Nielsen Lönn, Martin
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Angelov, Pavel
    Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Self-powered micro-watt level piezoelectric energy harvesting system with wide input voltage range2019In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 98, no 3, p. 441-451Article in journal (Refereed)
    Abstract [en]

    This paper presents a micro-watt level energy harvesting system for piezoelectric transducers with a wide input voltage range. Many such applications utilizing vibration energy harvesting have a widely varying input voltage and need an interface that can accommodate both low and high input voltages in order to harvest as much energy as possible. The proposed system consists of two rectifiers, both implemented as negative voltage converters followed by active-diodes, and three switched-capacitor DC-DC converters to either step-up or step-down and regulate to the target voltage. The system has been implemented in a 0.18m CMOS process and the chip measures 3mm(2). Measurements show a low voltage drop across the rectifiers and high peak power efficiency of the DC-DC converters (68.7-82.2%) with an input voltage range of 0.45-5.5V for the complete system. Used standalone, the DC-DC converters support input voltages between 0.5 and 11V while maintaining an output voltage of 1.8V at an output power of 16.2W. The ratio of each converter is selectable to be either 1:2, 1:3, or 1:4.

  • 35.
    Nilsson, Joakim
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Department of Physics, Imperial College, London.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    High-temperature characterisation and analysis of leakage-current-compensated, low-power bandgap temperature sensors2017In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 93, no 1, p. 137-147Article in journal (Refereed)
    Abstract [en]

    This paper analyses leakage current compensation techniques for low-power, bandgap temperature sensors. Experiments are conducted for circuits that compensate for collector-substrate, collector-base, body-drain and source-body leakage currents in a Brokaw bandgap sensor. The sensors are characterised and their failure modes are analysed at temperatures from 60 to 230&#x2218;C">230 ∘ C 230∘C . It is found that the most appropriate compensation circuit depends on the accuracy requirements of the application and on whether a stable reference voltage is required by other parts of the circuit. Experiments show that the power consumption is dominated by leakage current at high temperatures. One type of sensor was seen to consume 260 nW at 60&#x2218;C">60 ∘ C 60∘C , 2.1&#x03BC;W">2.1μW 2.1μW at 200&#x2218;C">200 ∘ C 200∘C and 14&#x03BC;W">14μW 14μW at 230&#x2218;C">230 ∘ C 230∘C . This work is motivated by the need to accurately monitor the temperature of power semiconductors in order to predict emerging faults in power semiconductor modules, a task for which cheap, single-chip, low-power, high-temperature, wireless bandgap temperature sensors are appropriate.

  • 36. Park, Seok-Bae
    et al.
    Ismail, Mohammed
    DC offsets in direct conversion multistandard wireless receivers: Modeling and cancellation2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 2, p. 123-130Article in journal (Refereed)
    Abstract [en]

    To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this paper, among many problems in direct conversion receivers, the DC offset problem is studied. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to better understand how the static (or time-invariant) and dynamic (or time-varying) DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed and verified through simulations.

  • 37.
    Pillai, Anu Kalidas Muralidharan
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Johansson, Håkan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Efficient signal reconstruction scheme for M-channel time-interleaved ADCs2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 2, p. 113-122Article in journal (Refereed)
    Abstract [en]

    In time-interleaved analog-to-digital converters (TI-ADCs), the timing mismatches between the channels result in a periodically nonuniformly sampled sequence at the output. Such nonuniformly sampled output limits the achievable resolution of the TI-ADC. In order to correct the errors due to timing mismatches, the output of the TI-ADC is passed through a digital time-varying finite-length impulse response reconstructor. Such reconstructors convert the nonuniformly sampled output sequence to a uniformly spaced output. Since the reconstructor runs at the output rate of the TI-ADC, it is beneficial to reduce the number of coefficient multipliers in the reconstructor. Also, it is advantageous to have as few coefficient updates as possible when the timing errors change. Reconstructors that reduce the number of multipliers to be updated online do so at a cost of increased number of multiplications per corrected output sample. This paper proposes a technique which can be used to reduce the number of reconstructor coefficients that need to be updated online without increasing the number of multiplications per corrected output sample.

  • 38.
    Qin, Yajie
    et al.
    KTH, School of Information and Communication Technology (ICT), Communication Systems, CoS.
    Chen, Qihui
    Hong, Zhiliang
    Signell, Svante R.
    KTH, School of Information and Communication Technology (ICT), Communication Systems, CoS.
    A highly linear 1.2 V 12bit 5-45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 72, no 1, p. 237-241Article in journal (Refereed)
    Abstract [en]

    A 1.2 V 12bit programmable pipelined ADC is presented and implemented in 0.13 mu m CMOS technology. A common-mode-sensing-and-input-interchanged OTA-sharing technique is proposed to address the non-resetting and successive-stage crosstalk issues in conventional OTA-sharing technique. Speed options of 5-45 MS/s are available with scalable power obtained by adjusting the bias currents for OTAs, comparators, and reference buffers, etc., or the global bias current. The measured signal-to-distortion-and-noise ratio is in range of 62.5-69.2 dB, and the peak spurious free dynamic range is 80.7 dB for all speed options, while the figure-of-merit is in the range of 0.26-0.49 pJ/conversion. The core area is 1.5 mm(2).

  • 39.
    Rabén, Hans
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Johansson, Jonny
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Borg, Johan
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    A CMOS Front-end for RFID Transponders Using Multiple Coil Antennas2015In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 83, no 2, p. 149-159Article in journal (Refereed)
    Abstract [en]

    A front-end architecture for inductive RFID transponders using multiple coil antennas for reduced ori- entation sensitivity is presented. The front-end uses multiple antennas for reception and one antenna for transmission. A select function identifies the antenna that is most favorably oriented toward the reader for transmission by comparing the DC charge-up phases of multiple DC generation blocks during power-up of the transponder. CMOS circuit design and simulation results of a front-end for 125 kHz FSK modulation are presented for a pulsed RFID system as well as an archi- tecture for cascaded DC generation. This paper also includes an example of a coil antenna for spherical transponders using three independent orthogonal windings.

  • 40.
    Ramesh, Chithrupa
    et al.
    KTH, School of Electrical Engineering (EES), Automatic Control.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT).
    Skoglund, Mikael
    KTH, School of Electrical Engineering (EES), Communication Theory.
    System co-optimization in wireless receiver design with TrACS2008In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 57, no 1-2, p. 117-127Article in journal (Refereed)
    Abstract [en]

    System co-optimization of the analog receiver front end circuit and the digital baseband processing could enable receiver designs with lower power budgets, as the signal processing in the digital receiver is asymmetric across circuit topologies. This paper presents a simulation tool that could assist with such co-optimized designs. TrACS (Transceiver Architecture and Channel Simulator) is an RF/DSP co-simulator, capable of providing an application-specific system-level perspective to receiver design. The simulator is especially relevant in the context of energy-constrained wireless sensor node design, where the simulator's system perspective determines the compatibility of circuit topologies, modulation techniques and synchronization methods for various wireless scenarios. A few case studies are presented, which illustrate co-optimization of a ZigBEE receiver using TrACS.

  • 41.
    Ramzan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Svensson, Christer
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Multiband RF-Sampling Receiver Front-End with On-Chip Testability in 0.13μm CMOS2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 61, no 2, p. 115-127Article in journal (Refereed)
    Abstract [en]

    In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5–6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 μm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 29 subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole frontend have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.

  • 42.
    Ramzan, Rashad
    et al.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Dabrowski, Jerzy
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    CMOS blocks for on-chip RF test2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 2, p. 151-150Article in journal (Refereed)
    Abstract [en]

    In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.

  • 43. Ravindran, A.
    et al.
    Vidal, E.
    Yoo, S. J.
    Ramarao, K.
    Ismail, Mohammed
    A differential CMOS current-mode variable gain amplifier with digital dB-linear gain control2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 38, no 03-feb, p. 161-174Article in journal (Refereed)
    Abstract [en]

    A novel CMOS variable gain amplifier operating on current signals with a dB-linear gain control is presented. The gain control is achieved by multiplying a digitally synthesized exponentially varying control current signal by a differential input signal in the current domain. A current amplifier at the output sets the gain to the desired level. Current-mode operation allows for a reduced supply voltage by minimizing the voltage swing at the low impedance nodes of the circuit. Multiple circuit realizations for various blocks are presented allowing for designs meeting different constraints. Experimental realization of the variable gain amplifier shows the validity of the presented approach.

  • 44.
    Raza Khan, Hashim
    et al.
    NED University of Engn and Technology, Pakistan .
    Fritzin, Jonas
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    ul Wahab, Qamar
    NED University of Engn and Technology, Pakistan .
    A parallel circuit differential class-E power amplifier using series capacitance2013In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 75, no 1, p. 31-40Article in journal (Refereed)
    Abstract [en]

    Class-E amplifiers are attractive for wireless handsets because of their high efficiency and simple implementation. However, it requires inductors in its output matching network that are inherently low Q components affecting efficiency and may require significantly large area in fully integrated implementation. In this paper a novel approach of implementing parallel circuit differential class-E amplifier is presented. Instead of using an inductor parallel to the transistor drain of each amplifier, a single capacitor at the single ended side of the balun provides the parallel inductance effect to the switching transistors. As a result, number of inductors required for circuit implementation is reduced which means reduced losses, less area and better tuning of reactance can be achieved. A test circuit is implemented in 0.13 mu m CMOS process. Measurement results verify the validity of the concept. The Power Amplifier achieves 22 dBm output power at 2.4 GHz from a 2.5 V with an overall Power Added Efficiency of 38 %.

  • 45.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    ARCHER: an automated RF-IC Rx front-end circuit design tool2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 58, no 3, p. 255-270Article in journal (Refereed)
    Abstract [en]

    This paper presents a tool capable of automatically compiling the circuit of a direct-conversion receiver at the schematics level based on system specifications that include the frequency of operation, gain, noise figure, IIP2 and IIP3 linearity. The front-end of a direct-conversion receiver is built using inductive source degeneration (LSD) LNA and double-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that automatically size the transistors, passive components, and find the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout. Case studies involving WiMAX, UMTS, GSM, Bluetooth and WLAN are presented to reveal the capabilities of the tool in reducing the design time.

  • 46.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A behavioral-based multi-agent optimization algorithm for system level radio design2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 61, no 1, p. 35-46Article in journal (Refereed)
    Abstract [en]

    This paper introduces a multi-agent behavioral-based optimization algorithm for system level radio design. Making multi-standard wireless communication receivers that meet their specs while keeping the requirements of the individual blocks as relaxed as possible is the goal of this algorithm. In order to achieve this goal a "divide and conquer" approach is proposed. Different agents focus on different objectives that are pursued in parallel. Agents adopt different behaviors depending on the status of the environment and their interaction with other agents. Agents are cooperative by default as they try to meet their spec without making changes that affect other agents. However, more aggressive behaviors that lead to global changes can be adopted when needed. The interaction between these simple entities yields an emergent behavior able to deal smoothly with the complexity of the problem at hand.

  • 47.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Borodenkov, A.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A triple-mode sigma-delta modulator for multi-standard wireless radio receivers2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 47, no 2, p. 113-124Article in journal (Refereed)
    Abstract [en]

    A 1.8 V sigma-delta modulator with a 4 bit quantizer has been designed for GSM/WCDMA/WLAN receivers in a 0.18 um CMOS process. The modulator makes use of low-distortion sigma-delta modulator architecture and Pseudo-Data-Weighted-Averaging technique to attain high linearity over a wide bandwidth. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. In GSM mode, the modulator achieves 96/104 dB peak SNR/SFDR over 100 kHz bandwidth and dissipates 18 mW at a sampling frequency of 32 MHz. The modulator achieves 92/68 dB peak SFDR and 77/54 dB peak SNR over a 2 MHz/10 MHz bandwidth and dissipates 23/39 mW at a sampling frequency of 64 MHz/160 MHz in WCDMA/WLAN.

  • 48.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Guest editorial: advanced design techniques for wireless communications2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 58, no 3, p. 179-181Article in journal (Other academic)
  • 49.
    Sadeghifar, Mohammad Reza
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering. Ericsson AB, Sweden.
    Bengtsson, Hakan
    Ericsson AB, Sweden.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters2019In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 100, no 3, p. 683-692Article in journal (Refereed)
    Abstract [en]

    As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radios digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into todays digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

  • 50.
    Sadeghifar, Mohammad Reza
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering. Ericsson AB, Sweden.
    Gustafsson, Oscar
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics2019In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 99, no 2, p. 287-298Article in journal (Refereed)
    Abstract [en]

    Optimization problem formulation for semi-digital FIR digital-to-analog converter (SDFIR DAC) is investigated in this work. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital sigma modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in SDFIR DAC optimization problem formulation. It is shown in this work, that hardware cost of the SDFIR DAC, can be significantly reduced by introducing flexible coefficient precision while the SDFIR DAC is not over designed either. Different use-cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metrics are used in different use cases of optimization problem formulation and solved to find out the optimum set of analog FIR taps. A new method with introducing the variable coefficient precision in optimization procedure was proposed to avoid non-convex optimization problems. It was shown that up to 22% in the total number of unit elements of the SDFIR filter can be saved when targeting the analog metric as the optimization objective subject to magnitude constraint in pass-band and stop-band.

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