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A Fast Sparse Reluctance- and Capacitance-Based Solver for the Partial Element Equivalent Circuit Method
University of L’Aquila.
University of L’Aquila.
Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
2014 (English)In: IEEE transactions on electromagnetic compatibility (Print), ISSN 0018-9375, E-ISSN 1558-187X, Vol. 56, no 5, 1077-1085 p.Article in journal (Refereed) Published
Abstract [en]

A new technique for the reluctance method applied to the Partial Element Equivalent Circuit (PEEC) method for the time domain analysis is presented which is well suited tobe combined with acceleration techniques. In particular, taking advantage of the rank-deficiency of the magnetic and electric field couplings, a new technique for the sparsification of reluctance and capacitance matrices is adopted. Furthermore, the multiscale block decomposition technique has been applied to fast fill these matrices. Finally, the the sparse multifrontal LU factorization has been adopted to efficiently compute the global solution. Numerical results demonstrate the validity of the proposed approach.

Place, publisher, year, edition, pages
2014. Vol. 56, no 5, 1077-1085 p.
Research subject
Industrial Electronics
URN: urn:nbn:se:ltu:diva-9250DOI: 10.1109/TEMC.2014.2314715Local ID: 7d59be26-8fa5-42bf-9b98-a180045c94c0OAI: diva2:982188
Validerad; 2014; 20140303 (jekman)Available from: 2016-09-29 Created: 2016-09-29Bibliographically approved

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Daroui, DaneshEkman, Jonas
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