Fast and Area Efﬁcient Adder for Wide Data in Recent Xilinx FPGAs
2016 (English)Conference paper, Poster (Other academic)
Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. This carry compression was implemented by letting some cells calculate the carry chain in two bits per cell, while some others calculate the summary output bits. In total the proposed design uses no more hardware than the normal adder. The result shows that the proposed adder is faster than a normal adder for word length larger than 64 bits in Virtex-6 FPGAs.
Place, publisher, year, edition, pages
2016. 338-341 p.
IdentifiersURN: urn:nbn:se:liu:diva-131088OAI: oai:DiVA.org:liu-131088DiVA: diva2:967655
26th International Conference on Field-Programmable Logic and Applications, Lausanne, Switzerland August 29 - September 2, 2016