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Graphene Hot-electron Transistors
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-1234-6060
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Graphene base transistors (GBTs) have been, recently, proposed to overcome the intrinsic limitations of the graphene field effect transistors (GFETs) and exploit the graphene unique properties in high frequency (HF) applications. These devices utilize single layer graphene as the base material in the vertical hot-electron transistors. In an optimized GBT, the ultimate thinness of the graphene-base and its high conductivity, potentially, enable HF performance up to the THz region.  This thesis presents an experimental investigation on the GBTs as well as integration process developments for the fabrication of graphene-based devices.

In this work, a full device fabrication and graphene integration process were designed with high CMOS compatibility considerations. To this aim, basic process modules, such as graphene transfer, deposition of materials on graphene, and formation of tunnel barriers, were developed and optimized. A PDMS-supporting graphene transfer process were introduced to facilitate the wet/dry wafer-scale transfer from metal substrate onto an arbitrarily substrate. In addition, dielectric deposition on graphene using atomic layer deposition (ALD) was investigated. These dielectric layers, mainly, served as the base-collector insulators in the fabricated GBTs. Moreover, the integration of silicon (Si) on the graphene surface was studied.

Using the developed fabrication process, the first proof of concept devices were demonstrated. These devices utilized 5 nm-thick silicon oxide (SiO2) and about 20 nm-thick aluminum oxide (Al2O3) as the emitter-base insulator (EBI) and base-collector insulator (BCI). The direct current (DC) functionality of these devices exhibited >104 on/off current ratios and a current transfer ratio of about 6%. The performance of these devices was limited by the non-optimized barrier parameters and device manufacturing technology.

The possibility to improve and optimize the GBT performance was demonstrated by applying different barrier optimization approaches. Comparing to the proof of concept devices, several orders of magnitude higher injection current density was achieved using a bilayer dielectric tunnel barrier. Utilizing the novel TmSiO/TiO2 (1 nm/6 nm) dielectric stack, this tunnel barrier prevents defect mediated tunneling and, simultaneously, promotes the Fowler-Nordheim tunneling (FNT) and step tunneling (ST). Furthermore, it was shown that Si/graphene Schottky junction can significantly improve the current gain by reducing the electron backscattering at the base-collector barrier. In this thesis, a maximum current transfer ratio of about 35% has been achieved.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2016. , xviii, 81 p.
Series
TRITA-ICT, 2016:08
Keyword [en]
Graphene, hot-electron transistors, graphene base transistors, GBT, cross-plane carrier transport, tunneling, ballistic transport, heterojunction transistors, graphene integration, graphene transfer
National Category
Engineering and Technology
Research subject
Information and Communication Technology
Identifiers
URN: urn:nbn:se:kth:diva-186044ISBN: 978-91-7595-932-0 (print)OAI: oai:DiVA.org:kth-186044DiVA: diva2:925052
Public defence
2016-05-26, SAL C, Electrum 229, Kista, 10:00 (English)
Opponent
Supervisors
Funder
EU, FP7, Seventh Framework Programme, 317839EU, European Research Council, 228229
Note

QC 20160503

Available from: 2016-05-03 Created: 2016-04-29 Last updated: 2017-05-23Bibliographically approved
List of papers
1. PDMS-supported Graphene Transfer Using Intermediary Polymer Layers
Open this publication in new window or tab >>PDMS-supported Graphene Transfer Using Intermediary Polymer Layers
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2014 (English)In: PROCEEDINGS OF THE 2014 44TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2014), IEEE, 2014, 309-312 p.Conference paper, Published paper (Refereed)
Abstract [en]

We propose a graphene transfer method based on chemical vapor deposited (CVD) graphene grown on copper foils. This transfer method utilizes a combination of a silicone elastomer (PDMS) and different intermediate polymer layers depending on the process requirements. We use polystyrene and polystyrene/photoresist intermediary layers for dry and wet graphene release. PMMA intermediary layer is applied for bubbling-assisted graphene transfer. The elastomer layer serves as an excellent solid support for electrochemical graphene delamination. Graphene-based field effect transistors (GFETs) were fabricated and characterized using this process. Raman spectroscopy was used in order to verify a successful

Place, publisher, year, edition, pages
IEEE, 2014
Series
Proceedings of the European Solid-State Device Research Conference, ISSN 1930-8876
Keyword
dry transfer, electrochemical, electrolysis, GFET, graphene, transfer, transistor
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-162024 (URN)10.1109/ESSDERC.2014.6948822 (DOI)000348858100074 ()2-s2.0-84911972301 (Scopus ID)978-1-4799-4376-0 (ISBN)
Conference
44th European Solid-State Device Research Conference (ESSDERC), SEP 22-26, 2014, ITALY
Note

QC 20150326

Available from: 2015-03-26 Created: 2015-03-20 Last updated: 2017-01-16Bibliographically approved
2. A Hysteresis-Free High-k Dielectric and Contact Resistance Considerations for Graphene Field Effect Transistors
Open this publication in new window or tab >>A Hysteresis-Free High-k Dielectric and Contact Resistance Considerations for Graphene Field Effect Transistors
2011 (English)In: ECS Transactions, ISSN 1938-5862, E-ISSN 1938-6737, Vol. 41, no 7, 165-171 p.Article in journal (Refereed) Published
Keyword
graphene
National Category
Nano Technology
Identifiers
urn:nbn:se:kth:diva-79349 (URN)10.1149/1.3633296 (DOI)000309539600016 ()2-s2.0-84857328544 (Scopus ID)
Funder
EU, European Research Council
Note

QC 20120209

Available from: 2012-02-08 Created: 2012-02-08 Last updated: 2017-12-07Bibliographically approved
3. A manufacturable process integration approach for graphene devices
Open this publication in new window or tab >>A manufacturable process integration approach for graphene devices
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2013 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 84, 185-190 p.Article in journal (Refereed) Published
Abstract [en]

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Keyword
Graphene, Transistors, Process integration, Hot electrons, Quantum capacitance, Dielectric breakdown
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-124456 (URN)10.1016/j.sse.2013.02.008 (DOI)000319547100026 ()2-s2.0-84879505639 (Scopus ID)
Conference
42nd European Solid-State Device Research Conference (ESSDERC), SEP, 2012, Bordeaux, FRANCE
Note

QC 20130709

Available from: 2013-07-09 Created: 2013-07-05 Last updated: 2017-12-06Bibliographically approved
4. A Graphene-Based Hot Electron Transistor
Open this publication in new window or tab >>A Graphene-Based Hot Electron Transistor
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2013 (English)In: Nano letters (Print), ISSN 1530-6984, E-ISSN 1530-6992, Vol. 13, no 4, 1435-1439 p.Article in journal (Refereed) Published
Abstract [en]

We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call graphene base transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 10(4).

Keyword
Graphene, transistor, hot electrons, hot carrier transport, tunneling
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-122342 (URN)10.1021/nl304305x (DOI)000317549300012 ()2-s2.0-84876059579 (Scopus ID)
Funder
EU, European Research Council, 228229EU, European Research Council, 307311
Note

QC 20130522

Available from: 2013-05-22 Created: 2013-05-20 Last updated: 2017-12-06Bibliographically approved
5. Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors
Open this publication in new window or tab >>Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors
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2015 (English)In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 7, no 30, 13096-13104 p.Article in journal (Refereed) Published
Abstract [en]

Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 103 A cm(-2) (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-172640 (URN)10.1039/c5nr03002a (DOI)000358615200036 ()26176739 (PubMedID)2-s2.0-84937928928 (Scopus ID)
Funder
Swedish Research CouncilEU, European Research Council, 307311
Note

QC 20150827

Available from: 2015-08-27 Created: 2015-08-27 Last updated: 2017-12-04Bibliographically approved
6. Going ballistic: Graphene hot electron transistors
Open this publication in new window or tab >>Going ballistic: Graphene hot electron transistors
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2015 (English)In: Solid State Communications, ISSN 0038-1098, E-ISSN 1879-2766, Vol. 224, 64-75 p.Article in journal (Refereed) Published
Abstract [en]

This paper reviews the experimental and theoretical state of the art in ballistic hot electron transistors that utilize two-dimensional base contacts made from graphene, i.e. graphene base transistors (GBTs). Early performance predictions that indicated potential for THz operation still hold true today, even with improved models that take non-idealities into account. Experimental results clearly demonstrate the basic functionality, with on/off current switching over several orders of magnitude, but further developments are required to exploit the full potential of the GBT device family. In particular, interfaces between graphene and semiconductors or dielectrics are far from perfect and thus limit experimental device integrity, reliability and performance.

Place, publisher, year, edition, pages
Elsevier, 2015
Keyword
Graphene, Hot electron transistors graphene base transistor, GBT, HBT, Ballistic transport, NEGF
National Category
Physical Sciences
Identifiers
urn:nbn:se:kth:diva-180239 (URN)10.1016/j.ssc.2015.08.012 (DOI)000366070300013 ()2-s2.0-84947603528 (Scopus ID)
Note

QC 20160118

Available from: 2016-01-18 Created: 2016-01-08 Last updated: 2017-11-30Bibliographically approved

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