Techniques for High-Speed Digital Delta-Sigma Modulators
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
In this theses techniques for high-speed digital delta-sigma modulator(DDSM) structures are considered. Four techniques are applied andevaluated: unfolding, increasing the number of delay elements in theinner loop, pipelining/retiming, and optimizations provided by thesynthesis tool. Of interest is to see the speed-area-power trade-offs.For implementation, three different modulators meeting the samerequirements are implemented. Each modulator has a 16-bit input andresults in a 3-bit output. The baseline case is a second-ordermodulator, which has one delay element in its inner loop. Throughoptimization, two new structures are found: to provide two delayelements in the inner loop, a fourth-order modulator is required,while to provide three delay elements, a thirteenth-order modulator isobtained.The results show that in general it is better to unfold the modulatorthan to obtain the speed-up through optimizing the arithmeticoperators with the synthesis tool. Using correct pipelining/retimingis also crucial. Finally, for very high-speed implementation, usingthe structures with more delay elements is required. Also, in manycases these are more area and power efficient compared to usingoptimized arithmetic operators, despite their higher computationalcomplexity.
Place, publisher, year, edition, pages
2016. , 48 p.
ASIC, Unfold, Pipeline, Higher Order, digital delta sigma modulator
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-125778ISRN: LiTH-ISY-EX–16/4922–SEOAI: oai:DiVA.org:liu-125778DiVA: diva2:908892
Subject / course
2016-01-25, Nollstället, 10:00 (English)
Syed Asad, Alam