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System-Level Architectural Hardware Synthesis for Digital Signal Processing Sub-Systems
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. (Electronic Systems)ORCID iD: 0000-0002-4157-4487
2015 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

This thesis presents a novel system-level synthesis framework called System-Level Architectural Synthesis Framework (SYLVA), which synthesizes DigitalSignal Processing (DSP) sub-systems modeled by synchronous data ?ow intohardware implementations in Application-Specific Integrated Circuit (ASIC),Field-Programmable Gate Array (FPGA) or Coarse-Grained ReconfigurableArchitecture (CGRA) style. SYLVA synthesizes in terms of pre-characterizedFunction Implementations (FIMPs). It explores the design space in threedimensions, number of FIMPs, type of FIMPs, and pipeline parallelism be-tween the producing and consuming FIMPs. SYLVA also introduces timingand interface model of FIMPs to enable reuse and automatic generation ofGlobal Interconnect and Control (GLIC) to glue the FIMPs together into aworking system. SYLVA has been evaluated by applying it to several realand synthetic DSP applications and the experimental results are analyzedfor the design space exploration, the GLIC synthesis, the code generation,and the CGRA floorplanning features. The conclusion from the experimentalresults is that by exploring the multi-dimensional design space in terms ofpre-characterized FIMPs, SYLVA explores a richer design space and does itmore effectively compared to the existing High-Level Synthesis (HLS) toolsto improve both engineering and computational efficiency.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. , xxii, 193 p.
, TRITA-ICT, ISSN 2015:28
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
URN: urn:nbn:se:kth:diva-180441ISBN: 978-91-7595-799-9OAI: diva2:893852
Public defence
2016-02-18, Sal/hall C, Elektrum, KTH-ICT, Kista, 13:00 (English)

QC 20160125

Available from: 2016-01-25 Created: 2016-01-13 Last updated: 2016-01-25Bibliographically approved

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