The Potential of the Intel (R) Xeon Phi (TM) for Supervised Deep Learning
2015 (English)In: Proceedings: 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security & 2015 IEEE 12th International Conference on Embedded Software and Systems, IEEE Press, 2015, 758-765 p.Conference paper (Refereed)
Supervised learning of Convolutional Neural Networks (CNNs), also known as supervised Deep Learning, is a computationally demanding process. To find the most suitable parameters of a network for a given application, numerous training sessions are required. Therefore, reducing the training time per session is essential to fully utilize CNNs in practice. While numerous research groups have addressed the training of CNNs using GPUs, so far not much attention has been paid to the Intel Xeon Phi coprocessor. In this paper we investigate empirically and theoretically the potential of the Intel Xeon Phi for supervised learning of CNNs. We design and implement a parallelization scheme named CHAOS that exploits both the thread-and SIMD-parallelism of the coprocessor. Our approach is evaluated on the Intel Xeon Phi 7120P using the MNIST dataset of handwritten digits for various thread counts and CNN architectures. Results show a 103.5x speed up when training our large network for 15 epochs using 244 threads, compared to one thread on the coprocessor. Moreover, we develop a performance model and use it to assess our implementation and answer what-if questions.
Place, publisher, year, edition, pages
IEEE Press, 2015. 758-765 p.
Research subject Computer and Information Sciences Computer Science, Computer Science
IdentifiersURN: urn:nbn:se:lnu:diva-47951DOI: 10.1109/HPCC-CSS-ICESS.2015.45ISI: 000380408100115ISBN: 978-1-4799-8937-9OAI: oai:DiVA.org:lnu-47951DiVA: diva2:877421
HPCC 2015, 24-26 Aug.