Low-frequency noise in high-k gate stacks with interfacial layer engineering
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
The rapid progress of complementary-metal-oxide-semiconductor (CMOS) integrated circuit technology became feasible through continuous device scaling. The implementation of high-k/metal gates had a significantcontribution to this progress during the last decade. However, there are still challenges regarding the reliability of these devices. One of the main issues is the escalating 1/fnoise level, which leads to degradation of signal-to-noise ratio (SNR) in electronic circuits. The focus of this thesis is on low-frequency noise characterization and modeling of various novel CMOS devices. The devices include PtSi Schottky-barriers for source/drain contactsand different high-kgatestacksusingHfO2, LaLuO3 and Tm2O3 with different interlayers. These devices vary in the high-k material, high-k thickness, high-k deposition method and interlayermaterial. Comprehensive electrical characterization and low-frequency noise characterization were performed on various devices at different operating conditions. The noise results were analyzed and models were suggested in order to investigate the origin of 1/f noise in these devices. Moreover, the results were compared to state-of-the-art devices.
High constant dielectrics limit the leakage current by offering a higher physical dielectric thickness while keeping the Equivalent Oxide Thickness (EOT) low. Yet, the 1/f noise increases due to higher number of traps in the dielectric and also deterioration of the interface with silicon compared to SiO2. Therefore, in order to improve the interface quality, applying an interfacial layer (IL) between the high-k layer and silicon is inevitable. Very thin, uniform insitu fabricated SiO2 interlayers with HfO2 high-k dielectric have been characterized. The required thickness of SiO2 as IL for further scaling has now reached below 0.5 nm. Thus, one of the main challenges at the current technology node is engineering the interfacial layer in order to achieve both high quality interface and low EOT. High-k ILs are therefore proposed to substitute SiOx dielectrics to fulfill this need. In this work, we have made the first experiments on low-frequency noise studies on TmSiO as a high-k interlayer with Tm2O3 or HfO2 on top as high-k dielectric. The TmSiO/Tm2O3 shows a lower level of noise which is suggested to be related to smoother interface between the TmSiO and Tm2O3. We have achieved excellentnoise performancefor TmSiO/Tm2O3 and TmSiO/HfO2 gate stacks which are comparableto state-of-the-art SiO2/HfO2 gate stacks.
Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. , xv, 60 p.
, TRITA-ICT, 2015:21
CMOS, high k, 1/ f noise, low-frequency noise, number fluctuations, mobility fluctuat ions, traps, interfacial layer, TmSiO, Tm 2O3
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject Information and Communication Technology
IdentifiersURN: urn:nbn:se:kth:diva-177911ISBN: 978-91-7595-751-7OAI: oai:DiVA.org:kth-177911DiVA: diva2:874952
2015-12-18, Sal/hall C, Elektrum, KTH-ICT, Kista, 10:00 (English)
Pavan, Paolo, Professor
Malm, Bengt Gunnar, Associate Professor
QC 201511302015-11-302015-11-302015-11-30Bibliographically approved
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