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Tunable Selective Receiver Front-End with Impedance Transformation Filtering
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
2016 (English)In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, no 5, 1071-1093 p.Article in journal (Refereed) Published
Abstract [en]

A highly selective impedance transformation filtering technique suitable for tunable selective RF receivers is proposed in this paper. To achieve blocker rejection comparable to SAW filters, we use a two stage architecture based on a low noise trans-conductance amplifier (LNTA). The filter rejection is captured by a linear periodically varying (LPV) model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. This model is also used to estimate “back folding” by interferers placed at harmonic frequencies. Discussed is also the effect of thermal noise folding and phase noise on the circuit noise figure. As a proof of concept a chip design of a tunable RF front-end using 65 nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB,out of bandIIP3 > +17 dBm and blocker P1dB > +5 dBm over frequency range of 0.5—3 GHz.

Place, publisher, year, edition, pages
John Wiley & Sons, 2016. Vol. 44, no 5, 1071-1093 p.
Keyword [en]
SAW-less receiver; N-path filter; wideband selective RF front-end
National Category
Condensed Matter Physics
Identifiers
URN: urn:nbn:se:liu:diva-122701DOI: 10.1002/cta.2125ISI: 000376206000009OAI: oai:DiVA.org:liu-122701DiVA: diva2:871754
Available from: 2015-11-16 Created: 2015-11-16 Last updated: 2017-12-01Bibliographically approved
In thesis
1. Efficient Integrated Circuits for Wideband Wireless Transceivers
Open this publication in new window or tab >>Efficient Integrated Circuits for Wideband Wireless Transceivers
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs). This dissertation addresses the key challenges encountered in the design of wideband wireless transceiver ICs. It is divided into two parts. Part I describes the design of crucial circuit blocks such as a highly selective wideband radio frequency (RF) front-end and an on-chip test module which are typically found in wireless receivers. The design of high-speed, capacitive DACs for wireless transmitters is included in Part II.

The first work in Part I is the design and implementation of a wideband RF frontend in 65-nm CMOS. To achieve blocker rejection comparable to surface-acousticwave (SAW) filters, the highly selective and tunable RF receiver utilizes impedance transformation filtering along with a two-stage architecture. It is well known that the low-noise amplifier (LNA) which forms the first front-end stage largely decides the receiver performance in terms of noise figure (NF) and linearity (IIP3/P1dB). The proposed LNA uses double cross-coupling technique to reduce NF while complementary derivative superposition (DS) and resistive feedback are employed to achieve high linearity. The resistive feedback also enhances input matching. In measurements, the front-end achieves performance comparable to SAW filters with blocker rejection greater than 38 dB, NF 3.2–5.2 dB, out-of-band IIP3 > +17 dBm and blocker P1dB > +5 dBm over a frequency range of 0.5–3 GHz.

The second work in Part I is the design of an RF amplitude detector for on-chip test. As the complexity of RF ICs continues to grow, the task of testing and debugging them becomes increasingly challenging. The degradation in performance or the drift from the optimal operation points may cause systems to fail. To prevent this effect and ensure acceptable performance in the presence of process, voltage and temperature variations (PVT), test and calibration of the RF ICs become indispensable. A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is proposed. Gain-boosting and sub-ranging techniques are applied to the detection circuit to increase the gain over the full range of input amplitudes without compromising the input impedance. A technique suitable for on-chip third/second-order intercept  point (IP3/IP2) test by embedded RF detectors is also introduced.

Part II comprises the design and analysis of high-speed switched-capacitor (SC) DACs for 60-GHz radio transmitters. The digital-to-analog converter (DAC) is one of the fundamental building blocks of transmitters. SC DACs offer several advantages over the current-steering DAC architecture. Specifically, lower capacitor mismatch helps the SC DAC to achieve higher linearity. The switches in the SC DAC are realized by MOS transistors in the triode region which substantially relaxes the voltage headroom requirement. Consequently, SC DACs can be implemented using lower supply voltages in advanced CMOS process nodes compared to their currentsteering counterparts. The first work in Part II analyzes the factors limiting the performance of capacitive pipeline DACs. It is shown that the DAC performance is  limited mainly by the clock feed-through and settling effects in the SC  arrays while the impact of capacitor mismatch and kT/C noise are found to be negligible. Based on this analysis, the second work in Part II proposes the split-segmented SC array DAC to overcome the clock feed-through problem since this topology eliminates pipelined charge propagation. Implemented in 65-nm CMOS, the 12-bit SC DAC achieves a Spurious Free Dynamic Range (SFDR) greater than 44 dB within the input signal bandwidth (BW) of 1 GHz with on-chip memory embedded for digital data generation. Power dissipation is 50 mW from 1.2 V supply. Similar performance is achieved with a lower supply voltage (0.9 V) which shows the scalability of the SC DAC for more advanced CMOS technologies. Furthermore, the proposed SC DAC satisfies the spectral mask of the IEEE 802.11ad WiGig standard with a second-order reconstruction filter and hence it can be used for the 60-GHz radio baseband.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2016. 146 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1722
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Communication Systems
Identifiers
urn:nbn:se:liu:diva-124006 (URN)978-91-7685-904-9 (ISBN)
Public defence
2016-02-26, Transformen, Hus B, Campus Valla, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2016-01-18 Created: 2016-01-18 Last updated: 2016-04-07Bibliographically approved
2. Selected Applications of Switched Capacitor Circuits: RF N-Path Filters and ΣΔ Modulators
Open this publication in new window or tab >>Selected Applications of Switched Capacitor Circuits: RF N-Path Filters and ΣΔ Modulators
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Electronic circuits based on switches and capacitors have been used in various applications for several decades. The common switched capacitor (SC) circuits have made their career primarily in analog filters and data converters due to high immunity to capacitance mismatch in integrated circuit (IC) technologies. Recently, also in other fields, circuits using switches and capacitors appeared very attractive. In particular, tunable sampling receiver frontends and N-path RF filters have proven very useful; the latter as a tunable integrated replacement for surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters. In this work addressed are applications of SC technique in ΣΔ modulators and RF bandpass filters.

In a typical receiver frontend the SAW or BAW filters are placed after the antenna to suppress the out-of-band interferers (OBI) that can have power levels as high as 0 dBm. These filters by their nature are neither tunable over frequency nor programmable for different bandwidths. Recently, several SAW-less receivers have been proposed based on the idea of N-path filters that are built with switches and capacitors and driven by N-phase non-overlapping clock. N-path filters make use of baseband impedance upconversion and are tunable with clock frequency. However, with capacitors at baseband, the resulting second order RF filter can only provide a limited blocker rejection.

The first contribution of this work is a tunable zero-IF receiver font-end which employs two 4-path bandpass filters in cascade that operate over the frequency range of (0.5-3) GHz. Each filter section is composed of low noise trans-conductance amplifier (LNTA) and a 4-path structure based on switches and capacitors. The second stage also serves as a downconversion mixer in this architecture. In order to avoid loading effects and thereby guarantee high blocker rejection, a voltage buffer is placed between the stages. The 4-path filter gain is estimated by linear periodically varying (LPV) model which accurately captures the RF filter gain in the presence of parasitic capacitance of the amplifier and the switches. The model is also suited to account for the possible clock phase mismatch effects. Fabricated in CMOS 65 nm technology the measured frontend has achieved out-of-band IIP3 and out-of-band P1dB of +15 dBm and +5 dBm respectively. The NF varies from 3.2 to 5.3 dB at 0.5 GHz to 3 GHz. A blocker rejection of 60 dB is achieved at 0.5 GHz which reduces gradually with frequency to 38 dB at 3 GHz.

Another technique suitable for high rejection filtering at RF is based on subtraction of two bandpass filter responses with slightly different center frequencies. Combining the frequency responses in this way also results in better shaping of the filter passband. The necessary offset frequency can be obtained with one clock frequency and quadrature coupled virtual LC tanks at baseband using gm − C cells. In this work the N-path filter is adopted to serve in a low-IF receiver frontend where the effect of 1/f noise of gm cells can be mitigated. For this purpose, the offset frequencies of both filter branches are chosen to be either positive or negative against the carrier. In this setup the filter is also used as a quadrature downconversion mixer. Importantly, some image rejection is already achieved at RF and it is upto 15 dB after downconversion to IF, relaxing thereby the demands for the ultimate image rejection. Simulated in 65 nm CMOS technology the frontend achieves out-of-band IIP3 of 8 dBm, NF of less than 6 dB while image rejection (IR) at RF and IF is 4.8 dB and 15 dB, respectively.

Another contribution of this work is the design of passive SC ΣΔ modulators for low frequency applications. A low frequency ultra-low-power passive modulator was designed in 65 nm CMOS technology and by exploring the design space it was optimized for signal-to-noise and distortion ratio (SNDR). Using a second order SC filter the modulator demonstrated in measurements SNDR = 67 dB and a figure of merit (FOM) of 0.296 pJ/step, which in a comparative design study was superior to its counterparts, semi-passive and active SC ΣΔ modulators.

Furthermore the analysis and design procedures of passive SC ΣΔ modulator are revisited. Presented is the optimization of the noise transfer function (NTF) of second order passive SC modulator in the design space defined by the filter capacitor ratios and the feedback coefficients. Included is a detailed analysis of the thermal noise of the loop filter and the quantizer. Quantization noise, and other parasitic effects are thoroughly analyzed as well. After the optimization, high level simulations show good compliance with the measurement results. Peak SNDR of 73.7/68.4 dB, DR of 73.4/70.7 dB and MSA of -6.6/-4.3 dBFS is measured in 65 nm CMOS process for the sampling frequency of 500 kHz/250 kHz, respectively, while the attained minimum FOM is 0.17 pJ/step.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. 63 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1627
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112882 (URN)978-91-7519-210-9 (ISBN)
Public defence
2015-01-14, Signalen, Hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2016-01-18Bibliographically approved

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