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Laboratory Test Set-up for the Assessment of PMU Time Synchronization Requirements
KTH, School of Electrical Engineering (EES), Electric Power Systems.ORCID iD: 0000-0002-6090-1674
KTH, School of Electrical Engineering (EES), Electric Power Systems. Statnett SF, Norway.ORCID iD: 0000-0002-4125-1055
2015 (English)Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the construction of a Hardware-in-the-loop laboratory test set-up designed to assess the time synchronization requirements of Phasor Measurement Units (PMUs). The test set-up also allows to investigate the effects of signal phase shifts caused by current and voltage transformers, errors in timing source and the impact of these errors when determining time synchronization compliance of PMUs. The paper also describes the structure of an IRIG-B time-sync real-time implementation, which allowed real-time hardware-in-the-loop simulation by providing a PMU with a high-accuracy timing source.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2015.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-175858DOI: 10.1109/PTC.2015.7232731ISI: 000380546800498Scopus ID: 2-s2.0-84951299222ISBN: 978-147997693-5 (print)OAI: oai:DiVA.org:kth-175858DiVA: diva2:862717
Conference
IEEE PowerTech Conference Eindhoven
Funder
StandUp
Note

QC 20151002

Available from: 2015-10-23 Created: 2015-10-23 Last updated: 2016-10-05Bibliographically approved

Open Access in DiVA

fulltext(1453 kB)48 downloads
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Publisher's full textScopusIEEE PowerTech Conference Eindhoven, 29 juni - 2 juli.

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CiteExportLink to record
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