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Low complexity FPGA based background subtraction technique for thermal imagery
Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.ORCID iD: 0000-0003-1923-3843
Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
2015 (English)In: ACM International Conference Proceeding Series, Association for Computing Machinery (ACM), 2015, 1-6 p.Conference paper, Published paper (Refereed)
Abstract [en]

Embedded smart camera systems are gaining popularity for a number of real world surveillance applications. However, there are still challenges, i.e. variation in illumination, shadows, occlusion, and weather conditions while employing the vision algorithms in outdoor environments. For safety-critical surveillance applications, the visual sensors can be complemented with beyond-visual-range sensors. This in turn requires analysis, development and modification of existing imaging techniques. In this work, a low complexity background modelling and subtraction technique has been proposed for thermal imagery. The proposed technique has been implemented on Field Programmable Gate Arrays (FPGAs) after in-depth analysis of different sets of images, characterizing poor signal-to-noise ratio challenges, e.g. motion of high frequency background objects, temperature variation and camera jitter etc. The proposed technique dynamically updates the background on pixel level and requires a single frame storage as opposed to existing techniques. The comparison of this approach with two other approaches show that this approach performs better in different environmental conditions. The proposed technique has been modelled in Register Transfer Logic (RTL) and implementation on the latest FPGAs shows that the design requires less than 1 percent logics, 47 percent block RAMs, and consumes 91 mW power consumption on Artix-7 100T FPGA.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2015. 1-6 p.
Keyword [en]
Background modelling; subtraction; FPGA; architecture; smart camera, thermal imaging.
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:miun:diva-25997DOI: 10.1145/2789116.2789121Scopus ID: 2-s2.0-84958251961Local ID: STCISBN: 978-145033681-9 (print)OAI: oai:DiVA.org:miun-25997DiVA: diva2:857262
Conference
9th International Conference on Distributed Smart Cameras, ICDSC 2015; Seville; Spain; 8 September 2015 through 11 September 2015; Code 117454
Available from: 2015-09-28 Created: 2015-09-28 Last updated: 2016-12-23Bibliographically approved

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Imran, MuhammadO'Nils, MattiasThörnberg, Benny
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CiteExportLink to record
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