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Simulation and Electrical Evaluation of 4H-SiC Junction Field Effect Transistors and Junction Barrier Schottky Diodes with Buried Grids
KTH, School of Electrical Engineering (EES), Electrical Energy Conversion. Acreo Swedish ICT AB.ORCID iD: 0000-0002-9850-9440
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Silicon carbide (SiC) has higher breakdown field strength than silicon (Si), which enables thinner and more highly doped drift layers compared to Si. Consequently, the power losses can be reduced compared to Si-based power conversion systems. Moreover, SiC allows the power conversion systems to operate at high temperatures up to 250 oC. With such expectations, SiC is considered as the material of choice for modern power semiconductor devices for high efficiencies, high temperatures, and high power densities. Besides the material benefits, the typeof the power device also plays an important role in determining the system performance.

Compared to the SiC metal-oxide semiconductor field-effect transistor (MOSFET) and bipolar junction transistor (BJT), the SiC junction field-effect transistor (JFET) is a very promising power switch, being a voltage-controlled device without oxide reliability issues. Its channel iscontrolled by a p-n junction. However, the present JFETs are not optimized yet with regard to on-state resistance, controllability of threshold voltage, and Miller capacitance.

In this thesis, the state-of-the-art SiC JFETs are introduced with buried-grid (BG) technology.The buried grid is formed in the channel through epitaxial growth and etching processes. Through simulation studies, the new concepts of normally-on and -off BG JFETs with 1200 V blocking capability are investigated in terms of static and dynamic characteristics. Additionally, two case studies are performed in order to evaluate total losses on the system level. These investigations can be provided to a power circuit designer for fully exploiting the benefit of power devices. Additionally, they can serve as accurate device models and guidelines considering the switching performance.

The BG concept utilized for JFETs has been also used for further development of SiC junctionbarrier Schottky (JBS) diodes. Especially, this design concept gives a great impact on high temperature operation due to efficient shielding of the Schottky interface from high electric fields. By means of simulations, the device structures with implanted and epitaxial p-grid formations, respectively, are compared regarding threshold voltage, blocking voltage, and maximum electric field at the Schottky interface. The results show that the device with an epitaxial grid can be more efficient at high temperatures than that with an implanted grid. To realize this concept, the device with implanted grid was optimized using simulations, fabricated and verified through experiments. The BG JBS diode clearly shows that the leakage current is four orders of magnitude lower than that of a pure Schottky diode at an operation temperature of 175 oC and 2 to 3 orders of magnitude lower than that of commercial JBS diodes.

Finally, commercialized vertical trench JFETs are evaluated both in simulations andexperiments, while it is important to determine the limits of the existing JFETs and study their performance in parallel operation. Especially, the influence of uncertain parameters of the devices and the circuit configuration on the switching performance are determined through simulations and experiments.

Abstract [sv]

Kiselkarbid (SiC) har en högre genombrottsfältstyrka än kisel, vilket möjliggör tunnare och mer högdopade driftområden jämfört med kisel. Följaktligen kan förlusterna reduceras jämfört med kiselbaserade omvandlarsystem. Dessutom tillåter SiC drift vid temperatures upp till 250 oC. Dessa utsikter gör att SiC anses vara halvledarmaterialet för moderna effekthalvledarkomponenter för hög verkningsgrad, hög temperature och hög kompakthet. Förutom materialegenskaperna är också komponenttypen avgörande för att bestämma systemets prestanda.

Jämfört med SiC MOSFETen och bipolärtransistorn i SiC är SiC JFETen en mycket lovande component, eftersom den är spänningsstyrd och saknar tillförlitlighetsproblem med oxidskikt. Dess kanal styrs an en PNövergång. Emellertid är dagens JFETar inte optimerade med hänseende till on-state resistans, styrbarhet av tröskelspänning och Miller-kapacitans.

I denna avhandling introduceras state-of-the-art SiC JFETar med buried-grid (BG) teknologi. Denna åstadkommes genom epitaxi och etsningsprocesser. Medelst simulering undersöks nya concept för normally-on och normally-off BG JFETar med blockspänningen 1200 V. Såvä statiska som dynamiska egenskper undersöks. Dessutom görs två fallstudier vad avser totalförluster på systemnivå. Dessa undersökningar kan vara värdefulla för en konstruktör för att till fullo utnyttja fördelarna av komponenterna. Dessutom kan resultaten från undersökningarna användas som komponentmodeller och anvisningar vad gäller switch-egenskaper.

BG konceptet som använts för JFETar har också använts för vidareutveckling av så kallade JBS-dioder. Speciellt ger denna konstruktion stora fördelar vid höga temperature genom en effektiv skärmning av Schottkyövergången mot höga elektriska fält. Genom simuleringar har komponentstrukturer med implanterade och epitaxiella grids jämförst med hänseende till tröskelspänning, genombrottspänning och maximalt elektriskt fält vid Schottky-övergången. Resultaten visar att den epitaxiella varianten kan vara mer effektiv än den implanterade vid höga temperaturer. För att realisera detta concept optimerades en komponent med implanterat grid med hjälp av simuleringar. Denna component tillverkades sedan och verifierades genom experiment. BG JBS-dioden visar tydligt att läckströmmen är fyra storleksordningar lägre än för en ren Schottky-diod vid 175 oC, och två till tre storleksordningar lägre än för kommersiella JBS-dioder.

Slutligen utvärderas kommersiella vertical trench-JFETar bade genom simuleringar och experiment, eftersom det är viktigt att bestämma gränserna för existerande JFETar och studera parallelkoppling. Speciellt studeras inverkan av obestämda parametrar och kretsens konfigurering på switchegenskaperna. Arbetet utförs bade genom simuleringar och experiment.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. , xvi, 97 p.
Series
TRITA-EE, ISSN 1653-5146 ; 2015:025
Keyword [en]
Silicon carbide (SiC), junction field-effect transistors (JFETs), junction barrier schottky diode (JBS), schottky barrier diode (SBD), buried-grid (BG) technology, simulation, implantation, epitaxial growth
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
URN: urn:nbn:se:kth:diva-173340ISBN: 978-91-7595-684-8 (print)OAI: oai:DiVA.org:kth-173340DiVA: diva2:852683
Public defence
2015-10-12, Kollegiesalen, Brinellvägen 8, KTH, Stockholm, 10:15 (English)
Opponent
Supervisors
Note

QC 20150915

Available from: 2015-09-15 Created: 2015-09-09 Last updated: 2015-09-15Bibliographically approved
List of papers
1. Analysis of 1.2 kV SiC buried-grid VJFETs
Open this publication in new window or tab >>Analysis of 1.2 kV SiC buried-grid VJFETs
2010 (English)In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T140, 014008- p.Article in journal (Refereed) Published
Abstract [en]

1.2 kV buried-grid vertical 4H-SiC JFET structures with normally-on (N-on) and normally-off (N-off) designs were investigated by simulation. The static and dynamic characteristics of the devices were determined over a wide range of current, voltage and gate drive conditions in the temperature range -50 degrees C to 250 degrees C. In this paper, the properties of the N-on designs with threshold voltages (V-th) -50 and -10 V are compared with the properties of the N-off design (V-th = 0). For constant V-th, on-resistance decreases and output current increases with increasing channel doping and decreasing channel width. Simulations show that an on-resistance lower than 2 m Omega cm(2) at 250 degrees C can be obtained provided the channel width is smaller than 1.5 and 0.5 mu m for N-on JFETs with V-th = -50 V and V-th = -10 V, respectively, and lower than 3 m Omega cm(2) provided the channel width is smaller than 0.3 mu m for the N-off JFET. At the same time, E-on decreases and E-off increases with increased channel doping concentration and reduced channel width. It is shown that E-on decreases with increasing channel doping concentration due to the reduced channel resistance for the faster turn-on process. E-off increases with increasing channel doping concentration due to the increase in gate-drain capacitance, C-GD.

Keyword
Physics, Multidisciplinary
National Category
Physical Sciences
Identifiers
urn:nbn:se:kth:diva-27661 (URN)10.1088/0031-8949/2010/T141/014008 (DOI)000284694500009 ()2-s2.0-79952386404 (Scopus ID)
Conference
23rd Nordic Semiconductor Community Univ Iceland, Reykjavik, ICELAND, JUN 14-17, 2009
Note
23rd Nordic Semiconductor Community, Univ Iceland, Reykjavik, ICELAND, JUN 14-17, 2009 QC 20101227Available from: 2010-12-27 Created: 2010-12-20 Last updated: 2017-12-11Bibliographically approved
2. Design and gate drive considerations for epitaxial 1.2 kV buried grid N-on and N-off JFETs for operation at 250°C
Open this publication in new window or tab >>Design and gate drive considerations for epitaxial 1.2 kV buried grid N-on and N-off JFETs for operation at 250°C
2010 (English)In: SILICON CARBIDE AND RELATED MATERIALS 2009, PTS 1 AND 2, STAFA-ZURICH: TRANS TECH PUBLICATIONS LTD , 2010, Vol. 645/648, 961-964 p.Conference paper, Published paper (Refereed)
Abstract [en]

The main problem when the conventional PSpice JFET model is used to simulate a vertical short-channel buried-grid JFET is caused by the constant values of Threshold Voltage (VTO) and Transconductance (BETA). This paper presents a new model for the vertical short-channel buried-grid 1200V JFET, where both VTO and BETA vary with respect to the Drain-Source voltage. Simulation data from Medici have been analyzed in order to extract the analytical equations for VTO and BETA. Also other PSpice parameters are extracted from these data. The proposed circuit model has been simulated in Matlab by optimizing the same algorithm that PSpice uses. A variety of results are shown and discussed in this paper.

Place, publisher, year, edition, pages
STAFA-ZURICH: TRANS TECH PUBLICATIONS LTD, 2010
Series
Materials Science Forum, ISSN 0255-5476 ; 645-648
Keyword
Buried-grid Vertical Junction Field Effect Transistor (BG VJFET)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-40814 (URN)10.4028/www.scientific.net/MSF.645-648.961 (DOI)000279657600229 ()2-s2.0-77955436937 (Scopus ID)
Conference
13th International Conference on Silicon Carbide and Related Materials. Nurnberg, GERMANY. OCT 11-16, 2009
Note

QC 20111020

Available from: 2011-09-20 Created: 2011-09-20 Last updated: 2015-09-15Bibliographically approved
3. Comparison of total losses of 1.2 kV SiC JFET and BJT in DC-DC converter including gate driver
Open this publication in new window or tab >>Comparison of total losses of 1.2 kV SiC JFET and BJT in DC-DC converter including gate driver
Show others...
2011 (English)In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679/680, 649-652 p.Article in journal (Refereed) Published
Abstract [en]

The 1.2 kV SiC JFET and BJT devices have been investigated and compared with respect to total losses including the gate driver losses in a DC-DC converter configuration. The buried grid, Normally-on JFET devices with threshold voltage of -50 V and -10V are compared to BJT devices with ideal semiconductor and passivating insulator interface and an interface with surface recombination velocity of 4.5·104 cm/s yielding agreement to the reported experimental current gain values. The conduction losses of both types of devices are independent of the switching frequency while the switching losses are proportional to the switching frequency. The driver losses are proportional to the switching frequency in the JFET case but to a large extent independent of the switching frequency in the BJT case. The passivation of the emitter junction modeled here by surface recombination velocity has a significant impact on conduction losses and gate driver losses in the investigated BJT devices.

Keyword
unction Field Effect Transistors (JFETs), Bipolar Junction Transistors (BJT)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
SRA - Energy
Identifiers
urn:nbn:se:kth:diva-40815 (URN)10.4028/www.scientific.net/MSF.679-680.649 (DOI)000291673500156 ()2-s2.0-79955079825 (Scopus ID)
Conference
8th European Conference on Silicon Carbide and Related Materials. Sundvolden Conf Ctr, Oslo, NORWAY. AUG 29-SEP 02, 2010
Funder
StandUp
Note

QC 20111020

Available from: 2011-09-20 Created: 2011-09-20 Last updated: 2017-12-08Bibliographically approved
4. Merits of Buried Grid Technology for Advanced SiC Device Concepts
Open this publication in new window or tab >>Merits of Buried Grid Technology for Advanced SiC Device Concepts
2011 (English)In: GALLIUM NITRIDE AND SILICON CARBIDE POWER TECHNOLOGIES, 2011, Vol. 41, no 8, 155-162 p.Conference paper, Published paper (Refereed)
Abstract [en]

Selected examples of the use of buried grid technology for SiC devices are discussed. First example is development of normally-off and normally-on JFETs, Second the development of Schottky barrier diodes for 250 degrees C operation. Other examples are efficient junction termination and avalanche UV detectors. Experimental results are used in support of simulations.

Series
ECS Transactions, ISSN 1938-5862
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-173346 (URN)10.1149/1.3631493 (DOI)000309600300014 ()2-s2.0-84857354398 (Scopus ID)978-1-60768-262-2 (ISBN)
Conference
Symposium on GaN and SiC Power Technologies held during the 220th Meeting of the Electrochemical-Society, OCT 09-14, 2011, Boston, MA
Note

QC 20150910

Available from: 2015-09-10 Created: 2015-09-10 Last updated: 2015-09-15Bibliographically approved
5. High-Power Modular Multilevel Converters With SiC JFETs
Open this publication in new window or tab >>High-Power Modular Multilevel Converters With SiC JFETs
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2012 (English)In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 27, no 1, 28-36 p.Article in journal (Refereed) Published
Abstract [en]

This paper studies the possibility of building a modular multilevel converter (M2C) using silicon carbide (SiC) switches. The main focus is on a theoretical investigation of the conduction losses of such a converter and a comparison to a corresponding converter with silicon-insulated gate bipolar transistors. Both SiC BJTs and JFETs are considered and compared in order to choose the most suitable technology. One of the submodules of a down-scaled 3 kVA prototype M2C is replaced with a submodule with SiC JFETs without antiparallel diodes. It is shown that the diode-less operation is possible with the JFETs conducting in the negative direction, leaving the possibility to use the body diode during the switching transients. Experimental waveforms for the SiC submodule verify the feasibility during normal steady-state operation. The loss estimation shows that a 300 MW M2C for high-voltage direct current transmission would potentially have an efficiency of approximately 99.8% if equipped with future 3.3 kV 1.2 kA SiC JFETs.

Place, publisher, year, edition, pages
IEEE Press, 2012
Keyword
Diodeless operation, high voltage directcurrent transmission, modular multilevel converter, SiC JFETs, silicon carbide
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-52687 (URN)10.1109/TPEL.2011.2155671 (DOI)000298048500001 ()2-s2.0-83655192819 (Scopus ID)
Note
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. QC 20111220Available from: 2011-12-20 Created: 2011-12-19 Last updated: 2017-12-08Bibliographically approved
6. Merits of Buried Grid Technology for SiC JBS Diodes
Open this publication in new window or tab >>Merits of Buried Grid Technology for SiC JBS Diodes
2012 (English)In: GALLIUM NITRIDE AND SILICON CARBIDE POWER TECHNOLOGIES 2, 2012, Vol. 50, no 3, 415-424 p.Conference paper, Published paper (Refereed)
Abstract [en]

The SiC Schottky barrier diodes for 200 degrees C to 250 degrees C operation have been developed using buried grid (BG) technology. 2A and 10A, 1700V BG JBS diodes have been fabricated and evaluated. Manufactured 10A, 1700V BG JBS diodes have leakage current at least three orders of magnitude lower compared to the typical data sheet values of the commercial devices. The leakage current at 250 degrees C is of the same order of magnitude as that of the commercial devices at 175 degrees C. The two alternative technologies for realization of BG, implantation and epitaxy, have been compared by simulations. The epitaxial grid is shown to have superior potential for best trade-off between on-state voltage and leakage current.

Series
ECS Transactions, ISSN 1938-5862
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-173347 (URN)10.1149/05003.0415ecst (DOI)000337755900045 ()2-s2.0-84885750739 (Scopus ID)978-1-60768-351-3 (ISBN)
Conference
2nd Symposium on Gallium Nitride (GaN) and Silicon Carbide (SiC) Power Technologies as part of ECS Fall Meeting, OCT 07-12, 2012, Honolulu, HI
Note

QC 20150910

Available from: 2015-09-10 Created: 2015-09-10 Last updated: 2015-09-15Bibliographically approved
7. Modeling of the impact of parameter spread on the switching performance of parallel-connected SiC VJFETs
Open this publication in new window or tab >>Modeling of the impact of parameter spread on the switching performance of parallel-connected SiC VJFETs
Show others...
2013 (English)In: Materials Science Forum, Trans Tech Publications Inc., 2013, 1098-1102 p.Conference paper, Published paper (Refereed)
Abstract [en]

Operation of parallel-connected 4H-SiC VJFETs from SemiSouth was measured and modeled using numerical simulations. The unbalanced current waveforms in parallel-connected VJFETs were related to spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The physical device structure was reconstructed based on SEM analysis, electrical characterization, and device simulations. The two hypothetical critical design parameters that were studied with respect to spread were the p-gate doping profile (Case 1) and the emitter doping (Case 2). Variation in both parameters could be related to variation in the emitter breakdown voltage, the on-state characteristics, and the threshold voltage of the experimental devices. The switching performance of the parallel-connected JFETs was measured using a single gate driver in a double pulse test and compared with simulations. In both investigated cases a very good agreement between measurements and simulations was obtained. The modeling of the transient performance relies on good reproduction of transfer characteristics and circuit parasitics.

Place, publisher, year, edition, pages
Trans Tech Publications Inc., 2013
Series
Materials Science Forum, ISSN 0255-5476 ; 740-742
Keyword
Medici, Parallel connection, SiC, VJFET (Vertical Junction Field Effect Transistor), Critical design parameters, Critical parameter, Device simulations, Device structures, Doping profiles, Double pulse, Electrical characterization, Emitter doping, Experimental devices, Measurement circuit, On state, Parallel connections, Parallel-connected, Parasitic inductances, Parasitics, Physical devices, SEM analysis, Single gates, Switching performance, Transfer characteristics, Transient performance, Unbalanced currents, Vertical junction field effect transistors, Wave forms, Electric connectors, Field effect transistors, Heterojunction bipolar transistors, Silicon carbide
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
SRA - Energy
Identifiers
urn:nbn:se:kth:diva-134687 (URN)10.4028/www.scientific.net/MSF.740-742.1098 (DOI)000319785500262 ()2-s2.0-84874056771 (Scopus ID)9783037856246 (ISBN)
Conference
9th European Conference on Silicon Carbide and Related Materials, ECSCRM 2012, 2 September 2012 through 6 September 2012, St. Petersburg
Funder
StandUp
Note

QC 20131129

Available from: 2013-11-29 Created: 2013-11-27 Last updated: 2016-02-26Bibliographically approved
8. Analysis and Experimental Verification of the Influence of Fabrication Process Tolerances and Circuit Parasitics on Transient Current Sharing of Parallel-Connected SiC JFETs
Open this publication in new window or tab >>Analysis and Experimental Verification of the Influence of Fabrication Process Tolerances and Circuit Parasitics on Transient Current Sharing of Parallel-Connected SiC JFETs
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2014 (English)In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 29, no 5, 2180-2191 p.Article in journal (Refereed) Published
Abstract [en]

Operation of parallel-connected 4H-SiC vertical junction field effect transistors (VJFETs) from SemiSouth is modeled using numerical simulations and experimentally verified. The unbalanced current waveforms of parallel-connected VJFETs are investigated with respect to the spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The device structures are reconstructed based on scanning electron microscopy (SEM) analysis, electrical characterization, and device simulations. The doping concentration and profile depth of a p-grid formed by angular implantation are studied as main contributors that influence the variation of the on-state characteristics, and the threshold voltage of the experimental devices. It has been shown elsewhere that similar differences in p-grid also lead to differences in gate-source breakdown voltage. The switching performance of the parallel-connected JFETs is measured using single and double gate drivers in a double-pulse test and compared with simulations. The switched current and voltage waveforms from measurements are reproduced in simulation by introducing the parasitics. From the analysis, it is found that reasonable differences in doping levels and profiles of the p-grid give rise to significant differences in device parameters. However, even with these parameter differences and circuit asymmetries, it is possible to successfully operate parallel-connected VJFETs of this type.

Place, publisher, year, edition, pages
IEEE, 2014
Keyword
Medici, parallel connection, silicon carbide (SiC), vertical junction field effect transistor (VJFET)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
SRA - Energy
Identifiers
urn:nbn:se:kth:diva-141275 (URN)10.1109/TPEL.2013.2281084 (DOI)000329991500005 ()2-s2.0-84893148878 (Scopus ID)
Funder
StandUp
Note

QC 20140213

Available from: 2014-02-13 Created: 2014-02-13 Last updated: 2017-12-06Bibliographically approved
9. Evaluation of buried grid JBS diodes
Open this publication in new window or tab >>Evaluation of buried grid JBS diodes
Show others...
2014 (English)In: 15th International Conference on Silicon Carbide and Related Materials, ICSCRM 2013, Trans Tech Publications Inc., 2014, 804-807 p.Conference paper, Published paper (Refereed)
Abstract [en]

The 4H-SiC Schottky barrier diodes for high temperature operation over 200 °C have been developed using buried grids formed by implantation. Compared to a conventional JBS-type SBD with surface grid (SG), JBS-type SBD with buried grid (BG) has significantly reduced leakage current at reverse bias due to a better field shielding of the Schottky contact. By introducing the BG technology, the 1.7 kV diodes with an anode area 0.0024 cm2 (1 A) and 0.024 cm2 (10 A) were successfully fabricated, encapsulated in TO220 packages, and electrically evaluated. Two types of buried grid arrangement with different grid spacing dimensions were investigated. The measured IV characteristics were compared with simulation. The best fit was obtained with an active area of approximately 60% and 70% of the anode area in large and small devices, respectively. The measured values of the device capacitances were 1000 pF in large devices and 100 pF in small devices at zero bias. The capacitance values are proportional to the device area. The recovery behavior of big devices was measured in a double pulse tester and simulated. The recovery charge, Qc, was 18 nC and 24 nC in simulation and measurement, respectively. The fabricated BG JBS-type SBDs have a smaller maximum reverse recovery current compared to the commercial devices. No influence of the different grid spacing on the recovery charge was observed.

Place, publisher, year, edition, pages
Trans Tech Publications Inc., 2014
Keyword
4H-SiC, Buried grid (BG), Junction barrier schottky (JBS) diode, Schottky barrier diode (SBD), Diodes, High temperature operations, Recovery, Schottky barrier diodes, Commercial Devices, IV characteristics, Junction barrier Schottky diodes, Reverse recovery current, Schottky Barrier Diode(SBD), Simulations and measurements, Silicon carbide
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
SRA - Energy
Identifiers
urn:nbn:se:kth:diva-167927 (URN)10.4028/www.scientific.net/MSF.778-780.804 (DOI)000336634100190 ()2-s2.0-84896087187 (Scopus ID)9783038350101 (ISBN)
Conference
29 September 2013 through 4 October 2013, Miyazaki
Funder
StandUp
Note

QC 20150608

Available from: 2015-06-08 Created: 2015-05-22 Last updated: 2016-02-26Bibliographically approved
10. High temperature capable SiC Schottky diodes, based on buried grid design
Open this publication in new window or tab >>High temperature capable SiC Schottky diodes, based on buried grid design
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2014 (English)In: International Conference and Exhibition on High Temperature Electronics, 2014, 158-160 p.Conference paper, Published paper (Refereed)
Abstract [en]

Electrical characteristics of 4H-SiC Schottky barrier diodes, based on buried grid design are presented. The diodes, rated to 1200V/10A and assembled into high temperature capable T0254 packages, have been tested and studied up to 250°C. Compared to conventional SiC Schottky diodes, Ascatron’s buried grid SiC Schottky diode demonstrates several orders of magnitude reduced leakage current at high temperature operation.

Keyword
Diodes; High temperature operations; Silicon carbide, Electrical characteristic; Grid design; High temperature; Orders of magnitude; SiC Schottky diode, Schottky barrier diodes
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-173349 (URN)2-s2.0-84916223864 (Scopus ID)
Conference
IMAPS International Conference and Exhibition on High Temperature Electronics, HiTEC 2014
Note

 QC 20150910

Available from: 2015-09-10 Created: 2015-09-10 Last updated: 2015-09-15Bibliographically approved
11. Temperature-Dependent Characteristics of 4H-SiC Buried Grid JBS Diodes
Open this publication in new window or tab >>Temperature-Dependent Characteristics of 4H-SiC Buried Grid JBS Diodes
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2015 (English)In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821/823, 600-603 p.Article in journal (Refereed) Published
Abstract [en]

4H-SiC Schottky Barrier Diodes (SBD) have been developed using p-type buried grids (BGs) formed by Al implantation. In order to reduce on-state resistance and improve forward conduction, the doping concentration of the channel region between the buried grids was increased. The fabricated diodes were encapsulated with TO-254 packages and electrically evaluated. Experimental forward and reverse characteristics were measured in the temperature range from 25 °C to 250 °C. On bare die level, the forward voltage drop was reduced from 5.36 V to 3.90 V at 20 A as the channel doping concentration was increased, which introduced a low channel resistance. By the encapsulation in TO-254 package, the forward voltage drop was decreased approximately 10% due to a lower contact resistance. The on-state resistance of the identical device measured on bare die and in TO-254 package increased with increasing temperature due to the decreased electron mobility in the drift region resulting in higher resistance. The incremental contact resistances of the bare dies were larger than in the packaged devices. One key issue associated with conventional Junction Barrier Schottky (JBS) diodes is a high leakage current at high temperature operation over 200 °C. The developed Buried Grid JBS (BG JBS) diode has significantly reduced leakage current due to a better field shielding at the Schottky contact. The leakage current of the packaged BG JBS diodes is compared to pure SBD and commercial JBS diodes.

Place, publisher, year, edition, pages
Trans Tech Publications Inc., 2015
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
SRA - Energy
Identifiers
urn:nbn:se:kth:diva-173353 (URN)10.4028/www.scientific.net/MSF.821-823.600 (DOI)2-s2.0-84950327389 (Scopus ID)
Funder
StandUp
Note

QC 20150910

Available from: 2015-09-10 Created: 2015-09-10 Last updated: 2017-12-04Bibliographically approved

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Lim, Jang-Kwon

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Lim, Jang-Kwon
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Electrical Energy Conversion
Electrical Engineering, Electronic Engineering, Information Engineering

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