A 11-GS/s 1.1-GHz Bandwidth Interleaved ΔΣ DAC for 60-GHz Radio in 65-nm CMOS
2015 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 50, no 10, 2306-2310 p.Article in journal (Refereed) Published
This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.
Place, publisher, year, edition, pages
IEEE , 2015. Vol. 50, no 10, 2306-2310 p.
ΔΣ DAC; 60 GHz radio; High speed; IEEE 80211ad; MASH; WiGig; time-interleaving
Signal Processing Computer Science
IdentifiersURN: urn:nbn:se:liu:diva-120624DOI: 10.1109/JSSC.2015.2460375ISI: 000362359700008OAI: oai:DiVA.org:liu-120624DiVA: diva2:847195
Funding text: Swedish Foundation for Strategic Research (SSF); Swedish Research Council (VR); Swedish Innovation Agency (VINNOVA)2015-08-192015-08-192015-11-03Bibliographically approved