Implementation and Evaluation of Update-Based Cache Protocols Under Relaxed Memory Consistency Models
Blekinge Institute of Technology, Department of Computer Science and Business Administration1995 (English)In: Future Generations Computer Systems, ISSN 0167-739X , Vol. 11, no 3, 247-271 p.Article in journal (Refereed) Published
The protocols of invalidation-based cache coherence have been extensively studied in the context of large-scale shared-memory multiprocessors. Under a relaxed memory consistency model, most of the write latency can be hidden whereas cache misses still incur a severe performance problem. By contrast, update-based protocols have a potential to reduce both write and read penalties under relaxed memory consistency models because coherence misses can be completely eliminated. This paper compares update- and invalidation-based protocols for their ability to reduce or hide memory access latencies and for their ease of implementation under relaxed memory consistency models.
Place, publisher, year, edition, pages
Amsterdam: North-Holland , 1995. Vol. 11, no 3, 247-271 p.
Multiprocessing systems, Buffer storage, Storage allocation (computer), Network protocols, Computer simulation, Synchronization, Computer hardware, Large scale systems, Performance
IdentifiersURN: urn:nbn:se:bth-10087Local ID: oai:bth.se:forskinfo44852BCE2ED55610C12568A3002CAB4FOAI: oai:DiVA.org:bth-10087DiVA: diva2:838116