Modelling a 10 Gbits/Port Shared Memory ATM Switch
Blekinge Institute of Technology, Department of Telecommunications and Mathematics1997 (English)Conference paper (Refereed) Published
The speed of optical transmission links is growing at a rate which is difficult for the microelectronic technology of ATM switches to follow. In order to cover the transmission rate gap between optical transmission links and ATM switches, ATM switches operating at multi Gbit/s rate have to be developed. A 10 Gbit/s/port shared memory ATM switch is under development at Linkoping Institute of Technology (LiTH) and Lund Institute of Technology (LTH) in Sweden. It has 8 inputs and 8 outputs. The switch will be implemented on a single chip in 0.8 μm BiCMOS. We report on a performance analysis of the switch under a specific traffic model. This traffic model emulates the LAN type of traffic. Performance analysis is crucial for evaluating and dimensioning the very high speed ATM switch
Place, publisher, year, edition, pages
Atlanta, Georgia, U.S.A. : IEEE , 1997.
IdentifiersURN: urn:nbn:se:bth-9810Local ID: oai:bth.se:forskinfo8B041633B4DBEBC0C12568A3002CA9D6ISBN: 0-7803-4278-XOAI: oai:DiVA.org:bth-9810DiVA: diva2:837758
Winter Simulation Conference
This article is written under the Project "Modelling of Bursty Traffics"2012-09-182000-03-152015-06-30Bibliographically approved