Hardware design and implementation of the Schmidl-Cox synchronization algorithm for an OFDM transceiver
Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
The subject of this document is the VHDL firmware implementation of a coarse synchronization method for a 4G/5G transceiver. The method of choice is the Schmidl-Cox synchronization algorithm that is applied to the OFDM transmission standard as preparation for later conversion to the FBMC method. This algorithm is first developed and validated in a MATLAB floating point environment. After this a thorough analysis step is conducted to devise a fixed point implementation of negligible perfor- mance loss. Thereafter a main contribution of this work comes through the proposal of a low-complexity hardware architecture that efficiently implements this fixed point Schmidl-Cox algorithm. This architecture is described in VHDL and validated through extensive simulations after integration with the transceiver model. Simulation results and logic syn- thesis targeting a Zynq 7020 FPGA board illustrate the efficiency of the proposed implementation.
Place, publisher, year, edition, pages
2015. , 48 p.
UPTEC F, ISSN 1401-5757 ; 15037
Engineering and Technology
IdentifiersURN: urn:nbn:se:uu:diva-256069OAI: oai:DiVA.org:uu-256069DiVA: diva2:824514
Master Programme in Engineering Physics
2015-06-18, Uppsala, 14:00 (English)
Nyberg, TomasGustafsson, Leif