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Improvements in High-Coverage and Low-Power LBIST
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Testing cost is one of the major contributors to the manufacturing cost of integrated circuits. Logic Built-In Self Test (LBIST) offers test cost reduction in terms of using smaller and cheaper ATE, test data volume reduction due to on-chip test pattern generation, test time reduction due to at-speed test pattern application. However, it is difficult to reach a sufficient test coverage with affordable area overhead using LBIST. Also, excessive power dissipation during test due to the random nature of LBIST patterns causes yield-decreasing problems such as IR-drop and overheating.

In this dissertation, we present techniques and algorithms addressing these problems.

In order to increase test coverage of LBIST, we propose to use on-chip circuitry to store and generate the "top-off" deterministic test patterns. First, we study the synthesis of Registers with Non-Linear Update (RNLUs) as on-chip sequence generators. We present algorithms constructing RNLUs which generate completely and incompletely specified sequences. Then, we evaluate the effectiveness of RNLUs generating deterministic test patterns on-chip. Our experimental results show that we are able to achieve higher test coverage with less area overhead compared to test point insertion. Finally, we investigate the possibilities of integrating the presented on-chip deterministic test pattern generator with existing Design-For-Testability (DFT) techniques with a case study.

The problem of excessive test power dissipation is addressed with a scan partitioning algorithm which reduces capture power for delay-fault LBIST. The traditional S-graph model for scan partitioning does not quantify the dependency between scan cells. We present an algorithm using a novel weighted S-graph model in which the weights are scan cell dependencies determined by signal probability analysis. Our experimental results show that, on average, the presented method reduces average capture power by 50% and peak capture power by 39% with less than 2% drop in the transition fault coverage. By comparing the proposed algorithm to the original scan partitioning, we show that the proposed method is able to achieve higher capture power reduction with less fault coverage drop.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2015. , xi, 84 p.
Series
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 15:05
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-165463ISBN: 978-91-7595-538-4 (print)OAI: oai:DiVA.org:kth-165463DiVA: diva2:808495
Public defence
2015-06-01, Sal A, Isafjordsgatan 26, Kista, 13:00 (English)
Opponent
Supervisors
Note

QC 20150508

Available from: 2015-05-08 Created: 2015-04-28 Last updated: 2015-05-08Bibliographically approved
List of papers
1. Synthesis of Power- and Area-Efficient Binary Machines for Incompletely Specified Sequences
Open this publication in new window or tab >>Synthesis of Power- and Area-Efficient Binary Machines for Incompletely Specified Sequences
2014 (English)In: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2014, 634-639 p.Conference paper, Published paper (Refereed)
Abstract [en]

Binary Machines (BMs) are a generalization of Linear Feedback Shift Registers (LFSRs) in which a current state is a nonlinear function of the previous state. It is known how to construct a BM generating a given completely specified binary sequence. In this paper, we present an algorithm which can efficiently handle the case of incompletely specified sequences. Our experimental results show that it significantly outperforms the approaches based on all-0 or random fill in both area and power dissipation. On average, it reduces dynamic power dissipation twice compared to all-0 fill approach and 6 times compared to random fill approach. The presented algorithm can potentially be useful for many applications, including Logic Built-In Self Test (LBIST).

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-136346 (URN)10.1109/ASPDAC.2014.6742962 (DOI)000350791700113 ()2-s2.0-84897842896 (Scopus ID)978-147992816-3 (ISBN)
Conference
19th Asia and South Pacific Design Automation Conference
Funder
VINNOVA, 2011-03336Swedish Foundation for Strategic Research , SM12-0005
Note

QC 20140313

Available from: 2013-12-04 Created: 2013-12-04 Last updated: 2015-05-08Bibliographically approved
2. An Algorithm for Constructing a Minimal Register with Non-Linear Update Generating a Given Sequence
Open this publication in new window or tab >>An Algorithm for Constructing a Minimal Register with Non-Linear Update Generating a Given Sequence
2014 (English)In: Proceedings of 2014 IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL), 2014, 254-259 p.Conference paper, Published paper (Refereed)
Abstract [en]

Registers with Non-Linear Update (RNLUs) are a generalization of Non-Linear Feedback Shift Registers (NLFSRs) in which both, feedback and feedforward, connections are allowed and no chain connection between the stages is required. An RNLU can be used to generate any given 2p-ary sequence, p ≥ 1. In this paper, a new algorithm for constructing RNLUs is presented. Expected size of RNLUs constructed by the presented algorithm is proved to be asymptotically smaller than the expected size of RNLUs constructed by previous algorithms generating the same sequence. The presented algorithm can potentially be useful for applications such as testing, wireless communications, and cryptography.

National Category
Computer Science
Research subject
Computer Science
Identifiers
urn:nbn:se:kth:diva-165459 (URN)10.1109/ISMVL.2014.52 (DOI)000361020700043 ()2-s2.0-84904460383 (Scopus ID)
Conference
44th International Symposium on Multiple-Valued Logic (ISMVL)
Note

QC 20150508

Available from: 2015-04-28 Created: 2015-04-28 Last updated: 2015-10-05Bibliographically approved
3. Area-efficient high-coverage LBIST
Open this publication in new window or tab >>Area-efficient high-coverage LBIST
2014 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 38, no 5, 368-374 p.Article in journal (Refereed) Published
Abstract [en]

Logic Built-In Self Test (LBIST) is a popular technique for applications requiring in-field testing of digital circuits. LBIST incorporates test generation and response-capture on-chip. It requires no interaction with a large, expensive tester. LBIST offers test time reduction due to at-speed test pattern application, makes possible test data re-usability at many levels, and enables test-ready IP. However, the traditional pseudo-random pattern-based LBIST often has a low test coverage. This paper presents a new method for on-chip generation of deterministic test patterns based on registers with non-linear update. Our experimental results on 7 real designs show that the presented approach can achieve a higher stuck-at coverage than the test point insertion with less area overhead. We also show that registers with non-linear update are asymptotically smaller than memories required to store the same test patterns in a compressed form.

Keyword
LBIST, LFSR, Top-off test patterns, In-field testing, Test compression
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-150537 (URN)10.1016/j.micpro.2014.05.002 (DOI)000340300900002 ()2-s2.0-84901824272 (Scopus ID)
Note

QC 20140908

Available from: 2014-09-08 Created: 2014-09-05 Last updated: 2017-12-05Bibliographically approved
4. Evaluation of Alternative LBIST Flows: A Case Study
Open this publication in new window or tab >>Evaluation of Alternative LBIST Flows: A Case Study
2014 (English)In: Proceedings of 32nd Nordic Microelectronics Conference (NORCHIP'2014), 2014Conference paper, Published paper (Refereed)
Abstract [en]

The cost of manufacturing test has been growing dramatically over the years. The traditional pseudo-random pattern based Logic Built-in Self Test (LBIST) can potentially reduce the test cost by minimizing the need for the automatic test equipment. However, LBIST test coverage can be unaccept-ably low for some designs. Various methods for complementing pseudo-random patterns to increase test coverage exist, but the combined effect of these methods has not been studied. In this paper, we evaluate the effectiveness of alternative LBIST flows by a case study on a real industrial design. Our results can guide the selection of the best LBIST flow for a given set of design constraints such as test coverage, area overhead, and test time.

Keyword
LBIST, LFSR, manufacturing test, top-off patterns
National Category
Computer Science
Research subject
Computer Science
Identifiers
urn:nbn:se:kth:diva-165461 (URN)10.1109/NORCHIP.2014.7004708 (DOI)2-s2.0-84921483971 (Scopus ID)9781479954421 (ISBN)
Conference
32nd Nordic Microelectronics Conference (NORCHIP'2014)
Funder
Swedish Foundation for Strategic Research
Note

QC 20150508

Available from: 2015-04-28 Created: 2015-04-28 Last updated: 2015-06-08Bibliographically approved
5. A Scan Partitioning Algorithm for Reducing Capture Power of Delay-Fault LBIST
Open this publication in new window or tab >>A Scan Partitioning Algorithm for Reducing Capture Power of Delay-Fault LBIST
2015 (English)In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), 2015, 2015, 842-847 p.Conference paper, Published paper (Refereed)
Keyword
BIST, delay-fault, Capture Power, scan partitioning
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-165462 (URN)2-s2.0-84945946794 (Scopus ID)
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE'2015)
Note

QC 20150508

Available from: 2015-04-28 Created: 2015-04-28 Last updated: 2015-05-08Bibliographically approved

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