A PRET microarchitecture implementation with repeatable timing and competitive performance
2012 (English)In: Proceedings of the 30th IEEE International Conference on Computer Design (ICCD 2012), IEEE conference proceedings, 2012, 87-93 p.Conference paper (Refereed)
We contend that repeatability of execution times is crucial to the validity of testing of real-time systems. However, computer architecture designs fail to deliver repeatable timing, a consequence of aggressive techniques that improve average-case performance. This paper introduces the Precision-Timed ARM (PTARM), a precision-timed (PRET) microarchitecture implementation that exhibits repeatable execution times without sacrificing performance. The PTARM employs a repeatable thread-interleaved pipeline with an exposed memory hierarchy, including a repeatable DRAM controller. Our benchmarks show an improved throughput compared to a single-threaded in-order five-stage pipeline, given sufficient parallelism in the software.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2012. 87-93 p.
IdentifiersURN: urn:nbn:se:kth:diva-163783DOI: 10.1109/ICCD.2012.6378622ISBN: 978-1-4673-3051-0OAI: oai:DiVA.org:kth-163783DiVA: diva2:803868
IEEE 30th International Conference on Computer Design(ICCD 2012), 30 september - 3 October 2012, Montreal, QC, Canada
QC 201505212015-04-142015-04-122015-05-21Bibliographically approved