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Fault-Tolerant Nostrum NoC on FPGA for theForSyDe/NoC System Generator Tool Suite
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. (Electronic Systems)
2014 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Moore’s law is the observation that over the years, the transistor density will increase,allowing billions of transistors to be integrated on a single chip. Over the lasttwo decades, Moore’s law has enabled the implementation of complex systems on asingle chip(SoCs). The challenge of the System-on-Chip(SoC) era was the demandof an efficient communication mechanism between the growing number of processingcores on the chip. The outcome established an new interconnection scheme (amongothers, like crossbars, rings, buses) based on the telecommunication networks andthe Network- on-Chip(NoC) appeared on the scene.The NoC has been developed not only to support systems embedded into asingle processor, but also to support a set of processors embedded on a singlechip.Therefore, the Multi-Processors System on Chip(MPSoC) has arisen, whichincorporate processing elements, memories and I/O with a fixed interconnection infrastructurein a complete integrated system. In such systems, the NoC constitutesthe backbone of the communication architecture that targets future SoC composedby hundred of processing elements. Besides that, together with the deep sub-microntechnology progress, some drawbacks have arisen. The communication efficiencyand the reliability of the systems rely on the proper functionality of NoC for onchipdata communication. A NoC must deal with the susceptibility of transistors tofailure that indicates the demand for a fault tolerant communication infrastructure.A mechanism that can deal with the existence of different classes of faults(transient,intermittent and permanent [11]) which can occur in the communication network.In this thesis, different algorithms are investigated that implement fault toleranttechniques for permanent faults in the NoC. The outcome would be to deliver a faulttolerantmechanism for the NoC System Generator Tool [29] which is a researchin Network-on-Chip carried out at the Royal Institute of Technology. It will beexplicitly described the fault tolerant algorithm that is implemented in the switchin order to achieve packet rerouting around the faulty communication links.

Place, publisher, year, edition, pages
2014. , 64 p.
TRITA-ICT-EX, 2014:187
Keyword [en]
Fault-Tolerant, Nostrum, Network-on-Chip, FPGA, ForSyDe
National Category
Embedded Systems
URN: urn:nbn:se:kth:diva-163426OAI: diva2:800428
Subject / course
Electronic- and Computer Systems
Educational program
Master of Science - System-on-Chip Design
Available from: 2015-04-07 Created: 2015-04-04 Last updated: 2015-04-07Bibliographically approved

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